Cypress CY7B992 - Manual

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Page 2 – Signal Name; “Test Mode”
Page 3 – Block Diagram Description; Phase Frequency Detector and Filter; Table 1; Skew Select Matrix; Table 2
Page 4 – Test Mode; “Skew Select; Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output
Page 5 – Range; Commercial
Page 6 – Electrical Characteristics
Page 7 – Capacitance; Parameter; Input Capacitance; pF; AC Test Loads and Waveforms
Page 8 – Switching Characteristics
Page 11 – AC Timing Diagrams
Page 12 – Operational Mode Descriptions; Figure 2; Figure 2. Zero Skew and Zero Delay Clock Driver
Page 13 – Figure 4. Inverted Output Connections
Page 15 – Figure 8
Page 16 – Ordering Information; Accuracy
Page 17 – Military Specifications; Group A Subgroup Testing; DC Characteristics; Package Diagrams; Figure 9. 32-Pin Plastic Leaded Chip Carrier
Page 18 – Figure 10. 32-Pin Rectangular Leadless Chip Carrier
Page 19 – Document History; Issue Date

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CY7B991
CY7B992

Programmable Skew Clock Buffer

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Document Number: 38-07138 Rev. *B

Revised June 22, 2007

Features

■

All output pair skew <100 ps typical (250 maximum)

■

3.75 to 80 MHz output operation

■

User selectable output functions

❐

Selectable skew to 18 ns

❐

Inverted and non-inverted

❐

Operation at 1

⁄

2 and 1

⁄

4 input frequency

❐

Operation at 2x and 4x input frequency (input as low as 3.75
MHz)

■

Zero input to output delay

■

50% duty cycle outputs

■

Outputs drive 50

terminated lines

■

Low operating current

■

32-pin PLCC/LCC package

■

Jitter < 200 ps peak-to-peak (< 25 ps RMS)

Functional Description

The CY7B991 and CY7B992 Programmable Skew Clock Buffers
(PSCB) offer user selectable control over system clock functions.
These multiple output clock drivers provide the system integrator
with functions necessary to optimize the timing of high perfor-
mance computer systems. Each of the eight individual drivers,
arranged in four pairs of user controllable outputs, can drive
terminated transmission lines with impedances as low as 50

They can deliver minimal and specified output skews and full
swing logic levels (CY7B991 TTL or CY7B992 CMOS).

Each output is hardwired to one of the nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are determined
by the operating frequency with outputs that skew up to ±6 time
units from their nominal “zero” skew position. The completely
integrated PLL allows cancellation of external load and trans-
mission line delay effects. When this “zero delay” capability of the
PSCB is combined with the selectable output skew functions,
you can create output-to-output delays of up to ±12 time units.

Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
enable distribution of a low frequency clock that are multiplied by
two or four at the clock destination. This facility minimizes clock
distribution difficulty, allowing maximum system clock speed and
flexibility.

Logic Block Diagram

TEST

REF

VCO AND

TIME UNIT

GENERATOR

SELECT

INPUTS

(THREE

LEVEL)

SKEW

SELECT

MATRIX

4F0
4F1

3F0
3F1

2F0
2F1

1F0
1F1

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

FILTER

PHASE

FREQ

DET

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Summary

Page 2 - Signal Name; “Test Mode”

CY7B991CY7B992 Document Number: 38-07138 Rev. *B Page 2 of 19 Pin Configuration Pin Definitions Signal Name IO Description REF I Reference frequency input. This input supplies the frequency and timing against which all functional variations are measured. FB I PLL feedback input (typically connected ...

Page 3 - Block Diagram Description; Phase Frequency Detector and Filter; Table 1; Skew Select Matrix; Table 2

CY7B991CY7B992 Document Number: 38-07138 Rev. *B Page 3 of 19 Block Diagram Description Phase Frequency Detector and Filter The Phase Frequency Detector and Filter blocks accept inputsfrom the reference frequency (REF) input and the feedback (FB)input and generate correction information to control t...

Page 4 - Test Mode; “Skew Select; Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output

CY7B991CY7B992 Document Number: 38-07138 Rev. *B Page 4 of 19 Test Mode The TEST input is a three level input. In normal systemoperation, this pin is connected to ground, enabling theCY7B991 or CY7B992 to operate as explained in “Skew Select Matrix” on page 3 . For testing purposes, any of the three...