Cypress CY62138FV30 - Manual
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Table of Contents:
- Page 2 – Top View; TSOP I; STSOP; Note
- Page 3 – Maximum Ratings; Electrical Characteristics; Notes
- Page 4 – THEVENIN; DATA RETENTION MODE; CE
- Page 5 – Switching Characteristics
- Page 6 – Switching Waveforms; Read Cycle 1
- Page 7 – Truth Table; SB; Data Out; Output Disabled; Data in
- Page 8 – Ordering Information; Industrial; Package Diagrams
- Page 13 – Document History Page; Issue; CCDR
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 001-08029 Rev. *E
Revised March 26, 2007
CY62138FV30 MoBL
®
2-Mbit (256K x 8) Static RAM
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62138CV25/30/33
• Ultra low standby power
— Typical standby current: 1
µ
A
— Maximum standby current: 5
µ
A
• Ultra low active power
— Typical active current: 1.6 mA @ f = 1 MHz
• Easy memory expansion with CE
1
, CE
2,
and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin
SOIC, 32-pin TSOP I and 32-pin STSOP packages
Functional Description
The CY62138FV30 is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption. Place the device into standby
mode reducing power consumption when deselected (CE
1
HIGH or CE
2
LOW).
To write to the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins (IO
0
through IO
7
) is then written into the location
specified on the address pins (A
0
through A
17
).
To read from the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appear on
the IO pins.
The eight input and output pins (IO
0
through IO
7
) are placed
in a high impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW and CE
2
HIGH and WE
LOW).
Logic Block Diagram
A0
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A7
A8
A9
SENSE AMPS
POWER
DOWN
WE
OE
A
13
A
14
A
15
A
16
ROW DECODER
COLUMN DECODER
256K x 8
ARRAY
DATA IN DRIVERS
A10
A11
A
17
CE1
CE2
A
12
Note
1. For best practice recommendations, refer to the Cypress application note
“System Design Guidelines”
at
http://www.cypress.com.
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Summary
Document #: 001-08029 Rev. *E Page 2 of 13 CY62138FV30 MoBL ® Pin Configuration [2] Product Portfolio Product V CC Range (V) Speed (ns) Power Dissipation Operating I CC (mA) Standby I SB2 ( µ A) f = 1 MHz f = f max Min Typ [3] Max Typ [3] Max Typ [3] Max Typ [3] Max CY62138FV30LL 2.2 3.0 3.6 45 1.6 ...
Document #: 001-08029 Rev. *E Page 3 of 13 CY62138FV30 MoBL ® Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.Storage Temperature .................................. –65°C to +150°CAmbient Temperature with Power Applied ...........
Document #: 001-08029 Rev. *E Page 4 of 13 CY62138FV30 MoBL ® Thermal Resistance [8] Parameter Description Test Conditions SOIC VFBGA TSOP II STSOP TSOP I Unit Θ JA Thermal Resistance (Junction to Ambient) Still air, soldered on a 3 x 4.5 inch, two layer printed circuit board 44.53 38.49 44.16 59.72...
