Cypress CY62126EV30 - Manual
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Table of Contents:
- Page 2 – MoBL; Pin Configurations; CC
- Page 3 – Maximum Ratings; Electrical Characteristics
- Page 4 – Thermal Resistance; DATA RETENTION MODE; CE
- Page 5 – Switching Characteristics
- Page 6 – Switching Waveforms; PREVIOUS DATA VALID; ADDRESS
- Page 9 – Truth Table
- Page 10 – Package Diagrams
- Page 12 – Document History Page; Date
- Page 13 – Worldwide Sales and Design Support
MoBL
®
,CY62126EV30
1-Mbit (64K x 16) Static RAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05486 Rev. *E
Revised January 5, 2009
Features
■
High speed: 45 ns
■
Temperature ranges
❐
Industrial: –40°C to +85°C
❐
Automotive: –40°C to +125°C
■
Wide voltage range: 2.2V to 3.6V
■
Pin compatible with CY62126DV30
■
Ultra low standby power
❐
Typical standby current: 1
μ
A
❐
Maximum standby current: 4
μ
A
■
Ultra low active power
❐
Typical active current: 1.3 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed and power
■
Offered in Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
Functional Description
The CY62126EV30 is a high performance CMOS static RAM
organized as 64K words by 16 bits
. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life
™
(MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (IO
0
through IO
15
) are placed in a high impedance
state when:
■
Deselected (CE HIGH)
■
Outputs are disabled (OE HIGH)
■
Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■
Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO
0
through IO
7
) is written into the location
specified on the address pins (A
0
through A
15
). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO
8
through IO
15
)
is written into the location specified on the address pins (A
0
through A
15
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO
0
to IO
7
. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO
8
to IO
15
complete description of read and write modes.
Note
1. For best practice recommendations, refer to the Cypress application note
AN1064, SRAM System Guidelines.
Logic Block Diagram
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Summary
MoBL ® , CY62126EV30 Document #: 38-05486 Rev. *E Page 2 of 13 Pin Configurations Figure 1. 44-Ball VFBGA (Top View) Figure 2. 44-Pin TSOP II (Top View) [2] Table 1. Product Portfolio Notes 2. NC pins are not connected on the die.3. Typical values are included for reference only and are not guarante...
MoBL ® , CY62126EV30 Document #: 38-05486 Rev. *E Page 3 of 13 Maximum Ratings Exceeding maximum ratings may shorten the battery life of the device. These user guidelines are not tested.Storage Temperature ................................. –65°C to +150°CAmbient Temperature with Power Applied .........
MoBL ® , CY62126EV30 Document #: 38-05486 Rev. *E Page 4 of 13 Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Test Conditions VFBGA Package TSOP II Package Unit Θ JA Thermal Resistance (Junction to Ambient) Still Ai...
