Cypress CY25822-2 - Manual

Cypress CY25822-2

Cypress CY25822-2 – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.

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Table of Contents:

  • Page 4 – Bytes 2 through 5: Reserved Registers
  • Page 5 – CLKOUT and REFOUT Enable Clarification; The CLKOUT enable and REFOUT enable I
  • Page 7 – Ordering Information
  • Page 8 – Package Diagram; Purchase of I
  • Page 9 – Document History Page; Issue; RGL
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CK-SSC Spread Spectrum Clock Generator

CY25822-2

Cypress Semiconductor Corporation

3901 North First Street

San Jose

,

CA 95134

408-943-2600

Document #: 38-07531 Rev. **

Revised March 18, 2003

Features

• 3.3V operation
• 48- and 66-MHz frequency support
• Selectable slew rate control
• 350-pS jitter
• I

2

C programmability

• 500-

µ

A power-down current

• Spread Spectrum for best electromagnetic interference

(EMI) reduction

• 8-pin SOIC package

Block Diagram

Pin Configuration

1

2

3

4

8

7

6

5

C L K I N

V D D

G N D

* P W R D W N #

S C L O C K

S D A T A

R E F O U T

C Y 2 5 8 2 2 - 2

C L K O U T

* 1 5 0 K

P u l l - u p

Freq.

Phase

Modulating

VCO

Post

CLKOUT

Detector

Charge

Pump

Waveform

Dividers

Divider

Feedback

Divider

PLL

GND

VDD

Σ

M

N

Clock Input

(SSCG Output)

REFOUT

Logic

Control

SDATA

SCLOCK

PWRDWN#

[+] Feedback

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Summary

Page 4 - Bytes 2 through 5: Reserved Registers

CY25822-2 Document #: 38-07531 Rev. ** Page 4 of 9 Bytes 2 through 5: Reserved Registers PWRDWN# (Power-down) Clarification The PWRDWN# (Power-down) pin is used to shut off ALLclocks prior to shutting off power to the device. PWRDWN# isan asynchronous active LOW input. This signal is synchro-nized i...

Page 5 - CLKOUT and REFOUT Enable Clarification; The CLKOUT enable and REFOUT enable I

CY25822-2 Document #: 38-07531 Rev. ** Page 5 of 9 CLKOUT and REFOUT Enable Clarification The CLKOUT enable and REFOUT enable I 2 C register bits are used to shot-off the CLKOUT and REFOUT clocks individually.The VCO and crystal oscillator must remain on. A shutdownclock is driven low. ALL clocks ne...

Page 7 - Ordering Information

CY25822-2 Document #: 38-07531 Rev. ** Page 7 of 9 t FALLL1 Falling Edge Rate Measured from 2.4V to 0.4VREFOUT and CLOCKOUT 1.33 4.0 V/ns Low Buffer StrengthRefer to I 2 C Control t RISEH2 Rise Time Measured from 0.4V to 2.4VREFOUT and CLOCKOUT 0.4 1.0 ns High Buffer StrengthRefer to I 2 C Control t...

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