Cypress CY25819 - Manual
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Table of Contents:
- Page 2 – Table 1; Pin Description; Table 2
- Page 3 – -Level Digital Inputs; Figure 1; Modulation Rate; Table 3; Maximum Ratings
- Page 4 – Characteristics Curves; Table 4; Table 5. Timing Electrical Characteristics
- Page 5 – SSCG Profiles; Figure 6; Application Schematic; Figure 6. CY25818 Spread Spectrum Profile; V d d; V s s; R E F C L K; Figure 8. Typical Application Schematic
- Page 6 – Part Number; -pin SOIC–Tape and Reel
- Page 7 – Document History Page; Issue
Spread Spectrum Clock Generator
CY25818/19
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-07362 Rev. *B
Revised April 11, 2006
Features
• 8- to 32-MHz input frequency range
• CY25818: 8–16 MHz
• CY25819: 16–32 MHz
• Separate modulated and unmodulated clocks
• Accepts clock, crystal, and resonator inputs
• Down spread modulation
• Power-down function
• Low-power dissipation
— CY25818 = 33 mW-typ @ 8 MHz
— CY25818 = 56 mW-typ @ 16 MHz
— CY25819 = 36 mW-typ @ 16 MHz
— CY25819 = 63 mW-typ @ 32 MHz
• Low cycle-to-cycle jitter
— SSCLK = 250 ps-typ
— REFOUT = 275 ps-typ
• Available in 8-pin (150-mil) SOIC package
Applications
• Printers and MFPs
• LCD panels and notebook PCs
• Digital copiers
• PDAs
• Automotive
• CD-ROM, VCD, and DVD
• Networking and LAN/WAN
• Scanners
• Modems
• Embedded digital systems
Benefits
• Peak electromagnetic interference (EMI) reduction by
8–16 dB
• Fast time to market
• Cost reduction
REFERENCE
DIVIDER
PD and
CP
LF
VCO
DIVIDER
and
M UX
INPUT
DECODER
1
8
300K
M ODULATION
CONTROL
3
6
S0 PD#
XIN/CLKIN
XOUT
VDD
7
VSS
2
4
SSCLK
5
REFCLK
VCO
COUNTER
2
1
3
4
8
7
6
5
XIN/CLKIN
Vss
S0
SSCLK
XOUT
Vdd
PD#
REFCLK
CY25818
CY25819
8 Pin SOIC
8-pin SOIC
Block Diagram
Pin Configuration
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Summary
CY25818/19 Document #: 38-07362 Rev. *B Page 2 of 7 . Overview The Cypress CY25818/19 products are Spread SpectrumClock Generator (SSCG) ICs used for the purpose of reducingEMI found in today’s high-speed digital electronic systems.The devices use a Cypress proprietary phase-locked loop(PLL) and Spr...
CY25818/19 Document #: 38-07362 Rev. *B Page 3 of 7 3-Level Digital Inputs S0 digital input is designed to sense three logic levels desig-nated as HIGH “1,” LOW “0,” and MIDDLE “M.” With this3-Level digital input logic, the 3-Level logic is able to detectthree different logic levels. The S0 pin incl...
CY25818/19 Document #: 38-07362 Rev. *B Page 4 of 7 Characteristics Curves The following curves demonstrate the characteristic behaviorof the CY25818/19 when tested over a number of environ-mental and application specific parameters. These are typicalperformance curves and are not meant to replace a...
