Cypress CY25566 - Manual
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Table of Contents:
- Page 3 – Figure 1; Control Logic Structures; REFOFF; Figure 2; SSCC; Figure 1. SSCLK1a/b Driver Configurations
- Page 4 – Modulation Rate; CDiv
- Page 6 – Application Schematic; Table 1; 5 MHz Clock source; Figure 4. Application Schematic
- Page 7 – Absolute Maximum Ratings
- Page 8 – Part Number; 6-pin SOIC–Tape and Reel
Spread Spectrum Clock Generator
CY25566
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07429 Rev. *B
Revised October 26, 2005
Features
• 25- to 200-MHz operating frequency range
• Wide range of spread selections (9)
• Accepts clock or crystal inputs
• Provides four clocks
— SSCLK1a
— SSCLK1b
— SSCLK2
— REFOUT
• Low-power dissipation
— 3.3V = 70 mW (typical @ 40 MHz, no load)
• Center spread modulation
• Low cycle-to cycle jitter
• 16-pin SOIC package
Applications
• High-resolution VGA controllers
• LCD panels and monitors
• Printers and MFPs
Benefits
• Peak EMI reduction by 8 to 16 dB
• Fast time to market
•
Cost reduction
Block Diagram
Pin Configuration
1
16
15
14
13
9
8
7
6
5
4
3
2
10
11
12
XIN/CLKIN
REFOFF
VDD
VSS
S2
S3
SSCLK1a
REFOUT
SSCLK1b
SSCC
VSS
S1
S0
VSS
SSCLK2
XOUT
C
Y
25566
3
PD
REFERENCE
DIVIDER
Loop
Filter
1
4
MODULATION
CONTROL
INPUT
DECODER
LOGIC
FEEDBACK
DIVIDER
vco
DIVIDER
&
MUX
16
5
CP
SSCLK1a
S0
S1
12
13
10
8
20 K
20 K
20 K
20 K
SSCC
VDD
VSS
Xout
Xin/
CLK
VDD
VDD
VSS
VSS
300K
14
11
VSS
VSS
RANGE
CONTROL
6
7
S3
S2
9
15
SSCLK1b
SSCLK2
/2
2
REFOUT
REFOFF
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Summary
CY25566 Document #: 38-07429 Rev. *B Page 3 of 9 SSCLK1a/b SSCLK1a and SSCLK1b are spread spectrum clock outputsused for the purpose of reducing EMI in digital systems.SSCLK1a and SSCLK1b can be connected in several differentways to provide flexibility in application designs. Each clockcan drive sep...
CY25566 Document #: 38-07429 Rev. *B Page 4 of 9 Modulation Rate Spread Spectrum clock generators utilize frequencymodulation (FM) to distribute energy over a specific band offrequencies. The maximum frequency of the clock (Fmax) andminimum frequency of the clock (Fmin) determine this band offrequen...
CY25566 Document #: 38-07429 Rev. *B Page 6 of 9 Application Schematic In this example, the CY25566 is being driven by a 75-MHzreference clock. S0 = 0 and S1 = 0 are programmed to select a BW of 2.5%.(Refer to Table 1 and 2. ) S2 = 0 and S3 = 1 are programmed to select the Group 2range. V DD = 3.30 ...
