Cypress CY24713 - Manual
Cypress CY24713 – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 2 – Recommended Operating Conditions
- Page 3 – AC Electrical Characteristics; Figure 3; Figure 4; Figure 4; CLK
- Page 4 – Ordering Code
- Page 5 – Document History Page; Worldwide Sales and Design Support; Change
CY24713
Set-top Box Clock Generator with VCXO
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-07396 Rev. *A
Revised May 22, 2008
Features
■
Integrated phase-locked loop (PLL)
■
Low-jitter, high-accuracy outputs
■
VCXO with analog adjust
■
3.3V Operation
■
8-pin SOIC
Benefits
■
High-performance PLL tailored for Set Top Box applications
■
Meets critical timing requirements in complex system designs
■
Large ±150-ppm range, better linearity
■
Meet industry standard voltage platforms
■
Industry standard packaging saves on board space
Pin Configuration
Figure 1. CY24713, 8-Pin SOIC
Part Number
Outputs
Input Frequency Range
Output Frequencies
CY24713
3
27-MHz pullable crystal input
per Cypress specification
4.9152 MHz, 13.5 MHz, 27 MHz
Logic Block Diagram
Table 1. Pin Definition
Name
Number
Description
XIN
1
Reference Crystal Input
VDD
2
3.3V Voltage Supply
VCXO
3
Input Analog Control for VCXO
VSS
4
Ground
CLK_B
5
13.5-MHz Clock Output
CLK_A
6
4.9152-MHz Clock Output
CLK_C
7
27-MHz Clock Output
XOUT
8
Reference Crystal Output
Note
1. Float X
OUT
if X
IN
is externally driven.
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Summary
CY24713 Document #: 38-07396 Rev. *A Page 2 of 5 Absolute Maximum Conditions Parameter Description Min Max Unit V DD Supply Voltage –0.5 7.0 V T S Storage Temperature [2] –65 125 °C T J Junction Temperature – 125 °C Digital Inputs V SS – 0.3 V DD + 0.3 V Digital Outputs referred to V DD V SS – 0.3 V...
CY24713 Document #: 38-07396 Rev. *A Page 3 of 5 AC Electrical Characteristics (V DD = 3.3V) Parameter [3] Description Conditions Min Typ. Max Unit DC Output Duty Cycle Duty Cycle is defined in Figure 3 50% of V DD 45 50 55 % ER 0 Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of ...
CY24713 Document #: 38-07396 Rev. *A Page 4 of 5 Package Diagram Figure 5. 8-Lead (150-Mil) SOIC S8 Ordering Information Ordering Code Package Type Operating Range Operating Voltage CY24713SC [4] 8-pin SOIC Commercial 3.3V CY24713SCT [4] 8-pin SOIC Commercial 3.3V Pb-free CY24713SXC [4] 8-pin SOIC C...
