Cypress CY24272 - Manual
Cypress CY24272 – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 2 – Pinouts; Name
- Page 4 – Device ID and SMBus Device Address; Table 4; SMBus Protocol; Table 6; RegB
- Page 5 – Table 3
- Page 6 – Absolute Maximum Conditions; D iffe re n tia l In p u t
- Page 7 – DC Operating Conditions
- Page 9 – AC Electrical Specification
- Page 10 – Test and Measurement Setup; Figure 3. Clock Outputs; Signal Waveforms; Figure 4; Jitter; Figure 6; Channel; Parameter
- Page 11 – CLK
- Page 12 – Part Number; Commercial, 0°C to 70°C
- Page 13 – Document History Page; See ECN
CY24272
Rambus
®
XDR™ Clock Generator with
Zero SDA Hold Time
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-42414 Rev. **
Revised November 9, 2007
Features
■
Meets Rambus
®
Extended Data Rate (XDR™) clocking
requirements
■
25 ps typical cycle-to-cycle jitter
❐
–135 dBc/Hz typical phase noise at 20 MHz offset
■
100 or 133 MHz differential clock input
■
300–667 MHz high speed clock support
■
Quad (open drain) differential output drivers
■
Supports frequency multipliers: 3, 4, 5, 6, 9/2 and 15/4
■
Spread Aware™
■
2.5V operation
■
28-pin TSSOP package
Table 1. Device Comparison
CY24271
CY24272
SDA hold time = 300 ns
(SMBus compliant)
SDA hold time = 0 ns
(I
2
C compliant)
R
RC
= 200
Ω
typical
(Rambus standard drive)
R
RC
= 295
Ω
minimum
(Reduced output drive)
CLK0
CLK0B
CLK1
CLK1B
CLK2
CLK2B
CLK3
CLK3B
REFCLK,REFCLKB
SCL
SDA
ID0
ID1
EN
RegA
EN
RegB
EN
RegC
EN
RegD
PLL
Bypass
MUX
/BYPASS
EN
Logic Block Diagram
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Summary
CY24272 Document Number: 001-42414 Rev. ** Page 2 of 13 Pinouts Table 2. Pin Definition - 28 Pin TSSOP Pin No. Name IO Description 1 VDDP PWR 2.5V power supply for phased lock loop (PLL) 2 VSSP GND Ground 3 ISET I Set clock driver current (external resistor) 4 VSS GND Ground 5 REFCLK I Reference clo...
CY24272 Document Number: 001-42414 Rev. ** Page 4 of 13 Device ID and SMBus Device Address The device ID (ID0 and ID1) is a part of the SMBus device 8-bitaddress. The least significant bit of the address designates awrite or read operation. Table 4 on page 3 shows the addresses for four CY24272 devi...
CY24272 Document Number: 001-42414 Rev. ** Page 5 of 13 Note 5. RW = Read and Write, RO = Read Only, POD = Power on default. See Table 3 on page 3 for PLL multipliers and Table 5 on page 4 for clock output selections. Table 6. Command Code 80h [5] Bit Register POD Type Description 7 Reserved 0 RW Re...
