Cypress CY24271 - Manual - manualsarea.com

Page 2 - Pinouts; Name

CY24272 Document Number: 001-42414 Rev. ** Page 2 of 13 Pinouts Table 2. Pin Definition - 28 Pin TSSOP Pin No. Name IO Description 1 VDDP PWR 2.5V power supply for phased lock loop (PLL) 2 VSSP GND Ground 3 ISET I Set clock driver current (external resistor) 4 VSS GND Ground 5 REFCLK I Reference clo...

Page 4 - Device ID and SMBus Device Address; Table 4; SMBus Protocol; Table 6; RegB

CY24272 Document Number: 001-42414 Rev. ** Page 4 of 13 Device ID and SMBus Device Address The device ID (ID0 and ID1) is a part of the SMBus device 8-bitaddress. The least significant bit of the address designates awrite or read operation. Table 4 on page 3 shows the addresses for four CY24272 devi...

Page 5 - Table 3

CY24272 Document Number: 001-42414 Rev. ** Page 5 of 13 Note 5. RW = Read and Write, RO = Read Only, POD = Power on default. See Table 3 on page 3 for PLL multipliers and Table 5 on page 4 for clock output selections. Table 6. Command Code 80h [5] Bit Register POD Type Description 7 Reserved 0 RW Re...

Page 6 - Absolute Maximum Conditions; D iffe re n tia l In p u t

CY24272 Document Number: 001-42414 Rev. ** Page 6 of 13 Figure 2. Differential and Single-Ended Clock Inputs Absolute Maximum Conditions Parameter Description Condition Min Max Unit V DD Clock Buffer Supply Voltage –0.5 4.6 V V DDC Core Supply Voltage –0.5 4.6 V V DDP PLL Supply Voltage –0.5 4.6 V V...

Page 7 - DC Operating Conditions

CY24272 Document Number: 001-42414 Rev. ** Page 7 of 13 DC Operating Conditions Parameter Description Condition Min Max Unit V DDP Supply Voltage for PLL 2.5V ± 5% 2.375 2.625 V V DDC Supply Voltage for Core 2.5V ± 5% 2.375 2.625 V V DD Supply Voltage for Clock Buffers 2.5V ± 5% 2.375 2.625 V V IHCL...

Page 9 - AC Electrical Specification

CY24272 Document Number: 001-42414 Rev. ** Page 9 of 13 AC Electrical Specification The AC Electrical specifications follow. [6] Parameter Description Min Typ Max Unit t CYCLE Clock Cycle time [19] 1.25 3.34 ns t JIT(cc) Jitter over 1-6 clock cycles at 400–635 MHz [20] – 25 40 ps Jitter over 1-6 clo...

Page 10 - Test and Measurement Setup; Figure 3. Clock Outputs; Signal Waveforms; Figure 4; Jitter; Figure 6; Channel; Parameter

CY24272 Document Number: 001-42414 Rev. ** Page 10 of 13 Test and Measurement Setup Figure 3. Clock Outputs Signal Waveforms A physical signal that appears at the pins of a device is deemedvalid or invalid depending on its voltage and timing relations withother signals. Input and output voltage wave...

Page 11 - CLK

CY24272 Document Number: 001-42414 Rev. ** Page 11 of 13 Figure 4. Input and Output Waveforms Figure 5. Crossing Point Voltage Figure 6. Cycle-to-cycle Jitter Figure 7. Cycle-to-cycle Duty-cycle Error V H t R t F 8 0 % 2 0 % V L V ( t ) Vx.nom CLK CLKB Vx+ Vx- CLK CLKB t CYCLE,i t CYCLE,i+1 t J = t ...

Page 12 - Part Number; Commercial, 0°C to 70°C

CY24272 Document Number: 001-42414 Rev. ** Page 12 of 13 Package Drawing and Dimension Figure 8. 28-Pin Thin Shrunk Small Outline Package (4.40-mm Body) ZZ28 Ordering Information Part Number Package Type Product Flow Pb-Free CY24272ZXC 28-pin TSSOP Commercial, 0°C to 70°C CY24272ZXCT 28-pin TSSOP – ...

Page 13 - Document History Page; See ECN

Document Number: 001-42414 Rev. ** Revised November 9, 2007 Page 13 of 13 PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registeredtrademarks referenced herein are property of t...

Cypress CY24271 - Manual

Table of Contents:

Summary

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