Cypress CY2048WAF - Manual
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Table of Contents:
- Page 2 – Die Pad Summary; Name
- Page 4 – AC Electrical Specifications; DD; Crystal Oscillator Tuning Capacitor Values
- Page 5 – Timing Parameters; Parameter; Figure 3. Output Enable Timing; POWER
- Page 6 – VDD; LOAD; GND; Ordering Information; Ordering Code; Wafer; Figure 5. Duty Cycle Definition; Clock
- Page 7 – Document History Page; Change; See ECN
Flash Programmable Capacitor Tuning Array Die
for Crystal Oscillator(XO)
CY2048WAF
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Document #: 38-07738 Rev. *A
Revised December 12, 2005
Features
• Flash-programmable capacitor tuning array for low
ppm initial frequency clock output
• Low clock output jitter
— 4 ps typ. RMS period jitter
— ±30 ps typ. peak-to-peak period jitter
• Flash-programmable dividers
• Two-pin programming interface
• On-chip oscillator runs from 10–48-MHz crystal
• Five selectable post-divide options, using reference
oscillator output
• Programmable asynchronous or synchronous OE and
PWR_DWN modes
• 2.7V to 3.6V operation
• Controlled rise and fall times and output slew rate
Benefits
• Enables fine-tuning of output clock frequency by
adjusting C
Load
of the crystal
• Allows multiple programming opportunities to correct
errors, and control excess inventory
• Enables programming of output frequency after
packaging
• PPM clock output error can be adjusted in package
• Provides flexibility in output configurations and testing
• Enables low-power operation or output enable function
• Provides flexibility for system applications through
selectable instantaneous or synchronous change in
outputs
•
Enables encapsulation in small-size, surface-mount
packages
Block Diagram
Die Pad Description
H o r i z o n t a l S c r i b e
V e r t i c a l
S c r i b e
Y ( m a x )
X ( m a x )
6
O U T
2
3
4
V D D
X I N
P D # / O E
5
7 C 8 0 3 3 0 A
1
X O U T
d i e # / r e v
V S S
Notes
:
X(max): 980
µ
m, Y(max): 988
µ
m
Bond pad opening: 85
µ
m x 85
µ
m
Pad pitch: 175
µ
m (min.)
Scribe: X = 70
µ
m, Y = 86
µ
m
Wafer thickness: 11 mils (Typ.)
PD#/OE
VSS
VDD
(SDATA/VPP)
XIN
XOUT
CRYSTAL
OUT
/ 1, 2, 4, 8, 16
OSCILLATOR
CONFIGURATION
(SCL)
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Summary
CY2048WAF Document #: 38-07738 Rev. *A Page 2 of 7 Die Pad Summary (Pad coordinates are referenced from the center of the die (X = 0, Y = 0)) Name Pad Number Description X coordinate ( µ m) Y coordinate ( µ m) VDD 1 Voltage Supply –360.8 353.7 XOUT 2 Oscillator Drain –360.8 134.1 XIN 3 Oscillator Ga...
CY2048WAF Document #: 38-07738 Rev. *A Page 4 of 7 Notes: 2. T PJ2 measured using DTS-2075, # of events set to 10, 000. AC Electrical Specifications [1] over the operating range, except as noted Parameter [1] Description Condition Min. Typ. Max. Unit F OUT Output Frequency 0.625 – 48 MHz DC Output D...
CY2048WAF Document #: 38-07738 Rev. *A Page 5 of 7 Timing Parameters over the operating range Parameter Description Min. Max. Unit T STP,SYNC Time from falling edge on PD# to stopped output, synchronous mode, T=1/F out 1.5T + 350 ns T STP,ASYNC Time from falling edge on PD# to stopped output, asynch...
