Cypress CY14E102L - Manual
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Table of Contents:
- Page 2 – ADVANCE; Pinouts
- Page 3 – Pin Definitions
- Page 4 – Device Operation; Figure 4; Figure 4. AutoStore Mode; Hardware STORE Operation
- Page 5 – Software STORE
- Page 6 – Preventing AutoStore; Noise Considerations
- Page 7 – Maximum Ratings; DC Electrical Characteristics
- Page 8 – AC Test Conditions; Thermal Resistance; AC Test Loads; OUTPUT
- Page 9 – AC Switching Characteristics
- Page 10 – AutoStore and Power Up RECALL
- Page 11 – Switching Waveforms
- Page 13 – Figure 9. AutoStore or Power Up RECALL
- Page 14 – Figure 11. OE Controlled Software STORE/RECALL Cycle
- Page 15 – Ordering Information
- Page 17 – Part Numbering Nomenclature; Cypress
- Page 18 – Package Diagrams; TOP VIEW
- Page 21 – Document History Page; Worldwide Sales and Design Support; Change
ADVANCE
CY14E102L, CY14E102N
2-Mbit (256K x 8/128K x 16) nvSRAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-45755 Rev. *A
Revised June 27, 2008
Features
■
15 ns, 20 ns, 25 ns, and 45 ns access times
■
Internally organized as 256K x 8 (CY14E102L) or 128K x 16
(CY14E102N)
■
Hands off automatic STORE
on power down with only a small
capacitor
■
STORE
to QuantumTrap
™
nonvolatile elements initiated by
software, device pin, or AutoStore
™
on power down
■
RECALL
to SRAM initiated by software or power up
■
Infinite read, write, and recall cycles
■
200,000 STORE
cycles to QuantumTrap
■
20 year data retention
■
Single 5V +10% operation
■
Commercial and Industrial temperatures
■
48-pin FBGA, 44 and 54-pin TSOP II packages
■
Pb-free and RoHS compliance
Functional Description
The Cypress CY14E102L/CY14E102N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
organized as 256K words of 8 bits each or 128K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap
technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data reside in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
Note
1. Address A
0
- A
17
and Data DQ0 - DQ7 for x8 configuration, Address A
0
- A
16
and Data DQ0 - DQ15 for x16 configuration.
A
0
- A
17
Address
WE
OE
CE
V
CC
V
SS
V
CAP
DQ0 - DQ7
HSB
CY14E102L
BHE
BLE
Logic Block Diagram
[1]
CY14E102N
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Summary
ADVANCE CY14E102L, CY14E102N Document Number: 001-45755 Rev. *A Page 2 of 21 Pinouts Figure 1. Pin Diagram - 48 FBGA (Top View) Figure 2. Pin Diagram - 44 TSOP II (Top View) WE V CC A 11 A 10 V CAP A 6 A 0 A 3 CE NC NC DQ0 A 4 A 5 NC DQ2 DQ3 NC V SS A 9 A 8 OE V SS A 7 NC NC NC A 17 A 2 A 1 NC V CC ...
ADVANCE CY14E102L, CY14E102N Document Number: 001-45755 Rev. *A Page 3 of 21 Figure 3. Pin Diagram - 54 TSOP II (Top View) Pinouts (continued) NC DQ7 DQ6 DQ5 DQ4 V CC DQ3 DQ2 DQ1 DQ0 NC A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 V CAP WE A 8 A 10 A 11 A 12 A 13 A 14 A 15 A 16 1 2 3 4 5 6 78 9 10 1112 1314 15 1...
ADVANCE CY14E102L, CY14E102N Document Number: 001-45755 Rev. *A Page 4 of 21 Device Operation The CY14E102L/CY14E102N nvSRAM is made up of twofunctional components paired in the same physical cell. They arean SRAM memory cell and a nonvolatile QuantumTrap cell. TheSRAM memory cell operates as a stan...
