Cypress CY14B104M - Manual
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Table of Contents:
- Page 2 – PRELIMINARY; Pinouts; DQ
- Page 3 – Device Operation; “Truth Table For SRAM Operations”; SRAM Read; Figure 2
- Page 4 – Software STORE
- Page 5 – Preventing AutoStore; Table 2. Mode Selection
- Page 6 – Data Protection; Table 4; Note
- Page 7 – Setting the Clock; Calibrating the Clock; Alarm; Watchdog Timer
- Page 8 – Figure 3; Figure 3. Watchdog Timer Block Diagram; Power Monitor; “AutoStore Operation”; Interrupts; Interrupt Register; Watchdog Interrupt Enable - WIE; Flags Register; “Stopping and
- Page 9 – Figure 4. RTC Recommended Component Configuration; WDF - Watchdog Timer Flag
- Page 10 – Table 4. RTC Register Map
- Page 12 – Register; Interrupt Status/Control
- Page 13 – Table 5. Register Map Detail
- Page 14 – Maximum Ratings; DC Electrical Characteristics
- Page 15 – AC Test Conditions; Thermal Resistance; OUTPUT
- Page 17 – AC Switching Characteristics
- Page 18 – Switching Waveforms; Figure 8. SRAM Read Cycle 2: CE Controlled
- Page 19 – Figure 10. SRAM Write Cycle 2: CE Controlled
- Page 20 – AutoStore/Power Up RECALL; RWI
- Page 21 – Software Controlled STORE and RECALL Cycle
- Page 22 – Hardware STORE Cycle; HSB To Output Active Time when write latch not set; Hardware STORE Pulse Width; Write latch set
- Page 23 – Truth Table For SRAM Operations; For x8 Configuration
- Page 24 – Part Numbering Nomenclature; Cypress
- Page 25 – Ordering Information
- Page 26 – Package Diagrams
- Page 28 – Document History Page; Date
- Page 31 – Worldwide Sales and Design Support
PRELIMINARY
CY14B104K, CY14B104M
4 Mbit (512K x 8/256K x 16) nvSRAM with
Real Time Clock
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 001-07103 Rev. *K
Revised January 29, 2009
Features
■
20 ns, 25 ns, and 45 ns access times
■
Internally organized as 512K x 8 (CY14B104K) or 256K x 16
(CY14B104M)
■
Hands off automatic STORE
on power down with only a small
capacitor
■
STORE
to QuantumTrap
®
nonvolatile elements is initiated by
software, device pin, or AutoStore
®
on power down
■
RECALL
to SRAM initiated by software or power up
■
High reliability
■
Infinite Read, Write, and RECALL cycles
■
200,000 STORE
cycles to QuantumTrap
■
20 year data retention
■
Single 3V +20%, –10% operation
■
Data integrity of Cypress nvSRAM combined with full featured
Real Time Clock
■
Watchdog timer
■
Clock alarm with programmable interrupts
■
Capacitor or battery backup for RTC
■
Commercial and industrial temperatures
■
44 and 54-pin TSOP II package
■
Pb-free and RoHS compliance
Functional Description
The Cypress CY14B104K/CY14B104M combines a 4-Mbit
nonvolatile static RAM with a full featured Real Time Clock in a
monolithic integrated circuit. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM is read and
written infinite number of times, while independent nonvolatile
data resides in the nonvolatile elements.
The Real Time Clock function provides an accurate clock with
leap year tracking and a programmable, high accuracy oscillator.
The alarm function is programmable for periodic minutes, hours,
days or months alarms. There is also a programmable watchdog
timer for process control.
STATIC RAM
ARRAY
2048 X 2048
R
O
W
D
E
C
O
D
E
R
COLUMN I/O
COLUMN DEC
I
N
P
U
T
B
U
F
F
E
R
S
POWER
CONTROL
STORE/RECALL
CONTROL
Quatrum
Trap
2048 X 2048
STORE
RECALL
V
CC
V
CA
P
HSB
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
SOFTWARE
DETECT
A
14
- A
2
OE
CE
WE
BHE
BLE
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
17
A
18
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
RTC
MUX
A
18
- A
0
X
1
X
2
INT
V
RTCbat
V
RTCcap
Logic Block Diagram
Notes
1. Address A
0
- A
18
for x8 configuration and Address A
0
- A
17
for x16 configuration.
2. Data DQ
0
- DQ
7
for x8 configuration and Data DQ
0
- DQ
15
for x16 configuration.
3. BHE and BLE are applicable for x16 configuration only.
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Summary
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 2 of 31 Pinouts Figure 1. Pin Diagram - 44-PIn and 54-Pin TSOP II Table 1. Pin Definitions Pin Name I/O Type Description A 0 – A 18 Input Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Configuration . A ...
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 3 of 31 Device Operation The CY14B104K/CY14B104M nvSRAM is made up of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a st...
PRELIMINARY CY14B104K, CY14B104M Document #: 001-07103 Rev. *K Page 4 of 31 power-on-recall, the MPU must be active or the WE held inactive until the MPU comes out of reset.To reduce unnecessary nonvolatile STOREs, AutoStore and Hardware STORE operations are ignored unless at least one write operati...
