Cypress CY14B104LA - Manual

Cypress CY14B104LA

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Table of Contents:

  • Page 2 – PRELIMINARY; Pinouts; Top View; Top View
  • Page 3 – Pin Definitions
  • Page 4 – Device Operation; Truth Table For SRAM Operations; SRAM Read; Figure 4; Figure 4. AutoStore Mode; Hardware STORE Operation
  • Page 5 – Software STORE; Table 1. Mode Selection
  • Page 6 – Preventing AutoStore; Noise Considerations
  • Page 7 – Best Practices
  • Page 8 – Maximum Ratings; DC Electrical Characteristics
  • Page 9 – AC Test Conditions; Thermal Resistance; OUTPUT
  • Page 10 – AC Switching Characteristics
  • Page 13 – AutoStore/Power Up RECALL; RWI
  • Page 14 – Software Controlled STORE/RECALL Cycle; Switching Waveforms
  • Page 15 – Hardware STORE Cycle; HSB To Output Active Time when write latch not set; Hardware STORE Pulse Width; Soft Sequence Processing Time; Write latch set
  • Page 16 – For x8 Configuration
  • Page 17 – Ordering Information
  • Page 19 – Part Numbering Nomenclature; Cypress; Rev
  • Page 20 – Package Diagrams
  • Page 23 – Document History Page; Worldwide Sales and Design Support; Submission
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PRELIMINARY

CY14B104LA, CY14B104NA

4 Mbit (512K x 8/256K x 16) nvSRAM

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

,

CA 95134-1709

•

408-943-2600

Document #: 001-49918 Rev. *A

Revised March 11, 2009

Features

■

20 ns, 25 ns, and 45 ns access times

■

Internally organized as 512K x 8 (CY14B104LA) or 256K x 16
(CY14B104NA)

■

Hands off automatic STORE

on power down with only a small

capacitor

■

STORE

to QuantumTrap

®

nonvolatile elements initiated by

software, device pin, or AutoStore

®

on power down

■

RECALL

to SRAM initiated by software or power up

■

Infinite Read, Write, and Recall cycles

■

200,000 STORE

cycles to QuantumTrap

■

20 year data retention

■

Single 3V +20

%

, -10

%

operation

■

Commercial and industrial temperatures

■

48-ball FBGA and 44/54-pin TSOP-II packages

■

Pb-free and RoHS compliance

Functional Description

The Cypress CY14B104LA/CY14B104NA is a fast static RAM,
with a nonvolatile element in each memory cell. The memory is
organized as 512K bytes of 8 bits each or 256K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap

technology, producing the world’s most reliable

nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.

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Logic Block Diagram

[1, 2, 3]

Notes

1. Address A

0

- A

18

for x8 configuration and Address A

0

- A

17

for x16 configuration.

2. Data DQ

0

- DQ

7

for x8 configuration and Data DQ

0

- DQ

15

for x16 configuration.

3. BHE and BLE are applicable for x16 configuration only.

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Summary

Page 2 - PRELIMINARY; Pinouts; Top View; Top View

PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 2 of 23 Pinouts Figure 1. Pin Diagram - 48 FBGA Figure 2. Pin Diagram - 44 Pin TSOP II WE V CC A 11 A 10 V CAP A 6 A 0 A 3 CE NC NC DQ 0 A 4 A 5 NC DQ 2 DQ 3 NC V SS A 9 A 8 OE V SS A 7 NC NC NC A 17 A 2 A 1 NC V CC DQ 4 NC DQ 5 D...

Page 3 - Pin Definitions

PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 3 of 23 Figure 3. Pin Diagram - 54 Pin TSOP II (x16) Pin Definitions Pin Name I/O Type Description A 0 – A 18 Input Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Configuration . A 0 – A 17 Address Inp...

Page 4 - Device Operation; Truth Table For SRAM Operations; SRAM Read; Figure 4; Figure 4. AutoStore Mode; Hardware STORE Operation

PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev. *A Page 4 of 23 Device Operation The CY14B104LA/CY14B104NA nvSRAM is made up of twofunctional components paired in the same physical cell. They area SRAM memory cell and a nonvolatile QuantumTrap cell. TheSRAM memory cell operates as a st...

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