Cypress CY14B102L - Manual

Cypress CY14B102L

Cypress CY14B102L – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.

1 Page 1
2 Page 2
3 Page 3
4 Page 4
5 Page 5
6 Page 6
7 Page 7
8 Page 8
9 Page 9
10 Page 10
11 Page 11
12 Page 12
13 Page 13
14 Page 14
15 Page 15
16 Page 16
17 Page 17
18 Page 18
19 Page 19
20 Page 20
21 Page 21
22 Page 22
23 Page 23
24 Page 24
Page: / 24

Table of Contents:

  • Page 2 – PRELIMINARY; Pinouts; Top View
  • Page 3 – Pin Definitions
  • Page 4 – Device Operation; “Truth Table For SRAM Operations”; SRAM Read; Figure 4; Figure 4. AutoStore Mode; Hardware STORE Operation
  • Page 5 – Software STORE
  • Page 6 – Preventing AutoStore; Noise Considerations
  • Page 7 – Maximum Ratings; DC Electrical Characteristics
  • Page 8 – AC Test Conditions; Thermal Resistance; OUTPUT
  • Page 9 – AC Switching Characteristics
  • Page 12 – AutoStore/Power Up RECALL
  • Page 13 – Software Controlled STORE/RECALL Cycle; Switching Waveforms
  • Page 14 – Hardware STORE Cycle; HSB To Output Active Time when write latch not set; Hardware STORE Pulse Width; Soft Sequence Processing Time
  • Page 15 – Truth Table For SRAM Operations; For x8 Configuration
  • Page 16 – Ordering Information
  • Page 19 – Part Numbering Nomenclature; Cypress
  • Page 20 – Package Diagrams
  • Page 23 – Document History Page; Submission
  • Page 24 – Worldwide Sales and Design Support
Loading the manual

PRELIMINARY

CY14B102L, CY14B102N

2 Mbit (256K x 8/128K x 16) nvSRAM

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

,

CA 95134-1709

•

408-943-2600

Document #: 001-45754 Rev. *B

Revised November 10, 2008

Features

■

20 ns, 25 ns, and 45 ns Access Times

■

Internally organized as 256K x 8 (CY14B102L) or 128K x 16

(CY14B102N)

■

Hands off Automatic STORE

on power down with only a small

Capacitor

■

STORE

to QuantumTrap

®

nonvolatile elements initiated by

software, device pin, or AutoStore

®

on power down

■

RECALL

to SRAM initiated by software or power up

■

Infinite Read, Write, and Recall Cycles

■

200,000 STORE

cycles to QuantumTrap

■

20 year data retention

■

Single 3V +20

%

to -10

%

operation

■

Commercial, Industrial and Automotive Temperatures

■

48-ball FBGA and 44/54-pin TSOP - II packages

■

Pb-free and RoHS compliance

Functional Description

The Cypress CY14B102L/CY14B102N is a fast static RAM, with

a nonvolatile element in each memory cell. The memory is

organized as 256K bytes of 8 bits each or 128K words of 16 bits

each. The embedded nonvolatile elements incorporate

QuantumTrap

technology, producing the world’s most reliable

nonvolatile memory. The SRAM provides infinite read and write

cycles, while independent nonvolatile data resides in the highly

reliable QuantumTrap cell. Data transfers from the SRAM to the

nonvolatile elements (the STORE operation) takes place

automatically at power down. On power up, data is restored to

the SRAM (the RECALL operation) from the nonvolatile memory.

Both the STORE and RECALL operations are also available

under software control.

67$7,&5$0

$55$<

;

5
2

:

'
(
&
2
'
(
5

&2/801,2

&2/801'(&

,

1
3
8

7
%

8

)
)
(

5
6

32:(5

&21752/

6725(5(&$//

&21752/

4XDWUXP7UDS

;

6725(

5(&$//

9

&&

9

&$3

+6%

$

$

$

$

$

$

$

$

62)7:$5(

'(7(&7

$

$

2(

&(

:(

%+(

%/(

$

$

$

$

$

$

$

$

$

$

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

Logic Block Diagram

[1, 2, 3]

Note

1. Address A

0

- A

17

for x8 configuration and Address A

0

- A

16

for x16 configuration.

2. Data DQ

0

- DQ

7

for x8 configuration and Data DQ

0

- DQ

15

for x16 configuration.

3. BHE and BLE are applicable for x16 configuration only.

[+] Feedback

"Loading the manual" means you need to wait until the file loads and becomes available for online reading. Some manuals are very large, and the time they take to appear depends on your internet speed.

Summary

Page 2 - PRELIMINARY; Pinouts; Top View

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 2 of 24 Pinouts Figure 1. Pin Diagram - 48 FBGA Figure 2. Pin Diagram - 44 Pin TSOP II 48-FBGA (not to scale) Top View (x8) 48-FBGA (not to scale) Top View (x16) WE V CC A 11 A 10 V CAP A 6 A 0 A 3 CE NC NC DQ0 A 4 A 5 NC DQ2 DQ3 NC...

Page 3 - Pin Definitions

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 3 of 24 Figure 3. Pin Diagram - 54 Pin TSOP II (x16) Pin Definitions Pin Name IO Type Description A 0 – A 17 Input Address Inputs Used to Select one of the 262,144 bytes of the nvSRAM for x8 Configuration . A 0 – A 16 Address Inputs...

Page 4 - Device Operation; “Truth Table For SRAM Operations”; SRAM Read; Figure 4; Figure 4. AutoStore Mode; Hardware STORE Operation

PRELIMINARY CY14B102L, CY14B102N Document #: 001-45754 Rev. *B Page 4 of 24 Device Operation The CY14B102L/CY14B102N nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a st...

Other Cypress Models

All Cypress Other