Cypress CY14B101LA - Manual
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Table of Contents:
- Page 2 – PRELIMINARY; Pinouts; Top View; Top View
- Page 4 – Device Operation; Truth Table For SRAM Operations; SRAM Read; Figure 4; Figure 4. AutoStore Mode; Hardware STORE Operation
- Page 5 – Software STORE; Table 2. Mode Selection
- Page 6 – Preventing AutoStore; Noise Considerations
- Page 7 – Maximum Ratings; DC Electrical Characteristics
- Page 8 – AC Test Conditions; Thermal Resistance; OUTPUT
- Page 9 – AC Switching Characteristics
- Page 12 – AutoStore/Power Up RECALL; RWI
- Page 13 – Software Controlled STORE/RECALL Cycle; Switching Waveforms
- Page 14 – Hardware STORE Cycle; HSB To Output Active Time when write latch not set; Hardware STORE Pulse Width; Soft Sequence Processing Time; Write latch set
- Page 16 – Ordering Information; Commercial
- Page 19 – Part Numbering Nomenclature; Cypress; Rev
- Page 20 – Package Diagrams
- Page 24 – Document History Page; Date
- Page 25 – Worldwide Sales and Design Support
PRELIMINARY
CY14B101LA, CY14B101NA
1 Mbit (128K x 8/64K x 16) nvSRAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 001-42879 Rev. *B
Revised January 29, 2009
Features
■
20 ns, 25 ns, and 45 ns Access Times
■
Internally organized as 128K x 8 (CY14B101LA) or 64K x 16
(CY14B101NA)
■
Hands off Automatic STORE
on power down with only a small
Capacitor
■
STORE
to QuantumTrap
®
nonvolatile elements initiated by
Software, device pin, or AutoStore
®
on power down
■
RECALL
to SRAM initiated by software or power up
■
Infinite Read, Write, and Recall Cycles
■
200,000 STORE
cycles to QuantumTrap
■
20 year data retention
■
Single 3V +20% to -10% operation
■
Commercial and Industrial Temperatures
■
48-ball FBGA, 44-pin TSOP - II, 48-pin SSOP, and 32-pin SOIC
packages
■
Pb-free and RoHS compliance
Functional Description
The Cypress CY14B101LA/CY14B101NA is a fast static RAM,
with a nonvolatile element in each memory cell. The memory is
organized as 128K bytes of 8 bits each or 64K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap
technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
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Logic Block Diagram
Note
1. Address A
0
- A
16
for x8 configuration and Address A
0
- A
15
for x16 configuration.
2. Data DQ
0
- DQ
7
for x8 configuration and Data DQ
0
- DQ
15
for x16 configuration.
3. BHE and BLE are applicable for x16 configuration only.
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Summary
PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev. *B Page 2 of 25 Pinouts Figure 1. Pin Diagram - 48 FBGA Figure 2. Pin Diagram - 44 Pin TSOP II WE V CC A 11 A 10 V CAP A 6 A 0 A 3 CE NC NC DQ 0 A 4 A 5 NC DQ 2 DQ 3 NC V SS A 9 A 8 OE V SS A 7 NC NC NC NC A 2 A 1 NC V CC DQ 4 NC DQ 5 DQ ...
PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev. *B Page 4 of 25 Device Operation The CY14B101LA/CY14B101NA nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as ...
PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev. *B Page 5 of 25 During any STORE operation, regardless of how it is initiated, the CY14B101LA/CY14B101NA continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the CY14B10...
