Cypress AN6077 - Manual
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Table of Contents:
- Page 2 – IFCONFIG; Creating GPIF Waveforms
- Page 3 – Figure 2; FIFOWR; Figure 3
- Page 4 – Firmware Architecture
- Page 5 – the PKTEND of the slave is tied; Psuedocode for Master OUT; if GPIF is IDLE; Psuedocode for Master IN; if the GPIF is IDLE; Expanded Master OUT Code
- Page 6 – Expanded Master IN Code
- Page 8 – Code Listing for Master Side
- Page 11 – // let transaction terminate naturally
- Page 17 – Code Listing for the Slave Side
February 19, 2008
Document No. 001-15342 Rev. **
1
with FX2LP
Implementing an 8-Bit Asynchronous Interface
Application Note Abstract
This application note discusses how to configure the General Programmable Interface (GPIF) and slave FIFOs of the EZ-USB
FX2LP™ to implement an 8-bit asynchronous interface. The GPIF is a programmable 8 or 16-bit parallel interface that reduces
system costs by providing a glueless interface between the EZ-USB FX2LP and different types of external peripherals. The
GPIF allows the EZ-USB FX2LP to perform local bus mastering to external peripherals implementing a wide variety of protocols.
For example, EIDE/ATAPI, printer parallel port (IEEE P1284), Utopia, and other interfaces are supported using the GPIF block
of the EZ-USB FX2LP. In this example, it masters the slave FIFO interface of another EZ-USB FX2LP.
This implementation uses the GPIF Designer (an utility Cypress provides to create GPIF waveform descriptors) to design the
application specific physical layer. The firmware is based on the Cypress EZ-USB FX2LP firmware ‘frameworks’. A hardware
setup of two back-to-back EZ-USB FX2LP boards is also used, one acting as a master and another as a slave. Familiarity with
the EZ-USB FX2LP development kit, examples and documentation on the development kit CD-ROM, and chapters 9 (EZ-USB
FX2LP Slave FIFOs) and 10 (GPIF) of the EZ-USB FX2LP Technical Reference Manual is assumed
.
Introduction
The objective of this application note is to:
■
Demonstrate a glueless interface to an 8-bit peripheral
data bus (the FIFO of a slave EZ-USB FX2LP).
■
Use EZ-USB FX2LP to transfer data to and from the pe-
ripheral (slave EZ-USB FX2LP) and the USB host.
This application note discusses the necessary hardware con-
nections, internal register settings, and 8051 firmware imple-
mented to execute data transactions over the interface and
across the USB bus.
Figure 1. Hardware Connection Diagram
AN6077
Author
: Sonia Gandhi
Associated Project
: No
Associated Part Family
: CY7C68013A
Software Version
: None
Associated Application Notes
: None
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Summary
February 19, 2008 Document No. 001-15342 Rev. ** 2 AN6077 GPIF Master Pin Descriptions The GPIF pin names, descriptions, and their uses are dis-cussed in this section. RDYn Inputs RDY[5:0] are ‘ready’ inputs that can be sampled and allow atransaction to wait (inserting wait states), continue, or rep...
February 19, 2008 Document No. 001-15342 Rev. ** 3 AN6077 Figure 2 shows the GPIF Designer view of the FIFO Read waveform. FIFOWR When creating the FIFOWR waveform the following timingparameters must be met. tWR pwl - SLWR Pulse Width LOW = 50 ns (minimum) tWR pwh - SLWR Pulse Width HIGH = 50 ns (mi...
February 19, 2008 Document No. 001-15342 Rev. ** 4 AN6077 Figure 4. FIFO Read Waveform in gpif.c Figure 5. FIFO Write Waveform in gpif.c 8051 Firmware Programming (Master) This section describes how to configure the 8051 to supportthe interface on the master side (register settings and others)and di...
