Cypress 001-07160 - Manual
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Table of Contents:
- Page 2 – rray; Array
- Page 3 – Pin Configuration
- Page 4 – Pin Definitions; Application Example
- Page 6 – Functional Overview; Write Operations
- Page 7 – Programmable Impedance; Echo Clocks; Switching; DLL; DLL Considerations in QDRIITM/DDRII; Figure 1; Figure 1. Application Example; ohms; BUS
- Page 8 – Write Cycle Descriptions
- Page 9 – BWS
- Page 10 – Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set
- Page 12 – TAP Controller State Diagram; The state diagram for the TAP controller follows.
- Page 14 – Figure 2
- Page 16 – Boundary Scan Order; Bump ID; Internal
- Page 17 – Power Up Sequence in DDR II SRAM; Power Up Sequence; Figure 3. Power Up Waveforms
- Page 18 – Neutron Soft Error Immunity; DC Electrical Characteristics
- Page 19 – AC Electrical Characteristics; Capacitance; ZQ
- Page 20 – Switching Characteristics
- Page 22 – Switching Waveforms; LD; CQD
- Page 23 – Ordering Information
- Page 24 – Package Diagram
- Page 25 – Document History Page; Date
- Page 26 – Worldwide Sales and Design Support; closest to you, visit us at; Products; PSoC
18-Mbit DDR II SRAM 2-Word
Burst Architecture
CY7C1318CV18
CY7C1320CV18
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-07160 Rev. *F
Revised August 24, 2009
Features
■
18-Mbit Density (1M x 18, 512K x 36)
■
267 MHz Clock for high Bandwidth
■
2-word Burst for reducing Address Bus Frequency
■
Double Data Rate (DDR) Interfaces
(data transferred at 534 MHz) at 267 MHz
■
Two Input Clocks (K and K) for precise DDR Timing
❐
SRAM uses rising edges only
■
Two Input Clocks for Output Data (C and C) to minimize Clock
Skew and Flight Time mismatches
■
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
■
Synchronous internally Self-timed Writes
■
DDR II operates with 1.5 Cycle Read Latency when the DLL is
enabled
■
Operates similar to a DDR I Device with one Cycle Read
Latency in DLL Off Mode
■
1.8V Core Power Supply with HSTL Inputs and Outputs
■
Variable drive HSTL Output Buffers
■
Expanded HSTL Output Voltage (1.4V–V
DD
)
■
Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free Packages
■
JTAG 1149.1 compatible Test Access Port
■
Delay Lock Loop (DLL) for accurate Data Placement
Configurations
CY7C1318CV18 – 1M x 18
CY7C1320CV18 – 512K x 36
Functional Description
The CY7C1318CV18, and CY7C1320CV18 are 1.8V
Synchronous Pipelined SRAMs equipped with DDR II archi-
tecture. The DDR II consists of an SRAM core with advanced
synchronous peripheral circuitry and a one-bit burst counter.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of C and C if provided, or on the rising edge of K and K if C/C are
not provided. For CY7C1318CV18 and CY7C1320CV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words (in the case of
CY7C1318CV18) of two 36-bit words (in the case of
CY7C1320CV18) sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need to capture data
separately from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
267 MHz
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
267
250
200
167
MHz
Maximum Operating Current
x18
805
730
600
510
mA
x36
855
775
635
540
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Summary
CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 2 of 26 Logic Block Diagram (CY7C1318CV18) Logic Block Diagram (CY7C1320CV18) WriteReg WriteReg CLK A (19:0) Gen. K K Control Logic Address Register Read Add . Decode Read Data Reg. R/W Output Logic Reg. Reg. Reg. 18 36 18 BWS [1:0] V ...
CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 3 of 26 Pin Configuration The pin configuration for CY7C1318CV18 and CY7C1320CV18 follow. [1] 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1318CV18 (1M x 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72M A R/W BWS 1 K NC/144M LD A NC/36M CQ B NC ...
CY7C1318CV18CY7C1320CV18 Document Number: 001-07160 Rev. *F Page 4 of 26 Pin Definitions Pin Name I/O Pin Description DQ [x:0] Input Output- Synchronous Data Input Output Signals . Inputs are sampled on the rising edge of K and K clocks during valid write operations. These pins drive out the request...
