MSI H6M-P3 (B3)- Manuals

MSI H6M-P3 (B3)– User Manual in PDF format online.

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User Manual

User Manual MSI H6M-P3 (B3)

Summary

Page 3 - Figure 2. Pin Connection

Figure 2. Pin Connection VDD_1 VSS_1 RESET SDA SCL SCKR SDI BIT_EN SDO VDD_4 VSS_4 XTI FILT XTO PVSS PVDD VDD_3 VSS_3 1 3 2 4 5 6 7 8 9 26 25 24 23 22 20 21 19 27 10 28 VDD_2 TESTEN D98AU911A VSS_2 SCKT LRCKT VSS_5 SRC_INT SCANEN 11 12 13 18 16 17 15 14 OCLK OUT_CLK/DATA_REQ 1 2 3 5 6 4 7 8 9 10 17 ...

Page 4 - PIN DESCRIPTION; Pin Name

PIN DESCRIPTION SO28 TQFP44 LFBGA64 Pin Name Type Function PAD Description 1 29 B5 VDD_1 Supply Voltage 2 30 B4 VSS_1 Ground 3 31 A4 SDA I/O i 2 C Serial Data + Acknowledge CMOS Input Pad BufferCMOS 4mA Output Drive 4 32 B3 SCL I I 2 C Serial Clock CMOS Input Pad Buffer 5 34 A1 SDI I Receiver Serial...

Page 5 - unless otherwise; GENERAL INTERFACE ELECTRICAL CHARACTERISTICS; POWER DISSIPATION

1. ELECTRICAL CHARACTERISTICS: V DD = 2.7V ± 0.3V; T amb = 0 to 70°C; Rg = 50 Ω unless otherwise specifiedDC OPERATING CONDITIONS Symbol Parameter Value V DD Power Supply Voltage 2.4 to 3.6V GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter Test Condition Min. Typ. Max. Unit Note I IL Lo...

Page 6 - Figure 3. Test Circuit; OUTPUT; Figure 4. Test Load Circuit; Output; SDA; Test Load; Symbol; Low Level Input Voltage

V DD 100nF 1 2 V DD 100nF 14 13 V SS V DD 100nF 16 15 V DD 100nF 23 22 V SS V SS V SS 17 18 27 28 26 RESET 24 TESTEN 25 SCANEN OUT_CLK/DATA_REQ V DD PV SS PV DD 100nF 4.7 µ F 4.7 µ F PV DD PV SS V SS 10K 1K 4.7nF PV SS 470pF 19 20 21 8 7 6 5 12 11 10 9 4 3 XTO XTI SCR_INT BIT_EN SCKR SDI OCLK LRCKT ...

Page 7 - Figure 6. Serial Input Interface Clocks; MPEG

SCLK_POL=0 SCLK_POL=4 DATA IGNORED DATA VALID SCKR SCKR SDI BIT_EN D98AU968A DATA IGNORED Figure 6. Serial Input Interface Clocks DATA SOURCE µ P MPEG DECODER IIC D98AU912 IIC SDO SCKT LRCKT SERIAL AUDIO INTERFACE SDI SCKR BIT_EN XTO DAC RX TX XTI FILT PLL OCLK SCL SDA DATA_REQ Figure 5. MPEG Decode...

Page 8 - PFD; Figure 7. PLL and Clocks Generation System

R C C XT I2DSPCLK XT I2OCLK X S N M PFD CP VCO SwitchingCircuit OCLK DCLK Update FRAC FRAC XTI Disable PLL Figure 7. PLL and Clocks Generation System 2.4 - PCM Output InterfaceThe decoded audio data are output in serial PCMformat. The interface consists of the following sig-nals:SDO PCM Serial Data ...

Page 9 - registers description.; C BUS SPECIFICATION; The STA013 supports the I

2.5 - STA013 Operation ModeThe STA013 can work in two different modes,called Multimedia Mode and Broadcast Mode.In Multimedia Mode, STA013 decodes the in-coming bitstream, acting as a master of the datacommunication from the source to itself.This control is done by a specific buffer manage-ment, con...

Page 11 - DESCRIPTION

3.4 - READ OPERATION (see Fig. 11) 3.4.1 - Current byte address readThe STA013 has an internal byte addresscounter. Each time a byte is written or read, thiscounter is incremented.For the current byte address read mode, follow-ing a START condition the master sends the de-vice address with the RW bi...

Page 13 - PLLCTL

4.1 - STA013 REGISTERS DESCRIPTIONThe STA013 device includes 128 I 2 C registers. In this document, only the user-oriented registersare described. The undocumented registers arereserved. These registers must never be ac-cessed (in Read or in Write mode). The Read-Only registers must never be written...

Page 18 - Figure 12. Volume Control and Output Setup

DLA register is used to attenuate the level ofaudio output at the Left Channel using the butter-fly shown in Fig. 12. When the register is set to 255 (0xFF), the maximum attenuation isachieved.A decimal unit correspond to an attenuation stepof 1 dB. DLAAddress: 0x46Type: R/WSoftware Reset: 0x00Hardw...

Page 21 - PCMCONF; Figure 13. LRCKT Polarity Selection

PCMCONF Address: 0x55Type: R/WSoftware Reset: 0x21Hardware Reset: 0x21 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description X ORD DIF INV FOR SCL PREC (1) PREC (1) X 1 PCM order the LS bit is transmitted First X 0 PCM order the MS bit is transmitted First X 0 The word is right padded X 1 The word is left pad...

Page 22 - PCMCROSS; The default configuration for this register is ’0x00’.; ANCILLARY DATA BUFFER

PCMCROSS Address: 0x56Type: R/WSoftware Reset: 0x00Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description X X X X X X 0 0 Left channel is mapped on the left output.Right channel is mapped on the Right output X X X X X X 0 1 Left channel is duplicated on both Output channels. X X X X X X 1 ...

Page 23 - SOFTVERSION

PLLFRAC_L ([7:0]) MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PLLFRAC_H ([15:8]) MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 PF15 PF14 PF13 PF12 PF11 PF10 PF9 PF8 Address: 0x64 - 0x65Type: R/WSoftware Reset: 0x46 | 0x5BHardware Reset: 0xNA | 0x5B The registers are considered logically concat...

Page 27 - GENERAL INFORMATION

TONE_ATTEN Address: 0x7DType: RWSoftware Reset: 0x00Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0 In the digital output audio, the full signal isachieved with 0 dB of attenuation. For this rea-son, before applying Bass & Treble Control, theuser has to set t...

Page 28 - IO

The Ancillary Data extraction on STA013 can bedescribed as follow:STA013 has a specific Ancillary Data buffer,mapped into the I2C registers: 0x59 ANC_DATA_1 0x5A ANC_DATA_2 0x5B ANC_DATA_3 0x5C ANC_DATA_4 0x5D ANC_DATA_5 Since the content of Ancillary Data into an MPEGFrame STA013 can extract is max...

Page 29 - Pad-timing versus load

5.4. TIMING DIAGRAMS5.4.1. Audio DAC Interfacea) OCLK in output. The audio PLL is used to clock the DAC OCLK (OUTPUT) SDO SCKT LRCLK t sdo t sckt t lrclk D98AU969 Pad-timing versus load Load (pF) Pad_timing 25 2.90ns 50 3.82ns 75 4.68ns 100 5.52ns Cload_XXX is the load in pF on the XXX output.pad_ti...

Page 31 - RESET

RESET D98AU974 t reset_low_min 5.4.5. RESETThe Reset min duration (t_reset_low_min) is 100ns HW RESET set PCM OUTPUT INTERFACE CONFIGURATION set set PCM-DIVIDER PCM-CONF. PLL FRAC_441_H,PLL FRAC_441_L,PLL FRAC_H,PLL FRAC_L } { set MFS DF_441,MFSDF } { PLL CONFIGURATION FOR: set PLL CTRL 48, 44.1, 32...

Page 34 - C REGISTER VALUE

5.6. STA013 CONFIGURATION FILE FORMATThe STA013 Configuration File is an ASCII format. An example of the file format is the following:58 142 4128 15............It is a sequence of rows and each one can be interpreted as an I 2 C command. The first part of the row is the I 2 C address (register) and ...

Page 35 - OUTLINE AND

SO28 DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 0.020 c1 45 ° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S 8 ° (max.) OUTLINE ...

Page 36 - mm

OUTLINE AND MECHANICAL DATA DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 1.60 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 B 0.30 0.37 0.45 0.012 0.015 0.018 C 0.09 0.20 0.004 0.008 D 11.80 12.00 12.20 0.464 0.472 0.480 D1 9.80 10.00 10.20 0.386 0.394 0.401 D3 8.00 0.315 E 11.8...

Page 38 - STMicroelectronics GROUP OF COMPANIES

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequencesof use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted by implication ...