MSI 5520 Master Series- Manuals

MSI 5520 Master Series– User Manual in PDF format online.

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User Manual

User Manual MSI 5520 Master Series

Summary

Page 3 - Contents

Contents Intel ® 7500 Chipset Specification Update 3 October 2011 Contents Revision History ........................................................................................................ 4 Preface ................................................................................................

Page 4 - Revision History

Revision History 4 Intel ® 7500 Chipset Specification Update October 2011 Intel Confidential Revision History Revision Number Description Date 001 • Initial release of the document March 2010 002 • Updated Erratum 3 and added spec change 1 and spec clarification 2 April 2010 003 • Added Erratum 58 M...

Page 5 - Preface; Affected Documents; Errata

Intel ® 7500 Chipset Specification Update 5 October 2011 Preface Preface This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device errata and documentation changes, specification clarifications and changes. It is intend...

Page 6 - Summary Table of Change; Codes Used in Summary Table; Stepping

Summary Table of Change 6 Intel ® 7500 Chipset Specification Update October 2011 Intel Confidential Summary Table of Change The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the Intel 7500 chipset product. Intel may...

Page 9 - Specification Changes; Specification Clarifications

Intel ® 7500 Chipset Specification Update 9 October 2011 Summary Table of Change 59 X X X No Fix PCIe Slot Status Register Command Completed bit not always updated on any configuration write to the Slot Control Register 60 X X X No Fix Level-triggered multicast device interrupts may cause an MCA tim...

Page 10 - Identification Information; Component Identification via Programming Interface; Top Side Marking Example

Identification Information 10 Intel ® 7500 Chipset Specification Update October 2011 Intel Confidential Identification Information Component Identification via Programming Interface The Intel 7500 chipset IOH stepping can be identified by the following register contents: Component Marking Informatio...

Page 11 - CPURST bit does not get cleared by hardware

Intel ® 7500 Chipset Specification Update 11 October 2011 Errata Errata 1. CPURST bit does not get cleared by hardware Problem: SYRE register (Device: 20, Function: 2; Offset 0CCh): CPURST bit does not get cleared by hardware. Implication: The Intel 7500 chipset IOH will not assert RESETO_N when CPU...

Page 12 - Extended Error Detect Mask Registers of all PCIe root ports mask

Errata 12 Intel ® 7500 Chipset Specification Update October 2011 Intel Confidential Dev 13:Func 0 1. Set Offset 1A0h [23:16] to 5, [7:0] to FFh 2. Set Offset 11Ch [28:25] to n, (n = 0) 3. For each n setting in step 2, set Offset 1B4h [11:8] to 8, [7:4] to 6, [3:0] to 5 Dev 13:Func 1 1. Set Offset 1A...

Page 14 - PCIe PMCSR Power State fields allow writing D1 and D2

Errata 14 Intel ® 7500 Chipset Specification Update October 2011 Intel Confidential 10. PCIe PMCSR Power State fields allow writing D1 and D2 Problem: The PMCSR (Devices: 0 to 10, Function: 0, Offset: E4h) bits 1:0 allow states D1 and D2 to be written. Implication: Given that the IOH does not suppor...

Page 15 - Intel

Intel ® 7500 Chipset Specification Update 15 October 2011 Errata • Dev 13: Funcs 6 - 1: Offset 4B4h bit[23] for root ports 6 - 1.• Dev 14: Funcs 3 - 0: Offset 4B4h bit[23] for root ports 10 - 7. Clear the default value of “1” to disable the corresponding root port from advertising upconfigure capabi...

Page 17 - during power-on resets

Intel ® 7500 Chipset Specification Update 17 October 2011 Errata Implication: For Intel VT-d Translated write transactions to the interrupt address range (0xFEExxxxx), the transaction is blocked, but evidence of the blocked transaction will not be available in the error registers. Workaround: None S...

Page 18 - Link training failure due to multiple resets

Errata 18 Intel ® 7500 Chipset Specification Update October 2011 Intel Confidential 27. Link training failure due to multiple resets Problem: When the Intel QuickPath Interconnect link is trained in slow mode and is followed by consecutive physical layer resets issued by the Tukwila processor, a lin...

Page 19 - Fatal

Intel ® 7500 Chipset Specification Update 19 October 2011 Errata 32. Failure during operation at PCI Express L1 power management state Problem: There may be intermittent failures observed when exiting from the L1 power management state back to the L0 power management state. Implication: Due to this ...

Page 21 - Error not logged due to a corrupt STP symbol

Intel ® 7500 Chipset Specification Update 21 October 2011 Errata if LNKCAP[11:10] = 11b // Support both L0s and L1 write Link Control Reg (PCIE Offset 0x10) LNKCON[1:0] = 10b // Disable L0s, Enable only L1 end Else LNKCON[1:0] = 11b else write Link Control Register (LNKCON, PCIE Offset 0x10) LNKCON[...

Page 22 - Intel QuickPath Interconnect Error Status D3 is observed

Errata 22 Intel ® 7500 Chipset Specification Update October 2011 Intel Confidential Workaround: Disable remote Non-posted Peer-to-Peer reads on the multi-IOH system on one IOH. Alternatively, disable Intel QuickData Technology on one IOH in a multi-IOH system. Status: For the steppings affected, see...

Page 25 - In-flight DMA requests received during the implicit DMA draining; a write to the Slot Control register must cause

Intel ® 7500 Chipset Specification Update 25 October 2011 Errata Implication: Live Error Recovery (LER) mode may not be used to bring the PCIe links back up after they have gone down due to errors being detected. Workaround: To recover the link after entering LER mode, a hard reset to the entire Int...

Page 26 - fail to train on some IOH devices

Errata 26 Intel ® 7500 Chipset Specification Update October 2011 Intel Confidential 60. Level-triggered multicast device interrupts may cause an MCA timeout Problem: When multiple processors are the target of an I/O initiated legacy interrupt (INTx), generated by the IOH IOAPIC, one of the target th...

Page 27 - Timeout Interval specification change to the; Datasheet; the next revision of the datasheet as follows:

Intel ® 7500 Chipset Specification Update 27 October 2011 Specification Changes Specification Changes 1. Intel QuickPath Interconnect Protocol Control Completion Retry Timeout Interval specification change to the Intel® 7500 Chipset Datasheet The following specification change to the QPIPCTRL Protoc...

Page 28 - to the

Specification Changes 28 Intel ® 7500 Chipset Specification Update October 2011 Intel Confidential 2. Intel QuickPath Interconnect Protocol APIC Source Address Decode Extended Logical Mode Interleave functionality specification change to the Intel® 7500 Chipset Datasheet The Extended Logical Mode In...

Page 29 - Memory Address Decode -; the next revision of the specification.; Memory Address Decode Fields

Intel ® 7500 Chipset Specification Update 29 October 2011 Specification Clarifications Specification Clarifications 1. Memory Address Decode - Intel® 7500 Chipset Datasheet The following clarification to the Memory Address Decoder Fields table will be made in the next revision of the specification. ...

Page 30 - the State Level description in the; of the document as shown below.; the extended tag field functionality, in the

Specification Clarifications 30 Intel ® 7500 Chipset Specification Update October 2011 Intel Confidential 3. Protocol Status - Intel® 7500 Chipset Datasheet The following clarification to the Intel QPI Protocol Status Register Fields (Register QPIPSTS, Device: 16, Function: 1, Offset: 54h) will be m...

Page 31 - Intel QuickPath Interconnect Interrupt Control (QPIPINTRC); item 6 in the; there are actually 17.

Intel ® 7500 Chipset Specification Update 31 October 2011 Specification Clarifications 6. Intel QuickPath Interconnect Interrupt Control (QPIPINTRC) clarification, in the Intel® 7500 Chipset Datasheet 7. Intel LNKSTS: PCI Express Link Status Register clarification, in the Intel® 7500 Chipset Datashe...

Page 32 - Chipset Datasheet; Table 8-6 MSI Address Format when Remapping is Enabled; Register; will be corrected in the next revision of the; MSI Address Format when Remapping is Enabled

Specification Clarifications 32 Intel ® 7500 Chipset Specification Update October 2011 Intel Confidential 9. Section 20.6.6.1 SR[0:3]: Scratch Pad Register 0-3 (Sticky) The register description in the table below incorrectly shows SR[4:7] where it should be described as SR[0:3]. This will be correct...

Page 33 - Thermal Sensor Control Register -; will be made in the next revision of the specification.

Intel ® 7500 Chipset Specification Update 33 October 2011 Documentation Changes Documentation Changes 1. Thermal Sensor Control Register - Intel® 7500 Chipset Datasheet The following additions to the TSCTRL Register (Device: 20, Function: 3, Offset: E8h) will be made in the next revision of the spec...