MSI 5520 Master Series- User Manual

MSI 5520 Master Series

MSI 5520 Master Series– User Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.

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Table of Contents:

  • Page 3 – Contents
  • Page 4 – Revision History
  • Page 5 – Preface; Affected Documents; Errata
  • Page 6 – Summary Table of Change; Codes Used in Summary Table; Stepping
  • Page 9 – Specification Changes; Specification Clarifications
  • Page 10 – Identification Information; Component Identification via Programming Interface; Top Side Marking Example
  • Page 11 – CPURST bit does not get cleared by hardware
  • Page 12 – Extended Error Detect Mask Registers of all PCIe root ports mask
  • Page 14 – PCIe PMCSR Power State fields allow writing D1 and D2
  • Page 15 – Intel
  • Page 17 – during power-on resets
  • Page 18 – Link training failure due to multiple resets
  • Page 19 – Fatal
  • Page 21 – Error not logged due to a corrupt STP symbol
  • Page 22 – Intel QuickPath Interconnect Error Status D3 is observed
  • Page 25 – In-flight DMA requests received during the implicit DMA draining; a write to the Slot Control register must cause
  • Page 26 – fail to train on some IOH devices
  • Page 27 – Timeout Interval specification change to the; Datasheet; the next revision of the datasheet as follows:
  • Page 28 – to the
  • Page 29 – Memory Address Decode -; the next revision of the specification.; Memory Address Decode Fields
  • Page 30 – the State Level description in the; of the document as shown below.; the extended tag field functionality, in the
  • Page 31 – Intel QuickPath Interconnect Interrupt Control (QPIPINTRC); item 6 in the; there are actually 17.
  • Page 32 – Chipset Datasheet; Table 8-6 MSI Address Format when Remapping is Enabled; Register; will be corrected in the next revision of the; MSI Address Format when Remapping is Enabled
  • Page 33 – Thermal Sensor Control Register -; will be made in the next revision of the specification.
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Notice:

The Intel

®

7500 Chipset may contain design defects or errors known as errata which may cause the

product to deviate from published specifications. Current characterized errata are available on request.

Reference Number:323168-009

Intel

®

7500 Chipset

Specification Update

October 2011

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Summary

Page 3 - Contents

Contents Intel ® 7500 Chipset Specification Update 3 October 2011 Contents Revision History ........................................................................................................ 4 Preface ................................................................................................

Page 4 - Revision History

Revision History 4 Intel ® 7500 Chipset Specification Update October 2011 Intel Confidential Revision History Revision Number Description Date 001 • Initial release of the document March 2010 002 • Updated Erratum 3 and added spec change 1 and spec clarification 2 April 2010 003 • Added Erratum 58 M...

Page 5 - Preface; Affected Documents; Errata

Intel ® 7500 Chipset Specification Update 5 October 2011 Preface Preface This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device errata and documentation changes, specification clarifications and changes. It is intend...

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