Intel PXA26X - Manuals

Intel® PXA26x Processor Family Developer’s Manual xxiii Contents Revision History Date Revision Description October 2002 Public Release -001 Released to the public March 2003 Release -002 Added fast wake-up and 33-MHz idle mode.

Intel® PXA26x Processor Family Developer’s Manual 1-1 Introduction 1 The Intel® PXA26x Processor Family is a 32-bit, multi-chip device which combines a processor based on Intel® XScale™ microarchitecture and Intel StrataFlash® memory. (Intel StrataFlash® memory is available on some versions.) The PX...

1-2 Intel® PXA26x Processor Family Developer’s Manual Introduction 1.2 System Integration Features The PXA26x processor family features are: • Integrated synchronous Intel StrataFlash® memory on some versions • Single-ended universal serial bus client interface • Network synchronous serial protocol ...

Intel® PXA26x Processor Family Developer’s Manual 1-3 Introduction The 3.6864-MHz crystal drives a core phase locked loop (PLL) and a peripheral PLL. The PLLs produce selected clock frequencies to run particular functional blocks. The 32.768-KHz crystal provides an optional clock source that must be...

1-4 Intel® PXA26x Processor Family Developer’s Manual Introduction 1.2.8 Multimedia Card (MMC) Controller The MMC controller provides a serial interface to standard memory cards. The controller supports up to two cards in either MMC or SPI modes with serial data transfers up to 20 Mbps. The MMC cont...

Intel® PXA26x Processor Family Developer’s Manual 1-5 Introduction The STUART’s transmit and receive pins are multiplexed with the fast infrared communication port. 1.2.14 Real-Time Clock (RTC) The RTC can be clocked from either the 3.6864-MHz crystal or from an optional 32-KHz crystal. A system wit...

1-6 Intel® PXA26x Processor Family Developer’s Manual Introduction 1.2.20 Network Synchronous Serial Protocol Port The PXA26x processor family has an SSP port optimized for connection to other network ASICs. This NSSP adds a Hi-Z function to TXD, the ability to control when Hi-Z occurs, and swapping...

Intel® PXA26x Processor Family Developer’s Manual 2-1 System Architecture 2 2.1 Overview The Intel® PXA26x Processor Family is an integrated system-on-a-chip microprocessor for high performance, low-power-portable handheld and handset devices. It incorporates the Intel® XScale™ microarchitecture wit...

2-2 Intel® PXA26x Processor Family Developer’s Manual System Architecture 2.2 Package Types The PXA26x processor family is available in a 13x13mm 294-pin TF-BGA package. It is available in multiple versions with different flash configurations: • PXA260 processor – No Intel StrataFlash® memory • PXA2...

Intel® PXA26x Processor Family Developer’s Manual 2-3 System Architecture 2.3 Intel® XScale™ Microarchitecture Implementation Options The processor incorporates the Intel® XScale™ microarchitecture. This core contains implementation options which an Application Specific Standard Product (ASSP) may e...

2-4 Intel® PXA26x Processor Family Developer’s Manual System Architecture 2.3.3 Coprocessor 14 Register 6 and 7– Clock and Power Management These registers allow software to use the clocking and power management modes. The valid operations are described in Table 3-25, “Coprocessor 14 Clock and Power...

Intel® PXA26x Processor Family Developer’s Manual 2-5 System Architecture 2.3.5 Coprocessor 15 Register 1 – P-Bit Bit 1 of this register is defined as the Page Table Memory Attribute bit or P-bit. It is not implemented in the processor and must be written as zero. Similarly, the P-bit in the page ta...

2-6 Intel® PXA26x Processor Family Developer’s Manual System Architecture Loads and stores to internal addresses are generally completed more quickly than those issued to external addresses. The difference in completion time allows one operation to be received before another operation, but completed...

Intel® PXA26x Processor Family Developer’s Manual 2-7 System Architecture Note: Clearing interrupts may take a delay. To allow the status bit to clear before returning from an interrupt service routine (ISR), clear the interrupt early in the routine. 2.7 Reset Table 2-4 shows each pin’s state after ...

2-8 Intel® PXA26x Processor Family Developer’s Manual System Architecture Byte and halfword accesses to internal registers are not permitted and yield unpredictable results. Register space, where a register is not specifically mapped, is defined as reserved space. Reading or writing reserved space c...

Intel® PXA26x Processor Family Developer’s Manual 2-9 System Architecture • Sleep mode – low power mode that does not save state but keeps I/Os powered. While the RTC, power manager, and clock module states are saved, coprocessor 14 is not. Note: In low power modes, ensure that input pins are not fl...

Intel® PXA26x Processor Family Developer’s Manual 2-21 System Architecture 2.13 Register Address Summary Table 2-8 lists the registers present in the PXA26x processor family. Table 2-7. Pin Description Notes Note Description [1] GPIO Reset Operation: Configured as GPIO inputs by default after any re...

Intel® PXA26x Processor Family Developer’s Manual 2-33 System Architecture 2.14 Memory Map Figure 2-3 on page 2-35 and Figure 2-2 on page 2-34 show the full processor memory map. Any unused register space from 0x4000 0000 to 0x4BFF FFFF is reserved. Note: Accessing reserved portions of the memory ma...

Intel® PXA26x Processor Family Developer’s Manual 3-1 Clocks and Power Manager 3 The clocks and power manager for the Intel® PXA26x Processor Family controls the clock frequency to each module and manages transitions between the different power manager operating modes to optimize both computing perf...

3-2 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager 3.2 Power Manager Introduction The clocks and power manager can place the processor in one of three resets. • Hardware reset (nRESET asserted) is a nonmaskable total reset. Use hardware reset at power up or when no system...

3-4 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager 3.3.1 32.768-KHz Oscillator The 32.768-KHz oscillator is a low-power, low-frequency oscillator that clocks the RTC and power manager. The 32.768-KHz oscillator is disabled out of hardware reset so the RTC and power manage...

3-6 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager 3.3.5 147.46-MHz Peripheral Phase Locked Loop The 147.46-MHz PLL is the clock source for many of the peripheral blocks’ external interfaces. These interfaces require: ~14.75 MHz for the UARTs, 12.288 MHz for the AC97, and...

Intel® PXA26x Processor Family Developer’s Manual 3-7 Clocks and Power Manager 3.4.1 Hardware Reset To invoke a hardware reset and reset all units in the processor to a known state, assert the nRESET pin. Hardware reset is only intended to be used for power up and complete resets. 3.4.1.1 Invoking H...

3-8 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager 3.4.2.2 Behavior During Watchdog Reset During watchdog reset, all units except the real time clock and parts of the clocks and power manager maintain their defined reset conditions. All pins except the oscillator pins ass...

Intel® PXA26x Processor Family Developer’s Manual 3-9 Clocks and Power Manager GPIO reset does not function in sleep mode because all GPIO pins’ alternate function inputs are disabled. External wake-up sources must be routed through one of the enabled GPIO wake-up sources (see Section 3.5.3, on page...

3-10 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager 3.4.5.1 Entering Turbo Mode The ratio between the run mode processor clock frequency and the turbo mode processor clock frequency is programmed in CCCR[N]. The value in CCCR[N], and any other appropriate clock configurat...

Intel® PXA26x Processor Family Developer’s Manual 3-11 Clocks and Power Manager During idle mode these resources are active: • System unit modules (real-time clock, operating system timer, interrupt controller, general-purpose I/O, and the clocks and power manager) • Peripheral unit modules (DMA con...

3-12 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager Software must then shut down the system and enter sleep mode. See Section 3.4.9.3, “Entering Sleep Mode” for more details. 3.4.7 33-MHz Idle Mode 33-MHz idle mode has the lowest power consumption of any idle mode. The ru...

Intel® PXA26x Processor Family Developer’s Manual 3-13 Clocks and Power Manager 3. Perform a frequency change sequence to 33MHz mode. The CCCR value for this mode is 0x13F 4. Enter idle mode by selecting the PWRMODE[M] bit (refer to Section 3.7.2 ) 3.4.7.2 Behavior in 33-MHz Idle Mode In 33-MHz idle...

3-14 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager 2. Disable the LCD controller or configure it to avoid the effects of an interruption in the LCD clocks and data from the processor. 3. Configure peripheral units to handle a lack of DMA service for up to 500 µ s. If a p...

Intel® PXA26x Processor Family Developer’s Manual 3-15 Clocks and Power Manager If hardware or watchdog reset is asserted during the frequency change sequence, the DRAM contents are lost because all states, including memory controller configuration and information about the previous frequency change...

3-16 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager • A power enable input pin that enables the primary supply output connected to VCC and PLL_VCC. This pin must be connected to the processor’s PWR_EN pin. To support fast sleep wake up by maintaining power during sleep, t...

Intel® PXA26x Processor Family Developer’s Manual 3-17 Clocks and Power Manager — PM GPIO Sleep State registers (PGSR0, PGSR,1 and PGSR2) — PM Wake-up Enable register (PWER) — PM GPIO Falling-edge Detect Enable and PM GPIO Rising-edge Detect Enable registers (PFER and PRER) — OPDE bit in the Power M...

3-18 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager in software by reading the Saved Program Status Register (SPSR) to see if the previous context was executing in abort mode. To enter sleep mode, software must complete this sequence: 1. Software uses external memory and ...

Intel® PXA26x Processor Family Developer’s Manual 3-19 Clocks and Power Manager Refer to Table 2-6, “Pin & Signal Descriptions for the PXA26x Processor Family” on page 2-9 for the PXA26x processor family pin states during sleep mode reset and other resets. 3.4.9.5 Exiting Sleep Mode Sleep mode e...

3-20 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager — The power manager wake-up source registers (PWER, PRER, and PFER) are loaded with 0x0000 0003, their wake-up default state. This limits the potential wake-up sources to a rising or falling edge on GPIO[0] or GPIO[1]. T...

Intel® PXA26x Processor Family Developer’s Manual 3-21 Clocks and Power Manager . Table 3-5. Power Mode Exit Sequence Table St e p Description of Action Tu rb o R un (fr om T u rb o ) Idle Fr eq C h a n ge S leep Fault 1 S leep 1 Wake up source or interrupt is received x x x 2 Power to I/O pins rest...

3-22 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager 3.5 Power Manager Registers This section describes the 32-bit registers that control the power manager. Table 3-6. Power and Clock Supply Sources and States During Power Modes Module Supply Source Power Mode Turbo Run Id...

3-24 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager 3.5.2 Power Manager General Configuration Register (PCFR) Use the PCFR, refer to Table 3-8 , to configure power manager functions in the processor. When the OPDE bit is set, it allows the 3.6864-MHz oscillator to be disa...

3-28 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager 3.5.6 Power Manager GPIO Edge Detect Status Register (PEDR) The PEDR, refer to Table 3-12 , indicates which of the GPIO pins enabled via the PWER, PRER, and PFER registers caused a sleep-mode wake up. The bits in PEDR ca...

Intel® PXA26x Processor Family Developer’s Manual 3-29 Clocks and Power Manager 3.5.7 Power Manager Sleep Status Register (PSSR) The PSSR, refer to Table 3-13 , contains these status flags: • Read Disable Hold (RD H) bit is set by hardware, watchdog, and GPIO resets and sleep mode. The RDH bit indic...

3-30 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager 3.5.8 Power Manager Scratch Pad Register (PSPR) The power manager contains a 32-bit register that can be used to save processor configuration information in any desired format. The PSPR, shown in Table 3-14 , is a holdin...

Intel® PXA26x Processor Family Developer’s Manual 3-31 Clocks and Power Manager 3.5.9 Power Manager Fast Sleep Wake Up Configuration Register (PMFWR) The power manager contains a 32-bit register that configures the processor sleep-wake-up sequence. The PMFWR, refer to Table 3-15 , contains a single ...

3-34 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager 3.5.12 Power Manager Register Locations Table 3-20 shows the registers associated with the power manager and the physical addresses used to access them. . Table 3-19. RCSR Bit Definitions 0x40F0_0030 RCSR Clocks and Powe...

Intel® PXA26x Processor Family Developer’s Manual 3-35 Clocks and Power Manager 3.6 Clocks Manager Registers The clocks manager contains three registers: • Core Clock Configuration Register (CCCR) • Clock Enable Register (CKEN) • Oscillator Configuration Register (OSCC) 3.6.1 Core Clock Configuratio...

3-36 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager Table 3-21. CCCR Register Bitmap and Bit Definitions 0x4130 0000 Core Clock Configuration Register (CCCR) Clocks Manager Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Re s e rv...

Intel® PXA26x Processor Family Developer’s Manual 3-39 Clocks and Power Manager 3.6.3 Oscillator Configuration Register (OSCC) The OSCC, refer to Table 3-23 , controls the 32.768-KHz oscillator configuration. It contains two bits, the set-only 32.768-KHz OON and the read-only 32.768-KHz OOK. The OON...

3-40 Intel® PXA26x Processor Family Developer’s Manual Clocks and Power Manager 3.7 Coprocessor 14: Clock and Power Management Coprocessor 14 contains two registers that control the power modes and sequences: • CP14 register 6 - CCLKCFG Register • CP14 register 7 - PWRMODE Register 3.7.1 Core Clock ...

Intel® PXA26x Processor Family Developer’s Manual 3-41 Clocks and Power Manager 3.7.2 Power Mode Register (PWRMODE) Use the PWRMODE register (CP14, register 7), refer to Table 3-27 , to enter idle and sleep modes. To select a mode, software writes to PWRMODE[M]. All core-initiated memory requests ar...

Intel® PXA26x Processor Family Developer’s Manual 4-1 System Integration Unit 4 This chapter describes the System Integration Unit (SIU) for the Intel® PXA26x Processor Family. The SIU controls several processor-wide system functions. The units contained in the SIU are: • General-purpose I/O ports •...

Intel® PXA26x Processor Family Developer’s Manual 4-3 System Integration Unit 4.1.2 GPIO Alternate Functions GPIO pins are capable of having as many as six alternate functions (shown Table 4-1 ) that can be set to enable additional functionality within the processor. If a GPIO is used for an alterna...

Intel® PXA26x Processor Family Developer’s Manual 4-7 System Integration Unit 4.1.3 GPIO Register Definitions There are a total of twenty-seven 32-bit registers within the GPIO control block. There are nine distinct register functions and there are three sets of each of the nine registers to serve t...

Intel® PXA26x Processor Family Developer’s Manual 4-21 System Integration Unit 4.1.3.7 Example Procedure for Configuring the Alternate Function Registers In this example, GP0 is used as a generic GPIO and GP(15:1) are configured as their alternate functions. Refer to Table 4-1 for the list of altern...

Intel® PXA26x Processor Family Developer’s Manual 4-23 System Integration Unit 4.2.1 Interrupt Controller Operation The Interrupt Controller provides masking capability for all interrupt sources and generates either an FIQ or IRQ processor interrupt. The interrupt hierarchy of the processor is a two...

4-24 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit 4.2.2 Interrupt Controller Register Definitions The interrupt controller contains the following registers: • Interrupt Controller IRQ Pending register (ICIP) • Interrupt Controller FIQ Pending register (ICFP) • Interrupt ...

Intel® PXA26x Processor Family Developer’s Manual 4-25 System Integration Unit Table 4-31 shows the bitmap of the Interrupt Controller Mask Register. Table 4-37 describes the available first-level interrupts and their location in the ICPR register. 4.2.2.2 Interrupt Controller Level Register (ICLR) ...

4-26 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit 4.2.2.3 Interrupt Controller Control Register (ICCR) The Interrupt Controller Control register (ICCR) contains a single control bit, Disable IDLE Mask (DIM). In normal IDLE mode any enabled interrupt can bring the process...

Intel® PXA26x Processor Family Developer’s Manual 4-27 System Integration Unit 4.2.2.5 Interrupt Controller Pending Register (ICPR) The ICPR is a 32-bit read-only register that shows all active interrupts in the system. These bits are not affected by the state of the mask register (ICMR). Clearing t...

Intel® PXA26x Processor Family Developer’s Manual 4-31 System Integration Unit Several units have more than one source per interrupt signal. When an interrupt is signalled from one of these units, the interrupt handler routine identifies which interrupt was signalled using the interrupt controller’s...

4-32 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit 4.3 Real-Time Clock (RTC) Use the RTC to configure a clock source with a wide range of frequencies. Typically, the RTC is set to be a 1 Hz output and is utilized as a system time keeper. There is also an alarm feature tha...

Intel® PXA26x Processor Family Developer’s Manual 4-35 System Integration Unit They are cleared by writing ones to the AL and HZ bits. The AL and HZ bits are routed to the interrupt controller where they may be enabled to cause a first level interrupt. Write zeros to all reserved bits and ignore all...

4-36 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit 4.3.3.1 Oscillator Frequency Calibration To determine the value programmed into the RTTR, you must first measure the output frequency at the oscillator multiplexor (approximately 32 KHz) using an accurate time base, such ...

Intel® PXA26x Processor Family Developer’s Manual 4-37 System Integration Unit 4.3.3.2.2 Trim Example #2 – Measured Value Has a Fractional Component This example is more common in that the measured frequency of the oscillator has a fractional component. Again, the desired Hz-clock-output frequency i...

4-38 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit The trim procedure can counteract these factors by providing a highly accurate mechanism to remove the variance and shifts from the manufacturing and static environment variables on an individual system level. However, si...

Intel® PXA26x Processor Family Developer’s Manual 4-39 System Integration Unit 4.4.2 Operating System Timer Register Definitions 4.4.2.1 Operating System Timer Match Register 0-3 (OSMR0, OSMR1, OSMR2, OSMR3) These registers are 32-bits wide and are readable and writable by the processor. They are co...

4-40 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit 4.4.2.3 Operating System Timer Watchdog Match Enable Register (OWER) The watchdog enable register contains a single control bit (bit 0) that enables the watchdog function. This bit is set by writing a one to it and can on...

Intel® PXA26x Processor Family Developer’s Manual 4-41 System Integration Unit 4.4.2.4 Operating System Timer Count Register (OSCR) The OS Timer Count register is a 32-bit counter that increments on rising edges of the 3.6864-MHz clock. This counter can be read or written at any time. It is recommen...

4-42 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit 4.4.3 Operating System Timer Register Locations Table 4-49 shows the registers associated with the OS timer and the physical addresses used to access them. Table 4-48. OSSR Bit Definitions Physical Address 0x40A0_0014 OS ...

Intel® PXA26x Processor Family Developer’s Manual 4-43 System Integration Unit 4.5 Pulse Width Modulator Use the Pulse Width Modulator (PWM) to generate as many as two signals to be output from the processor. The signals are based on the 3.6864-MHz clock and must be a minimum of 2 clock cycles wide....

4-44 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit 4.5.1.1 Interdependencies The PWM unit is clocked off the 3.6864-MHz oscillator output. Each Pulse Width Modulator Unit (PWMn) is controlled by three registers: • Pulse Width Control Register (PWM_CTRL) • Duty Cycle Contr...

Intel® PXA26x Processor Family Developer’s Manual 4-47 System Integration Unit Note: Due to internal timing requirements, all changes to any of the PWM registers must be complete a minimum of 4 core clock cycles before the start of end of a PWM clock cycle in order to guarantee that the following PW...

4-48 Intel® PXA26x Processor Family Developer’s Manual System Integration Unit The output waveform in Figure 4-4 is created by writing PWM_PERVALn[PV] with a decimal value of 10 (11 clocks) and PWM_DUTYn[DCYCLE] with 6. Figure 4-4 also shows that PWM_CTRLn[PRESCALE] is configured with a value of 0x0...

Intel® PXA26x Processor Family Developer’s Manual 5-1 Direct Memory Access Controller 5 This chapter describes the on-chip direct memory access (DMA) controller (DMAC) for the Intel® PXA26x Processor Family. The DMAC transfers data to and from main memory in response to requests generated by interna...

5-2 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller Figure 5-1. DMAC Block Diagram 5.1.1 Direct Memory Access Controller Channels The DMAC has 16 channels, each controlled by four 32-bit registers. Each channel can be configured to service any internal peripheral or...

Intel® PXA26x Processor Family Developer’s Manual 5-3 Direct Memory Access Controller Channel information must be maintained on a per-channel basis and is contained in the DMAC registers shown in Table 5-13, “DMA Controller Registers” on page 5-28 . The DMAC supports two methods of loading the DMAC ...

5-4 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller The PREQ[37:0] bits are the active high internal signals from the on-chip peripherals. Unlike DREQ[1:0], they are level sensitive. The DMAC does not sample the PREQ[37:0] signals until it completely finishes the cu...

5-6 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller 5.1.4 Direct Memory Access Descriptors The DMAC operates in two distinct modes: descriptor fetch mode and no-descriptor fetch mode. The mode used is determined by the DCSRx[NODESCFETCH] bit. The descriptor fetch an...

Intel® PXA26x Processor Family Developer’s Manual 5-7 Direct Memory Access Controller Figure 5-3. No-Descriptor Fetch Mode Channel State 5.1.4.2 Descriptor Fetch Mode In descriptor fetch mode, the DMAC registers are loaded from DMA descriptors in main memory. Multiple DMA descriptors can be chained ...

5-8 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller — Word [3] -> DCMDx register for the current transfer. 6. The channel waits for the request or starts the data transfer, as determined by the DCMD[FLOW] source and target bits. 7. The channel transmits a number ...

Intel® PXA26x Processor Family Developer’s Manual 5-9 Direct Memory Access Controller 5.1.4.3 Servicing an Interrupt If software receives an interrupt caused by a successful descriptor fetch, i.e. DCSRx[STARTINTR] = 0b1, then software must write a 1 to this bit to reset the corresponding interrupt. ...

5-10 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller 5.1.7 Byte Transfer Order The DCMD[ENDIAN] bit indicates the byte ordering in a word when data is read from or written to memory. Refer to Figure 5-5 on page 5-10 for details. The DCMD[ENDIAN} bit must be set to 0...

Intel® PXA26x Processor Family Developer’s Manual 5-11 Direct Memory Access Controller 5.1.8 Trailing Bytes The DMAC normally transfers bytes equal to the transaction size specified by DCMD[SIZE]. As the descriptor nears the end its data, the number of trailing bytes in the DCMD[LENGTH] field may be...

5-12 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller 5.2.1 Servicing Internal Peripherals The DMAC provides the DMA Request to Channel Map Registers (DRCMRx) that contain four bits used to assign a channel number for each possible DMA request. An internal peripheral...

Intel® PXA26x Processor Family Developer’s Manual 5-13 Direct Memory Access Controller 1. The DMAC transfers the required number of bytes from the I/O device addressed by DSADRx[31:0] to the DMAC write buffer. 2. The DMAC transfers the data to the memory controller via the internal bus. DCMD[WIDTH] ...

5-14 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller 5.2.3 Servicing Companion Chips and External Peripherals Companion chips and external peripherals can be serviced with flow-through transfers. The DMAC provides DMA Request to Channel Map Registers (DRCMRx) that c...

Intel® PXA26x Processor Family Developer’s Manual 5-17 Direct Memory Access Controller • DCMD[INCSRCADDR] = 1 • DCMD[INCTRGADDR] = 1 • DCMD[FLOWSRC] = 0 • DCMD[FLOWTRG] = 0 • DCSR[RUN] =1 5.3 Direct Memory Access Controller Registers The section describes the Direct Memory Access Controller register...

Intel® PXA26x Processor Family Developer’s Manual 5-19 Direct Memory Access Controller 5.3.3 DMA Request to Channel Map Registers The read/write DMA Request to Channel Map Registers (DRCMRx) ( Figure 5-8 ) map each DMA request to a channel. Refer to Table 5-13 for details. 3 STOPSTATE STOP STATE (re...

5-20 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller 5.3.4 DMA Descriptor Address Registers The DMA Descriptor Address Registers (DDADRx) (see Table 5-9, “DMA Descriptor Address Register Bit Definitions” on page 5-21 ) contain the memory address of the next descript...

Intel® PXA26x Processor Family Developer’s Manual 5-21 Direct Memory Access Controller 5.3.5 DMA Source Address Registers The DMA Source Address Registers (DSADRx) are read only in the descriptor fetch mode and are read/write in the no-descriptor fetch mode. The DSADRx (see Figure 5-10 ) contain the...

5-22 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller 5.3.6 DMA Target Address Registers To software, the DMA Target Address Registers (DTADRx) ( Figure 5-11 ) are read only in the Descriptor Fetch Mode and are read/write in the no-descriptor fetch mode. These regist...

Intel® PXA26x Processor Family Developer’s Manual 5-23 Direct Memory Access Controller 5.3.7 DMA Command Registers For software, the DMA Command Registers (DCMDx) ( Figure 5-12 ) are read only in descriptor fetch mode and are read/write in no-descriptor fetch mode. These registers contain the channe...

Intel® PXA26x Processor Family Developer’s Manual 5-25 Direct Memory Access Controller 5.4 Examples This section contains examples that show how to: • Set up and start a channel • Initialize a descriptor list for a channel that is running • Add a descriptor to the end of a descriptor list for a chan...

5-26 Intel® PXA26x Processor Family Developer’s Manual Direct Memory Access Controller Example 5-1. How to set up and start a channel: The following example shows how to set up a channel to transfer LENGTH words from the address DSADR to the I/O address DTADR. The example also shows how to start the...

Intel® PXA26x Processor Family Developer’s Manual 6-1 Memory Controller 6 This chapter describes the external memory interface structures and memory-related registers supported by the Intel® PXA26x Processor Family. The PXA26x processor family adds support for the extended mode register used in low-...

6-2 Intel® PXA26x Processor Family Developer’s Manual Memory Controller Figure 6-1. General Memory Interface Configuration 6.2 Functional Description The processor has three different memory spaces: SDRAM, static memory, and card memory. SDRAM has four partitions, static memory has six, and card spa...

Intel® PXA26x Processor Family Developer’s Manual 6-3 Memory Controller partition pairs: the 0/1 pair and the 2/3 pair. The partitions in a pair must be identical in size and configuration. The two pairs may be different (for example, the 0/1 pair can be 100-MHz SDRAM on a 32-bit data bus, while the...

6-4 Intel® PXA26x Processor Family Developer’s Manual Memory Controller The VLIO interface differs from SRAM in that it allows the data-ready input signal, RDY, to insert a variable number of wait states. For all static memory types, each chip select can be individually configured to a 16-bit or 32-...

6-6 Intel® PXA26x Processor Family Developer’s Manual Memory Controller Figure 6-3. Asynchronous Static Memory System Example 6.4 Memory Accesses If a memory access is followed by an idle bus period, the control signals return to their inactive state. The address and data signals remain at their pre...

Intel® PXA26x Processor Family Developer’s Manual 6-7 Memory Controller Table 6-1 lists all the transactions that the processor can generate. No burst can cross an aligned 32- byte boundary. On a 16-bit data bus, each full word access becomes a two half-word burst, with address bit 1 set to a 0. Eac...

6-8 Intel® PXA26x Processor Family Developer’s Manual Memory Controller If memory does not occupy all 64 MB of the partition, reads and writes from or to the unoccupied portion are processed as if the memory occupies the entire 64 MB of the memory partition. A single word (or half-word if the data b...

Intel® PXA26x Processor Family Developer’s Manual 6-9 Memory Controller 6.6 Synchronous DRAM Memory Interface Each possible SDRAM portion of the Memory Map is referred to as a partition, to distinguish them from banks internal to SDRAM devices. The signals used to control the SDRAM memory are listed...

6-12 Intel® PXA26x Processor Family Developer’s Manual Memory Controller 6.6.2 SDRAM Mode Register Set Configuration Register The MDMRS register issues an Mode Register Set (MRS) command to the SDRAM. The value written in this register is placed directly on address lines MA[24:17] during the MRS com...

Intel® PXA26x Processor Family Developer’s Manual 6-13 Memory Controller 6.6.2.1 Low-Power SDRAM Mode Register Set Configuration Register Use the Low-Power SDRAM Mode Register Set Configuration register (MDMRSLP) to issue a special low-power MRS command to SDRAM. Writing this register will trigger a...

6-14 Intel® PXA26x Processor Family Developer’s Manual Memory Controller 6.6.3 SDRAM MDREFR Register MDREFR is a read/write register and contains control bits that refresh both SDRAM partition pairs. MDREFR also contains control and status bits for SDRAM self-refresh, SDRAM/SMROM clock divisors, SDR...

Intel® PXA26x Processor Family Developer’s Manual 6-17 Memory Controller 6.6.4 SDRAM Memory Options The Dynamic Memory interface supports up to four partitions, organized as two pairs. Both partitions in a pair must have the same SDRAM size, configuration, timing category, and data bus width. Initia...

6-18 Intel® PXA26x Processor Family Developer’s Manual Memory Controller • SDRAM timing category • Data-bus width • Number of row, column, and bank address bits • Addressing scheme • Data-latching scheme Table 6-7, “Sample SDRAM Memory Size Options” on page 6-18 shows a sample of the supported SDRAM...

Intel® PXA26x Processor Family Developer’s Manual 6-19 Memory Controller Table 6-4 shows how the SDRAM row and column addresses are mapped to the internal SDRAM address. The SDRAM row and column addresses are muxed. The SDRAM row is sent during an Active command and is followed by the column address...

Intel® PXA26x Processor Family Developer’s Manual 6-25 Memory Controller 6.6.5 SDRAM Command Overview The processor accesses SDRAM with the following subset of standard interface commands: • Mode Register Set (MRS) • Bank Activate (ACT) • Read (READ) • Write (WRITE) • Precharge All Banks (PALL) • Pr...

6-26 Intel® PXA26x Processor Family Developer’s Manual Memory Controller • Power-Down (PWRDN) • Enter Self-Refresh (SLFRSH) • Exit Power-Down (PWRDNX) • No Operation (NOP) Table 6-12 shows the SDRAM interface commands. The table assumes the bank bits for the SDRAM are sent out on external address li...

Intel® PXA26x Processor Family Developer’s Manual 6-27 Memory Controller 6.6.6 SDRAM Waveforms Additional waveforms for the SDRAM controller are shown in Figure 6-5 , Figure 6-6 , Figure 6-7 , Figure 6-8 , Figure 6-9 , Figure 6-10 . Figure 6-5. SDRAM Read Figure 6-6. SDRAM Read With a Second Read to...

6-28 Intel® PXA26x Processor Family Developer’s Manual Memory Controller Figure 6-7. SDRAM Read With a Second Read to Same Bank, Different Row Figure 6-8. SDRAM Read With a Second Read to a Different Bank CL CL tRCD tRCD tRP tRAS tRP CL CL tRCD tRAS tRCD row col 0 1 2 3 0000 tRP = 2 clkstRAS = 7 clk...

Intel® PXA26x Processor Family Developer’s Manual 6-29 Memory Controller Figure 6-9. SDRAM Write Figure 6-10. SDRAM Write With a Second Write to Same Bank, Same Row CL tRCD CL tRCD row col 0 1 2 3 mask0 mask1 mask3 mask2 tRP = 2 clkstRCD = 2 clkstRAS = 2 clksCL = 2 clks 0ns 25ns 50ns 75ns SDCLK nSDC...

6-30 Intel® PXA26x Processor Family Developer’s Manual Memory Controller 6.7 Synchronous Static Memory Interface The synchronous static memory interface supports SMROM and non-SDRAM-like flash memories. The synchronous static memory can be configured for any of the nCS[3:0] signals. Chip Select 0 mu...

Intel® PXA26x Processor Family Developer’s Manual 6-35 Memory Controller 6.7.1.1 SMROM Memory Options Table 6-16 shows the possible external-to-internal address multiplexing options. For SMROM, there are no bank-address bits, but the corresponding bits are put on the external address bus. The number...

Intel® PXA26x Processor Family Developer’s Manual 6-37 Memory Controller 6.7.3 Synchronous Static Memory Timing Diagrams A three-beat read cycle for SMROM is shown in Figure 6-11 . Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R eser ved SXM RS 2 R eser ve...

6-38 Intel® PXA26x Processor Family Developer’s Manual Memory Controller Figure 6-11. SMROM Read Timing Diagram Half-Memory Clock Frequency, 6.7.4 Non-SDRAM Timing SXMEM Operation Non-SDRAM timing synchronous flash operation resets to asynchronous mode (page-mode for reads and asynchronous single wo...

Intel® PXA26x Processor Family Developer’s Manual 6-39 Memory Controller Table 6-19 shows sample frequency configurations for programming non-SDRAM timing fast flash. When in doubt, the higher frequency configuration and corresponding CAS latency must be used. Table 6-18. Read Configuration Register...

6-40 Intel® PXA26x Processor Family Developer’s Manual Memory Controller 6.7.4.1 Non-SDRAM Timing Flash Read Timing Diagram The burst-of-eight read timing diagram is shown in Figure 6-12 . In Figure 6-12 , the following timing parameters apply: • nADV asserted time = 1 MEMCLK • MA, nCS setup to nADV...

Intel® PXA26x Processor Family Developer’s Manual 6-41 Memory Controller • nADV assert time = 3 MEMCLKs • MA, nCS setup to nADV asserted = 1 MEMCLK • nADV deasserted to nOE asserted = (Code * 2) – 4 MEMCLKs 6.8 Asynchronous Static Memory 6.8.1 Static Memory Interface The Static Memory interface is m...

6-44 Intel® PXA26x Processor Family Developer’s Manual Memory Controller 6.8.2 Asynchronous Static Memory Control Registers (MSC0 – 2) The MSC0, MSC1, and MSC2 are read/write registers and contain control bits for configuring Static Memory (or Variable Latency I/O) that correspond to chip-select pai...

6-48 Intel® PXA26x Processor Family Developer’s Manual Memory Controller 6.8.3 ROM Interface The processor provides programmable timing for both burst and non-burst ROMs. The RDF field in MSCx is the latency (in memory clock cycles) for the first, and all subsequent, data beats from non-burst ROMs, ...

Intel® PXA26x Processor Family Developer’s Manual 6-51 Memory Controller 6.8.4 SRAM Interface Overview The processor provides a 16-bit or 32-bit asynchronous SRAM interface that uses the DQM pins for byte selects on writes. nCS[5:0] select the SRAM bank. nOE is asserted on reads and nWE is asserted ...

Intel® PXA26x Processor Family Developer’s Manual 6-53 Memory Controller • tAH = Address hold after nWE deasserted = 1 MEMCLK • nWE high time between burst beats = 2 MEMCLKs 6.8.5 Variable Latency I/O (VLIO) Interface Overview VLIO read accesses differ from SRAM read accesses in that the nOE toggles...

6-56 Intel® PXA26x Processor Family Developer’s Manual Memory Controller 6.8.6 FLASH Memory Interface The processor provides an SRAM-like interface for access of flash memory. The RDF fields in the MSCx registers are the latency for each read access to non-burst flash, or the first read access to bu...

6-58 Intel® PXA26x Processor Family Developer’s Manual Memory Controller 6.9.1 Expansion Memory Timing Configuration Register MCMEM0, MCMEM1, MCATT0, MCATT1, MCIO0, and MCIO1 are read/write registers that contain control bits for configuring the timing of the 16-bit PC Card/Compact Flash interface. ...

Intel® PXA26x Processor Family Developer’s Manual 6-59 Memory Controller : 13:12 — Reserved 11:7 MCATTx_ ASST Code for the command assertion time – See Table 6-30 for a description of this code and its affects on the command assertion. 6:0 MCATTx_ SET Minimum Number of memory clocks to set up addres...

Intel® PXA26x Processor Family Developer’s Manual 6-61 Memory Controller 6.9.2 Expansion Memory Configuration Register (MECR) To eliminate external hardware, two bits, shown in Table 6-31 , are used to signal the memory controller when a card (16-Bit PC Card/Compact Flash) is inserted in the socket ...

Intel® PXA26x Processor Family Developer’s Manual 6-63 Memory Controller Table 6-32. Common Memory Space Write Commands nPCE2 nPCE1 MA<0> nPOE nPWE MD[15:8] MD[7:0] 0 0 0 1 0 Odd Byte Even Byte 1 0 0 1 0 Unimportant Even Byte 1 0 1 1 0 Unimportant Odd Byte Table 6-33. Common Memory Space Read ...

6-64 Intel® PXA26x Processor Family Developer’s Manual Memory Controller 6.9.4 External Logic for 16-Bit PC Card Implementation The PXA26x processor family requires external glue logic to complete the 16-bit PC Card socket interface that allows either one- or two-socket solutions. Figure 6-25 and Fi...

Intel® PXA26x Processor Family Developer’s Manual 6-67 Memory Controller 6.9.5 Expansion Card Interface Timing Diagrams and Parameters Figure 6-27 shows a 16-bit access to a 16-bit memory or I/O device. When common memory is accessed, the MCMEM0 and MCMEM1 registers are used, depending on whether ca...

6-68 Intel® PXA26x Processor Family Developer’s Manual Memory Controller Figure 6-28. 16-Bit PC Card I/O 16-Bit Access to 8-Bit Device The interface waits the smallest possible amount of time (x_ASST_WAIT) before it checks the value of the nPWAIT signal. If the nPWAIT signal is asserted (active low)...

6-70 Intel® PXA26x Processor Family Developer’s Manual Memory Controller 6.10.1 Alternate Bus Master Mode The processor supports the presence of an alternate master on the SDRAM memory bus. The alternate master is given control of the bus with a hardware handshake that is performed through MBREQ and...

6-72 Intel® PXA26x Processor Family Developer’s Manual Memory Controller is deasserted or, as part of the sleep entry routine, the alternate master can be disabled. If necessary, the alternate master can hold the bus until its transaction is completed. After the memory controller has completed all o...

Intel® PXA26x Processor Family Developer’s Manual 6-73 Memory Controller 6.11.2.2 Boot-Time Configurations The boot time configurations are shown in Figure 6-31 – Figure 6-33 . A boot from a single 32- Mbit SMROM with nWORD = 1 is not supported. For the PXA260, BOOT_SEL[2:0] must be set appropriatel...

6-74 Intel® PXA26x Processor Family Developer’s Manual Memory Controller Figure 6-32. SMROM Boot Time Configurations and Register Defaults BOOT_SEL[2:0] = 100 SMROM 32-bit 32 MSC0 SXCNFG 7FF0 7FF0 0004 4531 SXEN0 = 1h, SXCL0 = 4h (CL = 5),SXRL0 = 1h (RL = 2), SXRA0 = 1h (13-bits),SXCA0 = 1h (8-bits)...

Intel® PXA26x Processor Family Developer’s Manual 6-75 Memory Controller Figure 6-33. SMROM Boot Time Configurations and Register Defaults (Continued) 6.11.3 Memory Interface Reset and Initialization On reset, the SDRAM Interface is disabled. Reset values for the Boot ROM are determined by BOOT_SEL....

6-76 Intel® PXA26x Processor Family Developer’s Manual Memory Controller In sleep mode, the memory pins and controller are in the same state as they are after a hardware reset, except that the GPIO signals are driven high. If SDRAMs are in self-refresh, they are held there by setting SDCKE<1> ...

6-78 Intel® PXA26x Processor Family Developer’s Manual Memory Controller 11. Optionally, in systems that contain SDRAM or synchronous static memory, enable auto- power-down by setting MDREFR:APD. 6.13 General Purpose Input/Output Reset Procedure On a GPIO Reset, the Memory Controller registers keep ...

Intel® PXA26x Processor Family Developer’s Manual 7-1 Liquid Crystal Display Controller 7 The liquid crystal display (LCD) controller provides an interface from the Intel® PXA26x Processor Family to a passive (DSTN) or active (TFT) flat panel display. Monochrome and several color pixel formats are s...

7-2 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller from the dither logic is grouped into the selected format (e.g., 8-bit color, dual panel, 16-bit color., etc.) and placed in a FIFO buffer before being sent out on the LCD controller ’s pins and driven to the dis...

7-4 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller 7.1.2 Pin Descriptions When the LCD controller is enabled, all of the LCD pins are outputs only. When the LCD controller is disabled, its pins are available for general-purpose input/output (GPIO). Refer to Secti...

Intel® PXA26x Processor Family Developer’s Manual 7-5 Liquid Crystal Display Controller • Program all of the LCD configuration registers except the Frame Descriptor Address registers (FDADRx) and the LCD Controller Configuration Register 0 (LCCR0). See Section 7.6 for details of all registers. • Pro...

7-6 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller • Section 7.3.3, “Temporal Modulated Energy Distribution (TMED) Dithering” • Section 7.3.4, “Output FIFOs” • Section 7.3.5, “Liquid Crystal Display Controller Pin Usage” • Section 7.3.6, “Direct Memory Access” 7....

Intel® PXA26x Processor Family Developer’s Manual 7-9 Liquid Crystal Display Controller 7.3.4 Output FIFOs The LCD controller has two output FIFOs to queue pixel data before it is sent to the pins. Each output FIFO is 16 bytes, organized as 16 entries by 8-bits wide. Pixel values are accumulated in ...

7-10 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller 7.3.5.2 Active-Display Timing In active display mode (LCCR0[PAS]=1), L_PCLK toggles continuously as long as the LCD controller is enabled. The other pins function as: L_BIAS – Output enable. When asserted, the L...

Intel® PXA26x Processor Family Developer’s Manual 7-11 Liquid Crystal Display Controller 7.4 Liquid Crystal Display External Palette and Frame Buffers The LCD controller supports a variety of user-programmable options, including display type and size, frame buffer location, encoded pixel size, and o...

7-12 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller 7.4.2 External-Frame Buffer The external frame buffer is an off-chip memory area used to supply enough encoded pixel values to fill the entire screen one or more times. The number of pixel data values depends on...

7-14 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller Note: For passive 16 bits per pixel operation, the Raw Pixel Data must be organized as shown above. ) Note: For active 16-bits per pixel operation, the raw pixel data is sent directly to the LCD panel pins and m...

Intel® PXA26x Processor Family Developer’s Manual 7-15 Liquid Crystal Display Controller If dummy pixels are to be inserted, the panel must ignore the extra pixel clocks at the end of each line that correspond to the dummy pixels. Use the following equation to calculate the total size of the frame b...

Intel® PXA26x Processor Family Developer’s Manual 7-17 Liquid Crystal Display Controller Figure 7-13. Passive Mode End-of-Frame Timing Figure 7-14. Passive Mode Pixel Clock and Data Pin Timing Line 239 Data Line 0 Data PPL = 319 BLW = 0 BLW = 0 ELW = 0 ELW = 0 VSW = 2 VSW = 2 HSW = 1 HSW = 1 ENB - L...

Intel® PXA26x Processor Family Developer’s Manual 7-19 Liquid Crystal Display Controller 7.6 Liquid Crystal Display Register Descriptions The LCD controller contains four control registers, ten DMA registers, one status register, and a 256-entry palette RAM. Table 7-16 lists their locations in physi...

7-20 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller An additional control field exists to tune the DMAC’s performance based on the type of memory system implemented with the processor. This field controls the placement of a minimum delay between each LCD-DMA-requ...

7-26 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller 7.6.1.12 Single-/Dual-Panel Select (SDS) In passive mode (PAS=0), the single-/dual-panel select (SDS) bit selects the type of display control implemented by the LCD screen. When SDS=0, single-panel operation is ...

7-28 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller blue pixel components. When CMS=1, monochrome mode is selected, palette entries are 8 bits wide, 4 or 8 data pins are enabled for single-panel mode, 8 data pins are enabled for dual-panel mode, and the blue dith...

7-30 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller elapsed. When L_LCLK is asserted, the value in HSW is transferred to a 6-bit down counter, which decrements at the programmed pixel clock frequency. When the counter reaches zero, L_LCLK is negated. HSW can be p...

Intel® PXA26x Processor Family Developer’s Manual 7-31 Liquid Crystal Display Controller 7.6.3.1 Beginning-of-Frame Line Clock Wait Count (BFW) In active mode (LCCR0[PAS]=1), the 8-bit beginning-of-frame line clock wait count (BFW) field specifies the number of line clocks to insert at the beginning...

Intel® PXA26x Processor Family Developer’s Manual 7-33 Liquid Crystal Display Controller 7.6.3.4 Lines Per Panel (LPP) The lines per panel (LPP) bit field specifies the number of lines or rows present on the LCD panel being controlled. In single-panel mode, it represents the total number of lines fo...

7-36 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller 7.6.4.7 AC Bias Pin Transitions Per Interrupt (API) The 4-bit API field specifies the number of AC bias pin (L_BIAS) transitions to count before setting the LCSR[ACS] status bit that signals an interrupt request...

Intel® PXA26x Processor Family Developer’s Manual 7-37 Liquid Crystal Display Controller • Number of panels (single or dual) • Display type (monochrome or color) • Number of pixel clock wait states programmed at the beginning and end of each line • Number of line clocks inserted at the beginning and...

7-38 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller 7.6.5.1 Frame Descriptors Although the FDADRx registers are loaded by software, the other DMA registers can only be loaded indirectly from DMA frame descriptors. A frame descriptor is a four-word block, aligned ...

Intel® PXA26x Processor Family Developer’s Manual 7-39 Liquid Crystal Display Controller memory location at the beginning of the palette data. The size of the palette data must be four 16-bit entries for 1- and 2-bit pixels, sixteen 16-bit entries for 4-bit pixels, or 256 16-bit entries for 8-bit pi...

Intel® PXA26x Processor Family Developer’s Manual 7-45 Liquid Crystal Display Controller 7.6.7.4 LCD Quick Disable Status (QD) QD is set when LCD enable (LCCR0[ENB]) is cleared and the DMA controller finishes any current data burst. When QD is set, an interrupt request is made to the interrupt contr...

7-46 Intel® PXA26x Processor Family Developer’s Manual Liquid Crystal Display Controller 7.6.7.10 Start Of Frame Status (SOF) SOF status is set after the DMA controller has loaded a new descriptor and that descriptor has the start of frame interrupt bit set (LDCMDx[SOFINT]=1). When SOF is set, an in...

Intel® PXA26x Processor Family Developer’s Manual 7-49 Liquid Crystal Display Controller 7.6.10.4 TMED Frame Number Adjuster Enable (FNAME) The frame number adjuster enable bit allows the frame number adjuster to add an offset to the current frame number before the value is sent through the algorith...

Intel® PXA26x Processor Family Developer’s Manual 8-1 Synchronous Serial Port Controller 8 This chapter describes the Synchronous Serial Port Controller’s (SSPC) signal definitions and operation for the Intel® PXA26x Processor Family. 8.1 Overview The SSPC is a full-duplex synchronous serial interfa...

8-2 Intel® PXA26x Processor Family Developer’s Manual Synchronous Serial Port Controller SSPEXTCLK is an external clock (input through GPIO27) that replaces the standard 3.6864-MHz clock used to generate the serial bit-rate clock (SSPSCLK). The external clock is also divided by the value in SSCR0[SC...

Intel® PXA26x Processor Family Developer’s Manual 8-3 Synchronous Serial Port Controller • SSPRXD – Receive signal for inbound data, from peripheral to system. A data frame can be configured to contain from 4 to 16 bits. Serial data is transmitted most significant bit first. The SSPC supports three ...

8-4 Intel® PXA26x Processor Family Developer’s Manual Synchronous Serial Port Controller . 8.4.1.2 SPI Format Details The SPI format has four sub-modes. The sub-mode used depends on the SSPSCLK edge selected for driving and sampling data and on the phase mode of SSPSCLK selected (see Section 8.7.2 f...

Intel® PXA26x Processor Family Developer’s Manual 8-5 Synchronous Serial Port Controller Figure 8-2 shows one of the four configurations for the Motorola SPI frame format for single and back-to-back frame transmissions. 8.4.1.3 Microwire Format Details Microwire format is similar to SPI, but it uses...

8-6 Intel® PXA26x Processor Family Developer’s Manual Synchronous Serial Port Controller Figure 8-3 shows the National Microwire frame format with 8-bit command words for single and back-to-back frame transmissions. 8.4.2 Parallel Data Formats for FIFO Storage Data in the FIFOs is stored with one 16...

Intel® PXA26x Processor Family Developer’s Manual 8-7 Synchronous Serial Port Controller 8.5.1 Using Programmed I/O Data Transfers Data words are 32 bits wide, but only 16-bit samples are transferred. Only the lower 2 bytes of a 32-bit word have valid data. The upper 2 bytes are not used and include...

8-14 Intel® PXA26x Processor Family Developer’s Manual Synchronous Serial Port Controller 8.7.2.6 Microwire Transmit Data Size (MWDS) Use the Microwire transmit data size (MWDS) bit to select the 8- or 16-bit size for command word transmissions in the National Microwire frame format. When MWDS=0, 8-...

Intel® PXA26x Processor Family Developer’s Manual 8-15 Synchronous Serial Port Controller 8.7.2.8 Receive FIFO Interrupt/DMA Threshold (RFT) This 4-bit value sets the level at or above which the FIFO controller triggers a DMA service interrupt and, if enabled, an interrupt request. Refer to Table 8-...

Intel® PXA26x Processor Family Developer’s Manual 8-19 Synchronous Serial Port Controller 8.7.4.7 Transmit FIFO Level The 4-bit Transmit FIFO Level bit indicates the number of entries currently in the transmit FIFO. 8.7.4.8 Receive FIFO Level The 4-bit receive FIFO Level bit indicates the one less t...

Intel® PXA26x Processor Family Developer’s Manual 9-1 Inter-Integrated Circuit Bus Interface Unit 9 This chapter describes the Inter-Integrated Circuit (I 2 C) bus interface unit, including the operation modes and setup for the Intel® PXA26x Processor Family. 9.1 Overview The I 2 C bus was created b...

9-2 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit For example, when the processor I 2 C unit acts as a master on the bus, it addresses an EEPROM as a slave to receive data (see Figure 9-1 ). When the I 2 C unit is addressing the EEPROM, it is a master-...

Intel® PXA26x Processor Family Developer’s Manual 9-3 Inter-Integrated Circuit Bus Interface Unit 9.3.1 Operational Blocks The I 2 C unit is connected to the peripheral bus. The processor interrupt mechanism can be used to notify the CPU that there is activity on the I 2 C bus. Polling can be used i...

9-4 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit While the I 2 C unit is idle, it defaults to slave-receive mode. This allows the interface to monitor the bus and receive any slave addresses intended for the processor. When the I 2 C unit receives an ...

Intel® PXA26x Processor Family Developer’s Manual 9-5 Inter-Integrated Circuit Bus Interface Unit Figure 9-2 shows the relationship between the SDA and SCL lines for START and STOP conditions. 9.3.3.1 START Condition The START condition (ICR[START]=1, ICR[STOP]=0) initiates a master transaction or r...

9-6 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit 9.3.3.2 No START or STOP Condition Use the no START or STOP condition (ICR[START]=0, ICR[STOP]=0) in master-transmit mode while the I 2 C unit is transmitting multiple data bytes (see Figure 9-2 ). Soft...

Intel® PXA26x Processor Family Developer’s Manual 9-7 Inter-Integrated Circuit Bus Interface Unit 8. Repeated START (Repeat Step 1) or STOP 9.4.1 Serial Clock Line (SCL) Generation When the I 2 C unit is in master-transmit or master-receive mode, it generates the I 2 C clock output. The SCL clock is...

9-8 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit The first byte transmission must be followed by an ACK pulse from the addressed slave. When the transaction is a write, the I 2 C unit remains in master-transmit mode and the addressed slave device stay...

Intel® PXA26x Processor Family Developer’s Manual 9-9 Inter-Integrated Circuit Bus Interface Unit In master-transmit mode, if the target slave-receiver device cannot generate the acknowledge pulse, the SDA line remains high. The lack of an acknowledge NAK causes the I 2 C unit to set the ISR[BED] bi...

9-10 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit 9.4.4.2 SDA Arbitration Arbitration on the SDA line can continue for a long time because it starts with the address and R/nW bits and continues through the data bits. Figure 9-7 shows the arbitration p...

Intel® PXA26x Processor Family Developer’s Manual 9-11 Inter-Integrated Circuit Bus Interface Unit If the I 2 C unit loses arbitration as the address bits are transferred and it is not addressed by the address bits, the I 2 C unit resends the address when the I 2 C bus becomes free. A resend is poss...

9-14 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit . \ Figure 9-8. Master-Receiver Read from Slave-Transmitter Figure 9-9. Master-Receiver Read from Slave-Transmitter / Repeated Start / Master- Transmitter Write to Slave-Receiver Figure 9-10. A Complet...

Intel® PXA26x Processor Family Developer’s Manual 9-15 Inter-Integrated Circuit Bus Interface Unit 9.4.6 Slave Operations Table 9-6 describes how the I 2 C unit operates as a slave device. Table 9-6. Slave Transactions I 2 C Slave Action Mode of Operation Definition Slave-receive (default mode) Slav...

9-16 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit Figure 9-11 through Figure 9-13 are examples of I 2 C transactions and show the relationships between master and slave devices. 9.4.7 General Call Address A general call address is a transaction with a...

Intel® PXA26x Processor Family Developer’s Manual 9-17 Inter-Integrated Circuit Bus Interface Unit master-transmitter. Figure 9-14 shows a general call address transaction. The least significant bit of the second byte, called B, defines the transaction. Table 9-7 shows the valid values and definitio...

9-18 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit 9.5 Slave Mode Programming Examples The following sub-sections describe slave mode programming. 9.5.1 Initialize Unit To initialize the unit: 1. Set the slave address in the ISAR. 2. Enable desired int...

Intel® PXA26x Processor Family Developer’s Manual 9-19 Inter-Integrated Circuit Bus Interface Unit 9.5.3 Read n Bytes as a Slave To read n bytes as a slave: 1. When a slave address detected interrupt occurs. Read ISR: slave address detected (1), unit busy (1), R/nW bit (0) 2. Write a 1 to the ISR[SA...

9-20 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit 5. Write a 1 to the ISR[ALD] bit if set. If the master loses arbitration, it performs an address retry when the bus becomes free. The arbitration loss detected interrupt is disabled to allow the addres...

Intel® PXA26x Processor Family Developer’s Manual 9-21 Inter-Integrated Circuit Bus Interface Unit 7. When an IDBR transmit empty interrupt occurs. Read ISR: IDBR transmit empty (1), unit busy (1), R/nW bit (0) 8. Write a 1 to the ISR[ITE] bit to clear interrupt. 9. Repeat steps 5-8 one time. 10. Lo...

9-22 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit 13. Read IDBR data. 14. Initiate STOP abort condition (STOP with no data transfer). Set ICR[MA] Note: If a NAK is not sent in step 11 , the next transaction must involve another data byte read. 9.7 Gli...

Intel® PXA26x Processor Family Developer’s Manual 9-23 Inter-Integrated Circuit Bus Interface Unit 9.9.2 I 2 C Data Buffer Register- IDBR The processor uses the I 2 C Data Buffer Register to transmit and receive data from the I 2 C bus. The IDBR is accessed by the program I/O on one side and by the ...

9-24 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit 9.9.3 I 2 C Control Register- ICR The processor uses the bits in the I 2 C Control Register (ICR) to control the I 2 C unit. 7:0 IDB I 2 C DATA BUFFER: Buffer for I 2 C bus send/receive data. Table 9-1...

9-26 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit 9.9.4 I 2 C Status Register The ISR signals I 2 C interrupts to the processor interrupt controller. Software can use the ISR bits to check the status of the I 2 C unit and bus. ISR bits (bits 9-5) are ...

9-28 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Bus Interface Unit 9.9.5 I 2 C Slave Address Register- ISAR The ISAR (see Table 9-13 ) defines the I 2 C unit’s 7-bit slave address. In slave-receive mode, the processor responds when the 7-bit address matches the value ...

Intel® PXA26x Processor Family Developer’s Manual 10-1 Universal Asynchronous Receiver/Transmitter 10 This chapter describes the three universal asynchronous receiver/transmitter (UART) serial ports without hardware flow control. Because the Hardware UART is configured differently than the other thr...

10-2 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/Transmitter 10.2 Overview Each serial port contains a UART and a slow infrared transmit encoder and receive decoder that conforms to the IrDA Serial Infrared (SIR) Physical Layer Link Specification. Each UART perf...

Intel® PXA26x Processor Family Developer’s Manual 10-3 Universal Asynchronous Receiver/Transmitter 10.3 Signal Descriptions Table 10-1 lists and describes each external signal that is connected to a UART module. The pins are connected through the system integration unit to GPIOs. Refer to Section 4....

10-4 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/Transmitter 10.4 UART Operational Description Figure 10-1 shows the format of a UART data frame. Figure 10-1. Example UART Data Frame Receive data sample counter frequency is 16 times the value of the bit frequenc...

Intel® PXA26x Processor Family Developer’s Manual 10-5 Universal Asynchronous Receiver/Transmitter Each UART has two FIFOs: one transmit and one receive. The transmit FIFO is 64 bytes deep and eight bits wide. The receive FIFO is 64 bytes deep and 11-bits wide. Three bits are used for tracking error...

10-6 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/Transmitter . 10.4.2.1 Receive Buffer Register (RBR) In non-FIFO mode, the Receive Buffer Register (RBR) holds the character received by the UART’s Receive Shift Register. If the RBR is configured to use fewer tha...

Intel® PXA26x Processor Family Developer’s Manual 10-7 Universal Asynchronous Receiver/Transmitter 10.4.2.2 Transmit Holding Register (THR) In non-FIFO mode, the THR holds the data byte that is to be transmitted next. When the TSR is emptied, the contents of the THR are loaded in the TSR and the LSR...

10-8 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/Transmitter 10.4.2.4 Interrupt Enable Register (IER) The IER enables the five types of interrupts that set a value in the Interrupt Identification Register (IIR). To disable an interrupt, software must clear the a...

Intel® PXA26x Processor Family Developer’s Manual 10-11 Universal Asynchronous Receiver/Transmitter Table 10-8. Interrupt Conditions Priority Level Interrupt origin 1 (highest) Receiver Line Status – One or more error bits were set 2 Received Data is available – In FIFO mode, trigger level was reach...

10-12 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/Transmitter 10.4.2.6 FIFO Control Register (FCR) The FCR is a write-only register that is located at the same address as the IIR, which is a read-only register. The FCR enables/disables the transmitter/receiver F...

Intel® PXA26x Processor Family Developer’s Manual 10-13 Universal Asynchronous Receiver/Transmitter Table 10-11. FIFO Control Register – FCR Base+0x08 FIFO Control Register UART Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R eser ve d ITL R eser ve d R es...

10-20 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/Transmitter Note: When bit 0, 1, 2, or 3 is set, a modem status interrupt is generated if IER[MIE] is set. Table 10-15. Modem Status Register – MSR Base+0x18 Modem Status Register UART Bit 31 30 29 28 27 26 25 24...

Intel® PXA26x Processor Family Developer’s Manual 10-21 Universal Asynchronous Receiver/Transmitter 10.4.2.11 Scratchpad Register (SPR) The read/write SPR has no effect on the UART. It is intended as a scratchpad register for use by the programmer. It is included for 16550 compatibility. 10.4.3 FIFO...

10-22 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/Transmitter After the processor reads one character from the receive FIFO or a new start bit is received, the character timeout indication interrupt is cleared and the timeout is reset. If a character timeout ind...

Intel® PXA26x Processor Family Developer’s Manual 10-23 Universal Asynchronous Receiver/Transmitter Note: Ensure that the DMAC has finished previous receive DMA requests before the error interrupt handler begins to clear the errors from the FIFO. 10.4.5.1 Trailing Bytes in the Receive FIFO Trailing ...

10-24 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/Transmitter 10.4.6.2 Operation The SIR modulation technique works with 5-, 6-, 7-, or 8-bit characters with an optional parity bit. The data is preceded by a zero value start bit and ends with one or more stop bi...

Intel® PXA26x Processor Family Developer’s Manual 10-25 Universal Asynchronous Receiver/Transmitter The top line in Figure 10-3 shows an asynchronous transmission as it is sent from the UART. The second line shows the pulses generated by the IR encoder at the TXD pin. A pulse is generated in the mid...

10-26 Intel® PXA26x Processor Family Developer’s Manual Universal Asynchronous Receiver/Transmitter Note: The SIR TXD output pin is automatically held deasserted when the RCVEIR bit is set. Before setting the RCVEIR bit, check that the TEMT bit is 1. While receiving, any data placed in the transmit ...

Intel® PXA26x Processor Family Developer’s Manual 10-27 Universal Asynchronous Receiver/Transmitter 10.5.1 UART Register Differences The default descriptions for BTMCR, BTMSR and STMCR are modified as shown in Table 10-21 . . 0x4020 0010 X BTMCR “Modem Control Register (MCR)” (read/write) 0x4020 001...

Intel® PXA26x Processor Family Developer’s Manual 11-1 Fast Infrared Communication Port 11 The Fast Infrared Communications Port (FICP) for the Intel® PXA26x Processor Family operates at half-duplex and provides direct connection to commercially available Infrared Data Association (IrDA) compliant L...

11-2 Intel® PXA26x Processor Family Developer’s Manual Fast Infrared Communication Port 11.2.1 Four-Position Pulse Modulation Four-position pulse modulation (4PPM) is used to transmit data at the high-speed rate, 4.0 Mbps. Data bits are encoded two at a time by placing a single 125 ns light pulse in...

Intel® PXA26x Processor Family Developer’s Manual 11-3 Fast Infrared Communication Port 11.2.2 Frame Format The frame format used with 4-Mbps transmission is shown in Figure 11-3 . Figure 11-3. Frame Format for IrDA Transmission (4.0 Mbps) The preamble, start, and stop flags are a mixture of chips t...

11-4 Intel® PXA26x Processor Family Developer’s Manual Fast Infrared Communication Port 11.2.3 Address Field A transmitter uses the 8-bit address field to target a receiver when multiple stations are connected to the same set of serial lines. The address allows up to 255 stations to be uniquely addr...

Intel® PXA26x Processor Family Developer’s Manual 11-5 Fast Infrared Communication Port 11.2.7 Baud Rate Generation The baud rate is derived by dividing a fixed 48-MHz clock by six. Using a digital PLL, the 8-MHz baud (or timeslot) clock for the receive logic is synchronized with the 4PPM data strea...

11-6 Intel® PXA26x Processor Family Developer’s Manual Fast Infrared Communication Port If the data field contains any invalid chips (such as 0011, 1010, 1110) the frame aborts and the oldest byte in the temporary FIFO is moved to the receive FIFO, the remaining temporary FIFO entries are discarded,...

Intel® PXA26x Processor Family Developer’s Manual 11-7 Fast Infrared Communication Port At the end of each transmitted frame, the FICP sends a pulse called the serial infrared interaction pulse (SIP). A SIP must be sent at least every 500 ms to ensure that low-speed devices (115.2 Kbps and slower) d...

11-8 Intel® PXA26x Processor Family Developer’s Manual Fast Infrared Communication Port The core must also read bytes from the FIFO until ICSR0[EIF] is cleared if there are errors in FIFO entries below the DMA trigger level. When the entries below the DMA trigger level no longer contain status flags...

11-10 Intel® PXA26x Processor Family Developer’s Manual Fast Infrared Communication Port 11.3.2 FICP Control Register 1 FICP control register 1 (ICCR1) contains the 8-bit address match value field that the FICP uses to selectively receive frames. To allow the address match value to be changed during...

Intel® PXA26x Processor Family Developer’s Manual 11-11 Fast Infrared Communication Port 11.3.3 FICP Control Register 2 The FICP control register 2 (ICCR2) contains two bit fields that control the polarity of the transmit and receive data pins and two bits that determine the trigger level for the re...

11-12 Intel® PXA26x Processor Family Developer’s Manual Fast Infrared Communication Port 11.3.4 FICP Data Register The FICP data register (ICDR) is a 32-bit register and its lower 8 bits are the top entry of the transmit FIFO when the register is written and the bottom entry of the receive FIFO when...

Intel® PXA26x Processor Family Developer’s Manual 11-13 Fast Infrared Communication Port each entry is removed, the EIF bit must be checked to determine if any set end or error tag remains and the procedure is repeated until all set tags are flushed from the FIFO’s bottom entries. When EIF is cleare...

11-14 Intel® PXA26x Processor Family Developer’s Manual Fast Infrared Communication Port . 11.3.6 FICP Status Register 1 FICP status register 1 (ICSR1) contains flags that indicate that the receiver is synchronized, the transmitter is active, the transmit FIFO is not full, the receive FIFO is not em...

Intel® PXA26x Processor Family Developer’s Manual 11-15 Fast Infrared Communication Port . Table 11-7. Fast Infrared Communication Port Status Register 1 0x4080 0018 Fast Infrared Communication Port Status Register 1 (ICSR1) FICP Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ...

Intel® PXA26x Processor Family Developer’s Manual 12-1 Universal Serial Bus Device Controller 12 This section describes the Universal Serial Bus (USB) protocol and its implementation-specific options for device controllers for the Intel® PXA26x Processor Family. These options include endpoint number...

12-2 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller service request is generated when a packet has been received. The DMA engine services the UDC FIFOs in 32-byte increments. Interrupts are also generated when the FIFO encounters a short packet or zero-lengt...

Intel® PXA26x Processor Family Developer’s Manual 12-3 Universal Serial Bus Device Controller Data flow is relative to the USB host. IN packets represent data flow from the UDC to the host. OUT packets represent data flow from the host to the UDC. The FIFOs for the bulk and isochronous endpoints are...

12-4 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller host detects a disconnect when an SE0 persists for more than 2.5 µs (30 bit times). When the UDC is connected to the USB cable, the pull-up resistor on the UDC+ pin causes D+ to be pulled above the single-e...

Intel® PXA26x Processor Family Developer’s Manual 12-5 Universal Serial Bus Device Controller The PID is 1 byte wide and always follows the sync field. The first four bits contain an encoded value that represents packet type (token, data, handshake, and special), packet format, and type of error det...

12-6 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller 12.3.4.2 Start of Frame Packet Type An SOF is a special type of token packet that the host issues at a nominal interval of once every 1 ms +/- 0.0005 ms. SOF packets consist of a sync, a PID, a frame number...

Intel® PXA26x Processor Family Developer’s Manual 12-7 Universal Serial Bus Device Controller 12.3.5 Transaction Formats Packets are assembled into groups to form transactions. The USB protocol uses four different transaction formats. Each transaction format is specific to a particular type of endpo...

12-8 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller 12.3.5.3 Control Transaction Type The host uses control transactions to configure endpoints and query their status. Like bulk transactions, control transactions begin with a setup packet, followed by an opt...

12-10 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller 12.3.7 Configuration In response to the GET_DESCRIPTOR command, the user device sends back a description of the UDC configuration. The UDC can physically support more data channel bandwidth than the USB sp...

Intel® PXA26x Processor Family Developer’s Manual 12-11 Universal Serial Bus Device Controller 12.4.1.1 When GPIOn and GPIOx are Different Pins The GPIOn and GPIOx pins can be any GPIO pins. GPIOn must be a GPIO that can wake the device from sleep mode. After a reset, GPIOx is configured as an input...

12-12 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller 12.4.2 Bus-Powered Devices The processor does not support bus-powered devices because it is required to consume less that 500 µA when the host issues a suspend (see Section 7.2.3 of the USB Specification, ...

Intel® PXA26x Processor Family Developer’s Manual 12-13 Universal Serial Bus Device Controller 14. When the host executes the STATUS OUT stage (zero-length OUT), the UDC sets the UDDCS0[OPR] bit, which causes an interrupt. 15. Software enters the ISR routine and determines that the UDCCS0[OPR] bit i...

Intel® PXA26x Processor Family Developer’s Manual 12-15 Universal Serial Bus Device Controller the wrong amount of data was sent, software cleans up any buffer pointers and disregards the received data. 20. Software changes its internal state machine to EP0_IDLE. 21. Software clears the UDC interrup...

12-16 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller 1. During the SETUP VENDOR command, software enables the DMA engine and masks the EP1 interrupt. The DMA start address must be aligned on a 16-byte boundary. a. If the packet size is 64 bytes, software tra...

Intel® PXA26x Processor Family Developer’s Manual 12-17 Universal Serial Bus Device Controller 2. The host PC sends a BULK-OUT. 3. The DMA engine reads data from the EP2 data FIFO (UDDR2). 4. Steps 2 and 3 repeat until all the data has been read from the host. 5. If the software receives an EP2 inte...

12-18 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller 1. During the SETUP VENDOR command, software enables the DMA engine and masks the EP3 interrupt. The DMA start address must be aligned on a 16-byte boundary. a. If the packet size is 256 bytes, software tr...

Intel® PXA26x Processor Family Developer’s Manual 12-19 Universal Serial Bus Device Controller When software receives a SETUP VENDOR command to set up an EP4 ISOCHRONOUS OUT transaction, it may take one of three courses of action, as appropriate for the chosen operating model: • Configure the DMA en...

12-20 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller 6. Return from interrupt. 7. Steps 2 through 6 repeat until all the data has been read from the host. 12.5.8.3 Software Enables the SOF Interrupt If software enables the SOF interrupt to handle the transac...

Intel® PXA26x Processor Family Developer’s Manual 12-21 Universal Serial Bus Device Controller b. If UDCCR[UDA] is a 1, there is currently no USB reset on the bus and software enables future reset interrupts by clearing the UDCCR[REM] bit. 3. Return from interrupt. 4. The host either asserts a USB r...

12-22 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller address for the 16 x 8 data FIFO that can be used to transmit and receive data. Endpoint 0 also has a write count register that is used to determine the number of bytes the USB host controller has sent to ...

12-26 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller 12.6.3 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 1, 6, or 11 The UDC Endpoint(x) Control Status Register contains 6 bits operate endpoint(x), a bulk IN endpoint). 12.6.3.1 Transmit FIFO S...

Intel® PXA26x Processor Family Developer’s Manual 12-27 Universal Serial Bus Device Controller 12.6.3.2 Transmit Packet Complete (TPC) The transmit packet complete bit is set by the UDC when an entire packet is sent to the host. When this bit is set, the IRx bit in the appropriate UDC status/interru...

Intel® PXA26x Processor Family Developer’s Manual 12-29 Universal Serial Bus Device Controller 12.6.4.1 Receive FIFO Service (RFS) The receive FIFO service bit is set if the receive FIFO has one complete data packet in it and the packet has been error checked by the UDC. A complete packet may be 64 ...

12-32 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller 12.6.5.3 Flush Tx FIFO (FTF) The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO. The Flush Tx FIFO bit is set when software writes a 1 to it or when the host performs a SET_CONFIGURATI...

12-38 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller 12.6.8.1 Interrupt Mask Endpoint x (IMx), Where x is 0 through 7 The UICR0[IMx] bit is used to mask or enable the corresponding endpoint interrupt request, USIR0[IRx]. When the mask bit is set, the interru...

Intel® PXA26x Processor Family Developer’s Manual 12-39 Universal Serial Bus Device Controller 12.6.9.1 Interrupt Mask Endpoint x (IMx), where x is 8 through 15. The UICR1[IMx] bit is used to mask or enable the corresponding endpoint interrupt request, USIR1[IRx]. When the mask bit is set, the inter...

Intel® PXA26x Processor Family Developer’s Manual 12-43 Universal Serial Bus Device Controller 12.6.12 UDC Frame Number High Register (UFNHR) The UDC frame number high register holds the three most significant bits of the frame number contained in the last received SOF packet, the isochronous OUT en...

12-44 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller 12.6.12.3 Isochronous Packet Error Endpoint 9 (IPE9) The isochronous packet error for Endpoint 9 is set if Endpoint 9 is loaded with a data packet that is corrupted. This status bit is used in the interrup...

Intel® PXA26x Processor Family Developer’s Manual 12-45 Universal Serial Bus Device Controller 12.6.13 UDC Frame Number Low Register (UFNLR) The UDC frame number low register is the eight least significant bits of the 11-bit frame number contained in the last received SOF packet. The three remaining...

Intel® PXA26x Processor Family Developer’s Manual 12-47 Universal Serial Bus Device Controller 12.6.16 UDC Data Register x (UDDRx), Where x is 1, 6, or 11 Endpoint(x) is a double-buffered bulk IN endpoint that is 64 bytes deep. Data can be loaded via DMA or direct core writes. Because it is double b...

12-50 Intel® PXA26x Processor Family Developer’s Manual Universal Serial Bus Device Controller 12.6.21 UDC Register Locations Table 12-32 shows the registers associated with the UDC and the physical addresses used to access them. Table 12-32. UDC Control, Data, and Status Register Locations (Sheet 1...

Intel® PXA26x Processor Family Developer’s Manual 13-1 AC97 Controller Unit 13 13.1 Overview The AC97 Controller Unit (ACUNIT) of the Intel® PXA26x Processor Family supports the AC97 revision 2.0 features listed in Section 13.2, “Feature List” . The ACUNIT also supports audio controller link (AC-lin...

13-2 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit 13.3 Signal Description The AC97 signals form the AC-link, which is a point-to-point synchronous serial interconnect that supports full-duplex data transfers. All digital audio streams, modem line codec streams, and command/...

Intel® PXA26x Processor Family Developer’s Manual 13-3 AC97 Controller Unit 13.4 AC-link Digital Serial Interface Protocol Each AC97 codec incorporates a five-pin digital serial interface that links it to the ACUNIT. AC-link is a full-duplex, fixed-clock, PCM digital stream. It employs a time divisi...

13-4 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit The ACUNIT provides synchronization for all data transaction on the AC-link. A data transaction is made up of 256 bits of information broken up into groups of 13 time slots and is called a frame. Time slot 0 is called the ta...

13-6 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit Note: When the ACUNIT transmits mono audio sample streams, software must ensure that the left and right sample stream time slots are filled with identical data. 13.4.1.1 Slot 0: Tag Phase In slot 0, the first bit is a global...

Intel® PXA26x Processor Family Developer’s Manual 13-7 AC97 Controller Unit 3. Write a non-zero value (0b01, 0b10, 0b11) to the codec ID field (slot 0, bits 1 and 0) 4. Specify the read/write direction of the access (slot 1, bit 19). 5. Specify the index to the codec register (slot 1, bits 18-12) 6....

13-8 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit 13.4.1.6 Slot 5: Modem Line Codec Audio output frame slot 5 contains the MSB justified modem DAC input data if the line codec is supported. The optional modem DAC input resolution can be implemented as 16, 18, or 20 bits. If...

Intel® PXA26x Processor Family Developer’s Manual 13-9 AC97 Controller Unit A new audio input frame begins when SYNC transitions from low to high. The low to high transition is synchronous to BITCLK’s rising edge. On BITCLK’s next falling edge, AC97 samples SYNC’s assertion. This falling edge marks ...

Intel® PXA26x Processor Family Developer’s Manual 13-11 AC97 Controller Unit Note: Slot requests for slots 3 and 4 are always set or cleared in tandem (both set or both cleared). 13.4.2.3 Slot 2: Status Data Port The status data port delivers 16-bit control register read data. Note: If slot 2 is tag...

13-12 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit 13.4.2.9 Slot 12: I/O Status The GPIOs configured as inputs return their status on this slot every frame. The data returned on the latest frame is accessible to software through the codec register at address 0x54 in the mod...

Intel® PXA26x Processor Family Developer’s Manual 13-13 AC97 Controller Unit 13.5.2 Waking up the AC-link 13.5.2.1 Wake up triggered by the Codec To wake up the AC-link a codec drives its SDATA_IN to a logic high level. The rising edge triggers the resume interrupt if that codec’s resume enable bit ...

13-14 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit 13.5.2.2.1 Cold AC97 Reset A cold reset is generated when the nACRESET pin is asserted through the GCR[COLD_RST]. Asserting and de-asserting nACRESET activates BITCLK (supplied by the codec) and SDATA_OUT. All AC97 control ...

Intel® PXA26x Processor Family Developer’s Manual 13-15 AC97 Controller Unit Note: After it is enabled, the ACUNIT requests the DMA immediately to fill the transmit FIFO. Note: The ACUNIT registers do not store the status of the DMA requests or information regarding the number of data samples in eac...

13-16 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit does not set the codec-ready bit, GCR[PCRDY] for the primary codec or GCR[SCRDY] for the secondary codec. 13.6.2 Trailing bytes If the transmit buffers do not have 32-byte resolution, the trailing bytes in the transmit FIFO...

Intel® PXA26x Processor Family Developer’s Manual 13-17 AC97 Controller Unit transmit valid data in certain frames. For example, if the controller sends out 480 frames, and the codec instructs the controller not to send valid data in 39 of those 480 frames, the codec would have in effect sampled dat...

13-18 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit 13.8.1.2 Receive FIFO Errors Channel-specific status bits are updated during receive overrun conditions and trigger interrupts when enabled. Refer to Table 13-13, “PCM_In Status Register” , Table 13-17, “Mic-In Status Regis...

Intel® PXA26x Processor Family Developer’s Manual 13-19 AC97 Controller Unit • Audio codec registers • Modem codec registers Channel specific data registers are for FIFO accesses and the PCM, modem, and mic-in FIFOs each have a register. A write access to one of these registers updates the written d...

13-20 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit 13.8.3.2 Global Control Register 0x4050_0118 MISR Modem In Status Register 0x4050_011C through 0x4050_013C — Reserved 0x4050_0140 MODR Modem FIFO Data Register 0x4050_0144 through 0x4050_01FC — Reserved (0x4050_0200 through...

Intel® PXA26x Processor Family Developer’s Manual 13-27 AC97 Controller Unit 13.8.3.10 Mic-In Control Register (MCCR) Figure 13-9. PCM Transmit and Receive Operation Table 13-16. Mic-In Control Register Physical Address 4050_0008 MCCR Register AC97 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

13-32 Intel® PXA26x Processor Family Developer’s Manual AC97 Controller Unit 13.8.3.18 Accessing Codec Registers Each codec has up to sixty-four 16-bit registers that are addressable internal to the codec at half-word boundaries (16-bit boundaries). Because the processor only supports internal regis...

14-2 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Sound Controller 14.2 Signal Descriptions SYSCLK is the clock on which all other clocks in the I 2 S unit are based. SYSCLK generates a frequency between approximately 2 MHz and 12.2 MHz by dividing down the PLL clock wi...

Intel® PXA26x Processor Family Developer’s Manual 14-3 Inter-Integrated Circuit Sound Controller To configure SYNC and SDATA_OUT as outputs, follow these steps: 1. Program SYSUNIT’s GPIO Direction Register (GPDR). See Section 4.1.3.2, “GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-9 ...

14-4 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Sound Controller 3. Optional: Programmed I/O may be used for priming the transmit FIFO with a few samples (ranging from 1 to 16). If the I2SLINK is enabled with an empty transmit FIFO, a Transmit Under-run error bit will...

Intel® PXA26x Processor Family Developer’s Manual 14-5 Inter-Integrated Circuit Sound Controller Asserting the DREC bit in SACR1 has the following effects: 1. I2SLINK recording activity is disabled. The frame or data sample, in the midst of which the recording is disabled, could have invalid data (s...

14-6 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Sound Controller The BITCLK, as shown in Table 14-2 , is different for different sampling frequencies. If the BITCLK is chosen as an output, the Audio Clock Divider Register divides the 147.46-MHz PLL clock to generate t...

Intel® PXA26x Processor Family Developer’s Manual 14-7 Inter-Integrated Circuit Sound Controller Figure 14-1 and Figure 14-2 provide timing diagrams that show formats for I 2 S and MSB-justified modes of operations. Data is transmitted and received in frames of 64 BITCLK cycles. Each frame consists ...

14-8 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Sound Controller • The Status Register signals the state of the FIFO buffers and the status of the interface that is selected by the common control register. • The Interrupt Registers include the Interrupt Mask Register,...

Intel® PXA26x Processor Family Developer’s Manual 14-9 Inter-Integrated Circuit Sound Controller NOTES: † If ENB is toggled in the middle of a normal operation, the RST bit must also be set and cleared to reset all I2SC registers. †† The SACR0[ENB] control signal crosses clock domains. It is registe...

14-10 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Sound Controller 14.6.1.2 Suggested TFTH and RFTH for DMA servicing The DMA controller can only be programmed to send 8, 16, or 32 bytes of data. This corresponds to 2, 4, or 8 FIFO samples. Table 14-5 shows the recomme...

Intel® PXA26x Processor Family Developer’s Manual 14-11 Inter-Integrated Circuit Sound Controller † SACR1 bits DRPL, DREC, and AMSL cross clock domains. They are registered in an internal clock domain that is much faster than the BITCLK domain. It takes 4 BITCLK cycles and 4 internal clock cycles be...

Intel® PXA26x Processor Family Developer’s Manual 14-13 Inter-Integrated Circuit Sound Controller 14.6.4 Serial Audio Clock Divider Register (SADIV) This register is used for generating six different BITCLK frequencies and hence six different sampling frequencies. All bits are read/write. Table 14-8...

14-14 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Sound Controller 14.6.6 Serial Audio Interrupt Mask Register (SAIMR) Writing a one to the corresponding bit position in the Interrupt Mask Register enables the corresponding interrupt signal. All bits are read/write. Ta...

Intel® PXA26x Processor Family Developer’s Manual 14-15 Inter-Integrated Circuit Sound Controller Figure 14-3. Transmit and Receive FIFO Accesses Through the SADR 14.6.8 Controller: Register Memory Map All registers are word addressable (32 bits wide) and hence increment in units of 0x00004. All I2S...

14-16 Intel® PXA26x Processor Family Developer’s Manual Inter-Integrated Circuit Sound Controller 14.7 Interrupts The following SASR0 status bits, if enabled, interrupt the processor: • Receive FIFO Service DMA Request (RFS) • Transmit FIFO Service DMA Request (TFS) • Transmit Under-run (TUR) • Rece...

Intel® PXA26x Processor Family Developer’s Manual 15-1 MultiMediaCard Controller 15 15.1 Overview The Intel® PXA26x Processor Family MultiMediaCard (MMC) controller acts as a link between the software used to access the processor and the MMC stack (a set of memory cards). The MMC controller is desig...

Intel® PXA26x Processor Family Developer’s Manual 15-3 MultiMediaCard Controller . In SPI mode, not all commands are available. The available commands have both a command and response token. The MMCMD and MMDAT signals are no longer bidirectional in SPI mode. The MMCMD is an output and the MMDAT is ...

15-4 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller Note: One- and three-byte data transfers are not supported with this controller. Data transfers of 10 or more bytes are supported for stream writes only. Refer to the MultiMediaCard System Specification, Version 2.1 for...

Intel® PXA26x Processor Family Developer’s Manual 15-5 MultiMediaCard Controller The MMCLK, MMCCS0, and MMCCS1 signals are routed through alternate functions within the GPIO. Refer to Section 4.1, “General-Purpose Input/Output” for a description of the process used to assign these signals to a speci...

15-6 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller address in the argument portion of the command token that is protected with a 7-bit CRC (see Table 15-1 ). For a description of the identification process when multiple cards are connected to a system, refer to the Card...

Intel® PXA26x Processor Family Developer’s Manual 15-7 MultiMediaCard Controller The command token is protected with a 7-bit CRC. The card always sends a response to a command token. The response token has four formats, including an 8-bit error response. The length of the response tokens is one, two...

15-8 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller 3. Restart the clock. Software must not stop the clock when it attempts to read the receive FIFOs or write the transmit FIFOs. When the clock stops, it resets the pointers in the FIFOs and any data left in the FIFOs can...

Intel® PXA26x Processor Family Developer’s Manual 15-11 MultiMediaCard Controller For the DMA, use three descriptors of 32 bytes and 32-byte bursts and one descriptor of two more bytes and 8-, 16- or 32-byte bursts and program the descriptor to set an interrupt, for the software to write the MMC_PRT...

15-12 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller — MMC_CLKRT — MMC_SPI — MMC_RESTO 4. Start the clock 5. Write 0x7b to the MMC_I_MASK register and wait for and verify the MMC_I_REG[END_CMD_RES] interrupt 6. Read the MMC_RES FIFO and MMC_STAT registers Some cards may ...

Intel® PXA26x Processor Family Developer’s Manual 15-13 MultiMediaCard Controller The MMC controller performs data transactions in all the basic modes: single block, multiple blocks, and stream modes. 15.3.2.1 Block Data Write In a single block data write, a block of data is written to a card. In a ...

15-14 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller In a block data read, the following parameters must be specified: • The data transfer is a read. • The block length, if the block length is different from the previous block data transfer or this is the first time that...

Intel® PXA26x Processor Family Developer’s Manual 15-15 MultiMediaCard Controller • The data transfer is a read. • The data transfer is in stream mode. • The block length, if the block length is different from the previous block data transfer or this is the first time that the parameter is being spe...

15-16 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller 15.4.1 Start and Stop Clock The set of registers is accessed by stopping the clock, writing the registers, and starting the clock. The software stops the clock, as follows: 1. Write 0x01 in MMC_STRPCL to stop the MMC c...

Intel® PXA26x Processor Family Developer’s Manual 15-17 MultiMediaCard Controller The software must not make changes in the set of registers until the end of the command and response sequence, after the clock is turned on. After the clock is turned on, the software must wait for the MMC_I_REG[END_CM...

15-18 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller 5. Wait for MMC_I_REG[PRG_DONE] interrupt. This interrupt indicates that the card has finished programming. Software may wait for MMC_I_REG[PRG_DONE] or start another command sequence on a different card. 6. Read the M...

Intel® PXA26x Processor Family Developer’s Manual 15-19 MultiMediaCard Controller The multiple block write mode also requires a stop transmission command, CMD12, after the data is transferred to the card. After the MMC_I_REG[DATA_TRAN_DONE] interrupt occurs, the software must program the controller ...

15-20 Intel® PXA26x Processor Family Developer’s Manual MultiMediaCard Controller 8. Set MMC_I_MASK to 0x1d. 9. Wait for MMC_I_REG[PRG_DONE] interrupt. This interrupt indicates that the card has finished programming. Software may wait for MMC_I_REG[PRG_DONE] interrupt or start another command sequen...

Intel® PXA26x Processor Family Developer’s Manual 15-21 MultiMediaCard Controller 15.5 MultiMediaCard Controller Register Descriptions The MMC controller is controlled by a set of registers that software configures before every command sequence on the MMC bus. Table 15-6 lists the address, name, and...

Intel® PXA26x Processor Family Developer’s Manual 16-1 Network/Audio Synchronous Serial Protocol Serial Ports 16 This chapter describes the signal definitions and operation of the Intel® PXA26x Processor Family Network and Audio Synchronous Serial Protocol (SSP) serial ports. The Network SSP (NSSP) ...

16-2 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports 16.3 Signal Description Table 16-1 lists the external signals between the SSP serial ports and external device. If any port is disabled, its pins are available for GPIO use. See Section 4.1,...

Intel® PXA26x Processor Family Developer’s Manual 16-3 Network/Audio Synchronous Serial Protocol Serial Ports 16.4.1 Processor and DMA FIFO Access The CPU or DMA accesses data through the SSP ports transmit and receive FIFOs. A CPU access takes the form of programmed I/O, transferring one FIFO entry...

16-4 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports 16.4.2.2 Removing Trailing Bytes In this case, no receive DMA service request is generated. To read out the trailing bytes, have the software wait for the time-out interrupt and then read al...

Intel® PXA26x Processor Family Developer’s Manual 16-5 Network/Audio Synchronous Serial Protocol Serial Ports • For PSP, the protocol allows for the configuration of which edge of the SSPSCLK is used for switching transmit data and the edge for sampling receive data. In addition, the idle state for ...

16-6 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports 16.4.3.2 SPI Protocol Details The SPI protocol has four possible sub-modes, depending on the SSPSCLK edges selected for driving data and sampling received data and on the selection of the ph...

Intel® PXA26x Processor Family Developer’s Manual 16-9 Network/Audio Synchronous Serial Protocol Serial Ports Note: When configured as either master or slave (to clock or frame) the SSP port continues to drive SSPTXD with the last bit of data sent (the LSB). If SSCR0[SSE] is cleared, SSPTXD goes low...

16-10 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports Note: When configured master the SSP port continues to drive SSPTXD with the last bit of data sent (the LSB) or it drives zero, depending on the status of SSPSP[ETDS]. If SSCR0[SSE] is clea...

Intel® PXA26x Processor Family Developer’s Manual 16-13 Network/Audio Synchronous Serial Protocol Serial Ports (SSCR1[SFRMDIR] is set) if the assertion of frame is not before the MSB is sent (For example, T5 <= T2 if SSCR1[SFRMDIR] is set). Transmit Data transitions from the “End of Transfer Data...

16-14 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports Note: If SSPSCLK is an input, the device driving SSPSCLK must provide another clock edge to cause the TXD line to go to Hi-Z. 16.4.4.2 Motorola SPI When SSCR1[TTE] is 0, the SSP behaves as ...

Intel® PXA26x Processor Family Developer’s Manual 16-15 Network/Audio Synchronous Serial Protocol Serial Ports Note: SSCR1[TTELP] must be 0 for National Semiconductor Microwire. 16.4.4.4 Programmable Serial Protocol When SSCR1[TTE] is 0, the SSP behaves as described in Section 16.4.3.4 . If SSCR1[TT...

Intel® PXA26x Processor Family Developer’s Manual 16-17 Network/Audio Synchronous Serial Protocol Serial Ports 16.4.5 FIFO Operation Two separate and independent FIFOs are present for transmit (to peripheral) and receive (from peripheral) serial data. FIFOs are filled or emptied by programmed I/O or...

16-18 Intel® PXA26x Processor Family Developer’s Manual Network/Audio Synchronous Serial Protocol Serial Ports 16.5 SSP Port Register Descriptions Each SSP port consists of seven registers: three control, one data, one status, one time-out, and one test. • The SSP control registers (SSCR0, SSCR1) co...

Intel® PXA26x Processor Family Developer’s Manual 16-27 Network/Audio Synchronous Serial Protocol Serial Ports 16.5.3 SSP Programmable Serial Protocol Register (SSPSP) SSPSPx, shown in Table 16-5 , contains bit fields used to program the various programmable serial- protocol parameters. The contents...

Intel® PXA26x Processor Family Developer’s Manual 17-1 Hardware UART 17 This chapter describes the signal definitions and operation of the Intel® PXA26x Processor Family Hardware UART (HWUART) port. The HWUART interface pins are available via either the PCMCIA general purpose I/O (GPIO) pins or the ...

Intel® PXA26x Processor Family Developer’s Manual 17-3 Hardware UART • Slow infrared asynchronous interface that conforms to the Infrared Data Association (IrDA) standard 17.3 Signal Descriptions Table 17-1 lists and describes each external signal that is connected to the UART module. The pins are c...

Intel® PXA26x Processor Family Developer’s Manual 17-7 Hardware UART Note: When DMA requests are enabled and an interrupt occurs, software must first read the LSR to see if an error interrupt exists, then check the IIR for the source of the interrupt. If an interrupt occurs and LSR[FIFOE] is clear, ...

Intel® PXA26x Processor Family Developer’s Manual 17-9 Hardware UART The SIR interface does not contain the actual IR LED driver or the receiver amplifier. The I/O pins attached to the SIR only have digital CMOS level signals. The SIR supports two-way communication, but full duplex communication is ...

17-10 Intel® PXA26x Processor Family Developer’s Manual Hardware UART Figure 17-4. XMODE Example. Note: The SIR TXD output pin is automatically held deasserted when the RCVEIR bit is set. Before setting the RCVEIR bit, check that the TEMT bit is 1. While receiving, any data placed in the transmit FI...

Intel® PXA26x Processor Family Developer’s Manual 17-11 Hardware UART 17.5.2 Transmit Holding Register (THR) In non-FIFO mode, the Transmit Holding Register (THR) holds the data byte(s) to be transmitted next. When the Transmit Shift Register (TSR) is emptied, the contents of the THR are loaded in t...

17-12 Intel® PXA26x Processor Family Developer’s Manual Hardware UART Load these divisor latches during initialization to ensure that the baud rate generator operates properly. If each divisor latch is loaded with a 0, the 16X clock stops. The divisor latches are accessed with a word write. The baud...

17-20 Intel® PXA26x Processor Family Developer’s Manual Hardware UART Note: Auto-baud rate detection is not supported with slow infrared Mode. See Section 17.4.4, “Auto-Baud-Rate Detection” for more information on auto-baud rate. 17.5.9 Auto-Baud Count Register (ACR) The ACR stores the number of 14....

Intel® PXA26x Processor Family Developer’s Manual 17-21 Hardware UART 17.5.10 Line Control Register (LCR) The Line Control Register (LCR) specifies the format for the asynchronous data communications exchange. The serial data format consists of a start bit, five to eight data bits, an optional parit...

Intel® PXA26x Processor Family Developer’s Manual 17-29 Hardware UART Note: When bit 0, 1, 2, or 3 is set, a Modem Status interrupt is generated if IER[MIE] is set. 17.5.14 Scratchpad Register (SPR) The read/write Scratchpad Register has no effect on the UART. It is intended as a scratchpad register...

17-30 Intel® PXA26x Processor Family Developer’s Manual Hardware UART 17.5.15 Infrared Selection Register (ISR) Each UART can manage an IrDA module associated with it. The Infrared Selection Register controls IrDA functions (see Section 17.4.5, “Slow Infrared Asynchronous Interface” on page 17-8 ). ...

Intel® PXA26x Processor Family Developer’s Manual 17-31 Hardware UART 17.6 Hardware UART Register Summary Table 17-20 contains the register addresses for the HWUART. 2 R/W XMODE TRANSMIT PULSE WIDTH SELECT: When XMODE is cleared, the UART 16X clock is used to clock the IrDA transmit and receive logi...

Intel® PXA26x Processor Family Developer’s Manual 18-1 Internal Flash 18 This chapter describes the flash interface for the Intel® PXA26x Processor Family. The PXA26x processor family has three devices that contain internal Intel StrataFlash® memory: • PXA261 processor – 128 megabit x 16 Intel Strat...

18-2 Intel® PXA26x Processor Family Developer’s Manual Internal Flash If watchdog reset is not necessary, a secondary GPIO can control nRESET_OUT using the equation nRST_F = nRESET & (nRESET_OUT | GPIO_a). This allows sleep-mode entry to reset the flash memory while keeping it in synchronous mod...

Intel® PXA26x Processor Family Developer’s Manual 18-3 Internal Flash Warning: Using a memory-clock frequency above 133 MHz is not allowed in synchronous mode with Intel StrataFlash® memory. 18.1.5 Configuring the Intel StrataFlash® Memory To configure the Intel StrataFlash® memory for synchronous o...

18-6 Intel® PXA26x Processor Family Developer’s Manual Internal Flash strh r9, [r8] ;/* No need for cache alignment since second flash chip */ ldrh r9, [r8] ;/* Read identifier second bus cycle, address=0x0 */ cmp r9, #0x89 ;/* Intel manufacturer code */ bne EndSynchronousMode ;//--- Write to second...