Fujitsu MHD2021AT - Manuals

Preface ii C141-E050-02EN Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alertmessage consists of an alert signal and alert statements. The alert signal consists ofan alert symbol and a signal word or just a signal word. The following are the...

Preface C141-E050-02EN iii Liability Exception “Disk drive defects” refers to defects that involve adjustment, repair, orreplacement. Fujitsu is not liable for any other disk drive defects, such as those caused by usermisoperation or mishandling, inappropriate operating environments, defects in thep...

C141-E050-02EN v Important Alert Items Important Alert Messages The important alert messages in this manual are as follows: A hazardous situation could result in minor or moderate personalinjury if the user does not perform the procedure correctly. Also,damage to the predate or other property, may o...

C141-E050-02EN vii Contents CHAPTER 1 Device Overview........................................................................ 1-1 1.1 Features 1-2 1.1.1 Functions and performance 1-2 1.1.2 Adaptability 1-2 1.1.3 Interface 1-3 1.2 Device Specifications 1-4 1.2.1 Specifications summary 1-4 1.2.2 Model...

Contents viii C141-E050-02EN CHAPTER 3 Installation Conditions ..............................................................3-1 3.1 Dimensions 3-2 3.2 Mounting 3-4 3.3 Cable Connections 3-8 3.3.1 Device connector 3-8 3.3.2 Cable connector specifications 3-9 3.3.3 Device connection 3-9 3.3.4 Power s...

Contents C141-E050-02EN ix 4.6.1 Read/write preamplifier (PreAMP) 4-9 4.6.2 Write circuit 4-10 4.6.3 Read circuit 4-12 4.6.4 Digital PLL circuit 4-13 4.7 Servo Control 4-14 4.7.1 Servo control circuit 4-14 4.7.2 Data-surface servo format 4-18 4.7.3 Servo frame format 4-18 4.7.4 Actuator motor contro...

Contents C141-E050-02EN xi CHAPTER 6 Operations ................................................................................. 6-1 6.1 Device Response to the Reset 6-2 6.1.1 Response to power-on 6-2 6.1.2 Response to hardware reset 6-4 6.1.3 Response to software reset 6-5 6.1.4 Response to diagno...

Contents xii C141-E050-02EN Illustrations Figures Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on 1-6 Figure 2.1 Disk drives outerview (The MHC Series and MHD Series) 2-2 Figure 2.2 Configuration of disk media heads 2-3 Figure 2.3 1 drive system configuration 2-4 Figure 2.4 2 dr...

Contents C141-E050-02EN xiii Figure 5.5 WRITE SECTOR(S) command protocol 5-73 Figure 5.6 Protocol for the command execution without data transfer 5- 75 Figure 5.7 Normal DMA data transfer 5-76 Figure 5.8 An example of generation of parallel CRC 5-90 Figure 5.9 Ultra DMA termination with pull-up or p...

C141-E050-02EN 1-1 CHAPTER 1 Device Overview 1.1 Features 1.2 Device Specifications 1.3 Power Requirements 1.4 Environmental Specifications 1.5 Acoustic Noise 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate 1.9 Media Defects Overview and features are described in this chapter, and specificati...

Device Overview 1-2 C141-E050-02EN 1.1 Features 1.1.1 Functions and performance The fillowing features of the MHC Series and MHD Series are described. (1) Compact The MHC2032AT and MHC2040AT have 2 or 3 disks of 65 mm (2.5 inches)diameter, and its height is 12.5 mm (0.492 inch). The MHD2032AT andMHD...

Device Overview 1-4 C141-E050-02EN 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specfications of the disk drives (MHC2032AT/MHC2040AT). Table 1.1 Specifications (MHC2032AT/MHC2040AT) MHC2032AT MHC2040AT Format Capacity (*1) 3.25 GB 4.09 GB Number of Heads 4 6 Number of ...

1.2 Device Specifications C141-E050-02EN 1-5 Table 1.2 shows the specfications of the disk drives (MHD2021AT/MHD2032AT). Table 1.2 Specifications (MHD2021AT/MHD2032AT) MHD2021AT MHD2032AT Format Capacity (*1) 2.16 GB 3.25 GB Number of Heads 3 4 Number of Cylinders (User) 7,290 7,322 Bytes per Sector...

Device Overview 1-6 C141-E050-02EN Model Formatted Capacity No. of Cylinder No. of Heads No. of Sectors MHC2032AT 3,253.46 MB 6,304 16 63 MHC2040AT 4,099.86 MB 7,944 16 63 MHD2021AT 2,167.60 MB 4,200 16 63 MHD2032AT 3,253.46 MB 6,304 16 63 1.2.2 Model and product number Table 1.3 lists the model nam...

1.3 Power Requirements C141-E050-02EN 1-7 (3) Current Requirements and Power Dissipation Table 1.4 lists the current and power dissipation. Table 1.4 Current and power dissipation Typical RMS Current Typical Power (*3) MHC Series MHD Series MHC Series MHD Series Spin up (*1) 0.9 A 0.9 A 4.5 W 4.5 W ...

Device Overview 1-8 C141-E050-02EN (5) Power on/off sequence The voltage detector circuits (the MHC Series and MHD Series) monitor +5 V.The circuits do not allow a write signal if either voltage is abnormal. Theseprevent data from being destroyed and eliminates the need to be concerned withthe power...

1.7 Reliability C141-E050-02EN 1-9 1.6 Shock and Vibration Table 1.7 lists the shock and vibration specification. Table 1.7 Shock and vibration specification Vibration (swept sine, one octave per minute) • Operating • Non-operating 5 to 500 Hz, 1.0G0-peak (MHC series)5 to 400 Hz, 1.0G0-peak (MHD ser...

C141-E050-02EN 2-1 CHAPTER 2 Device Configuration 2.1 Device Configuration 2.2 System Configuration This chapter describes the internal configurations of the hard disk drives and theconfiguration of the systems in which they operate.

Device Configuration 2-2 C141-E050-02EN 2.1 Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE),read/write preamplifier, and controller PCA. The disk enclosure contains the diskmedia, heads, spindle motors, actuators, and a circulating air filter. F...

2.1 Device Configuration C141-E050-02EN 2-3 0 4 5 Head MHC2040AT 2 1 3 0 Head MHC2032AT 2 1 3 0 Head MHD2032AT 3 1 2 0 Head MHD2021AT 1 2 Figure 2.2 Configuration of disk media heads (3) Spindle motor The disks are rotated by a direct drive Hall-less DC motor. (4) Actuator The actuator uses a revolv...

Device Configuration 2-4 C141-E050-02EN (5) Air circulation system The disk enclosure (DE) is sealed to prevent dust and dirt from entering. The diskenclosure features a closed loop air circulation system that relies on the blowereffect of the rotating disk. This system continuously circulates the a...

2.2 System Configuration C141-E050-02EN 2-5 2.2.3 2 drives connection MHC2032ATMHC2040AT MHC2032ATMHC2040AT (Host adaptor) Note: When the drive that is not conformed to ATA is connected to the disk drive aboveconfiguration, the operation is not guaranteed. Figure 2.4 2 drives configuration HA (host ...

C141-E050-02EN 3-1 CHAPTER 3 Installation Conditions 3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings This chapter gives the external dimensions, installation conditions, surfacetemperature conditions, cable connections, and switch settings of the hard diskdrives.

Installation Conditions 3-2 C141-E050-02EN 3.1 Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of themounting screw holes. All dimensions are in mm. Figure 3.1 Dimensions (MHC series) (1/2) MHD2032AT

3.2 Mounting C141-E050-02EN 3-5 (2) Frame The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frameis connected to SG. Use M3 screw for the mounting screw and the screw length shouldsatisfy the specification in Figure 3.3.The tightening torque must not exceed 3 kgcm.When attaching ...

Installation Conditions 3-8 C141-E050-02EN 3.3 Cable Connections 3.3.1 Device connector The disk drive has the connectors and terminals listed below for connectingexternal devices. Figure 3.6 shows the locations of these connectors andterminals. Figure 3.6 Connector locations (Sample: MHC2040AT) Con...

3.3 Cable Connections C141-E050-02EN 3-9 3.3.2 Cable connector specifications Table 3.2 lists the recommended specifications for the cable connectors. Table 3.2 Cable connector specifications Name Model Manufacturer Cable socket (44-pin type) 89361-144 BERG Cable (44-pin type) FV08-A440 Junkosha For...

Installation Conditions 3-10 C141-E050-02EN 3.3.4 Power supply connector (CN1) Figure 3.8 shows the pin assignment of the power supply connector (CN1). Figure 3.8 Power supply connector pins (CN1) 3.4 Jumper Settings 3.4.1 Location of setting jumpers Figure 3.9 shows the location of the jumpers to s...

3.4 Jumper Settings C141-E050-02EN 3-11 3.4.2 Factory default setting Figure 3.10 shows the default setting position at the factory. Figure 3.10 Factory default setting 3.4.3 Master drive-slave drive setting Master device (device #0) or slave device (device #1) is selected. Figure 3.11 Jumper settin...

Installation Conditions 3-12 C141-E050-02EN 3.4.4 CSEL setting Figure 3.12 shows the cable select (CSEL) setting. Note: The CSEL setting is not depended on setting between pins Band D. Figure 3.12 CSEL setting Figure 3.13 and 3.14 show examples of cable selection using unique interfacecables. By con...

C141-E050-02EN 4-1 CHAPTER 4 Theory of Device Operation 4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration 4.4 Power-on Sequence 4.5 Self-calibration 4.6 Read/write Circuit 4.7 Servo Control This chapter explains basic design concepts of the disk drive. Also, this chapterexplains subassemblies ...

Theory of Device Operation 4-2 C141-E050-02EN 4.1 Outline This chapter consists of two parts. First part (Section 4.2) explains mechanicalassemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains aservo information recorded in the disk drive and drive control method. 4.2 Subassem...

4.2 Subassemblies C141-E050-02EN 4-3 0 4 5 Head MHC2040AT 2 1 3 0 Head MHC2032AT 2 1 3 0 Head MHD2032AT 3 1 2 0 Head MHD2021AT 1 2 Figure 4.1 Head structure 4.2.3 Spindle The spindle consists of a disk stack assembly and spindle motor. The disk stackassembly is activated by the direct drive sensor-l...

Theory of Device Operation 4-4 C141-E050-02EN 4.3 Circuit Configuration Figure 4.2 shows the disk drive circuit configuration. (1) Read/write circuit The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) andread channel (RDC). The PreAMP consists of the write current switch c...

4.3 Circuit Configuration C141-E050-02EN 4-5 Figure 4.2 Circuit Configuration

4.5 Self-calibration C141-E050-02EN 4-7 Figure 4.3 Power-on operation sequence 4.5 Self-calibration The disk drive occasionally performs self-calibration in order to sense andcalibrate mechanical external forces on the actuator, and VCM tarque. Thisenables precise seek and read/write operations. 4.5...

4.6 Read/write Circuit C141-E050-02EN 4-9 Table 4.1 Self-calibration execution timechart Time elapsed Time elapsed (accumulated) 1 At power-on Initial calibration 2 About 5 minutes About 5 minutes 3 About 5 minutes About 10 minutes 4 About 10 minutes About 20 minutes 5 About 10 minutes About 30 minu...

Theory of Device Operation 4-10 C141-E050-02EN signal (WUS) when a write error occurs due to head short-circuit or headdisconnection. The Pre AMP sets the write current and bias current which flows through MRdevices. 4.6.2 Write circuit The write data is output from the hard disk controller (HDC) wi...

4.6 Read/write Circuit C141-E050-02EN 4-11 Figure 4.4 Read/write circuit block diagram

Theory of Device Operation 4-12 C141-E050-02EN 4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control(AGC) circuit. Then the output is converted into the sampled read data pulse bythe programmable filter circuit and the flash digitizer circuit. This clock ...

4.6 Read/write Circuit C141-E050-02EN 4-13 (3) Flash digitizer circuit This circuit is 10-tap sampled analog transversal filter circuit that cosine-equalizesthe head read signal to the partial response class 4 (EPR4) waveform. (4) Viterbi detection circuit The sample hold waveform output from the fl...

Theory of Device Operation 4-14 C141-E050-02EN 4.7 Servo Control The actuator motor and the spindle motor are submitted to servo control. Theactuator motor is controlled for moving and positioning the head to the trackcontaining the desired data. To turn the disk at a constant velocity, the actuator...

Theory of Device Operation 4-16 C141-E050-02EN Figure 4.7 Physical sector servo configuration on disk surface Servo frame(60 servo framesrevolution) Circumference direction Diameterdirection Erase: DC erase area CYL-n (n: even number)

Theory of Device Operation 4-18 C141-E050-02EN 4.7.2 Data-surface servo format Figure 4.7 describes the physical layout of the servo frame. The three areasindicated by (1) to (3) in Figure 4.7 are described below. (1) Inner guard band The head is in contact with the disk in this space when the spind...

C141-E050-02EN 5-1 CHAPTER 5 Interface 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands 5.4 Command Protocol 5.5 Ultra DMA Feature Set 5.6 Timing This chapter gives details about the interface, and the interface commands andtimings.

Interface 5-2 C141-E050-02EN 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. INTRQ: INTERRUPT REQUEST IOCS16-: 16-BIT I/OPDIAG: PASSED DIAGNOSTICS DASP-: DEVICE ACTIVE/SLAVE PRESENT DIOW-: I/O WRITESTOP: STOP DURING ULTRA DMA DATA BURSTS DIOR-: I/O READ HDMARDY...

5.1 Physical Interface C141-E050-02EN 5-3 5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Signal assignment on the interface connector Pin No. Signal Pin No. Signal A C E 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43...

Interface 5-6 C141-E050-02EN [signal] [I/O] [Description] DMARQ O This signal is used for DMA transfer between the host system andthe device. The device asserts this signal when the devicecompletes the preparation of DMA data transfer to the host system(at reading) or from the host system (at writin...

5.2 Logical Interface C141-E050-02EN 5-7 5.2.1 I/O registers Communication between the host system and the device is done through input-output (I/O) registers of the device. These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 toDA2 from the host system. Table 5.2. shows the...

5.3 Host Commands C141-E050-02EN 5-19 The implementation of the READ MULTIPLE command is identical to that of theREAD SECTOR(S) command except that the number of sectors is specified bythe SET MULTIPLE MODE command are transferred without interveninginterrupts. In the READ MULTIPLE command operation...

Interface 5-20 C141-E050-02EN Figure 5.2 Execution example of READ MULTIPLE command At command issuance (I/O registers setting contents) 1F7 H (CM) 1 1 0 0 0 1 0 0 1F6 H (DH) × L × DV Start head No. /LBA [MSB] 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) Start cylinder No. [MSB] / LBA Star...

Interface 5-32 C141-E050-02EN At command issuance (I/O registers setting contents) 1F7 H (CM) 1 1 1 0 1 1 0 0 1F6 H (DH) × × × DV xx 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (FR) xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7 H (ST) Status information 1F6 H (DH...

Interface 5-34 C141-E050-02EN Word Value Description 69-79 X’00’ Reserved 80 X’000E’ Major version number *11 81 X’0000’ Minor version number (not reported) 82 X’000B’ Support of command sets *12 83 X’4000’ Support of command sets (fixed) 84-87 X’00’ Reserved 88 X’xx07’ Ultra DMA transfer mode 89-12...

Interface 5-36 C141-E050-02EN Table 5.4 Information to be read by IDENTIFY DEVICE command (3 of 3) *9 Word 63: Multiword DMA transfer mode Bit 15-8: Currently used multiword DMA transfer mode Bit 7-0: Supportable multiword DMA transfer mode Bit 2=1 Mode 2 Bit 1=1 Mode 1 Bit 0=1 Mode 0 *10 Word 64: A...

Interface 5-38 C141-E050-02EN (14) SET FEATURES (X’EF’) The host system issues the SET FEATURES command to set parameters in theFeatures register for the purpose of changing the device features to be executed.For the transfer mode (Feature register = 03), detail setting can be done using theSector C...

5.3 Host Commands C141-E050-02EN 5-43 Table 5.6 Diagnostic code Code Result of diagnostic X’01’ X’03’ X’05’ X’8x’ No error detected. Data buffer compare error ROM sum check error Failure of device 1 attention: The device responds normally to this command without excuting internal diagnostic test. At...

Interface 5-54 C141-E050-02EN Table 5.7 Features Register values (subcommands) and functions Features Resister Function X’D0’ SMART Read Attribute Values: A device that received this subcommand asserts the BSY bit and saves allthe updated attribute values. The device then clears the BSY bit andtrans...

Interface 5-56 C141-E050-02EN At command completion (I-O registers setting contents) 1F7 H (ST) Status information 1F6 H (DH) × × × DV xx 1F5 H (CH) 1F4 H (CL) 1F3 H (SN) 1F2 H (SC) 1F1 H (ER) Key-failure prediction status (C2h-2Ch) Key-failure prediction status (4Fh-F4h) xx xx Error information The...

5.3 Host Commands C141-E050-02EN 5-57 Table 5.9 Format of insurance failure threshold value data Byte Item 00 01 Data format version number 02 Attribute 1 Attribute ID 03 Insurance failure threshold 04 to 0D Threshold 1(Threshold ofattribute 1) Reserved 0E to 169 Threshold 2 tothreshold 30 (The form...

5.3 Host Commands C141-E050-02EN 5-61 Table 5.10 Contents of security password Word Contents 0 Control word Bit 0: Identifier 0 = Compares the user passwords. 1 = Compares the master passwords. Bits 1 to 15: Reserved 1 to 16 Password (32 bytes) 17 to 255 Reserved At command issuance (I-O register co...

5.3 Host Commands C141-E050-02EN 5-65 (32) SECURITY SET PASSWORD (F1h) This command enables a user password or master password to be set. The host transfers the 512-byte data shown in Table 1.2 to the device. The devicedetermines the operation of the lock function according to the specifications of ...

Interface 5-66 C141-E050-02EN Table 5.12 Relationship between combination of Identifier and Security level, and operation of the lock function Indentifier Level Description User High The specified password is saved as a new user password. Thelock function is enabled after the device is turned off an...

Interface 5-70 C141-E050-02EN 5.4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0prior to issue a command. If BSY bit is 1, the host should wait for issuing acommand until BSY bit is cleared to 0. Commands can be executed only when the DRDY bit of ...

5.4 Command Protocol C141-E050-02EN 5-71 words, the host should receive the relevant sector of data (512 bytes of uninsureddummy data) or release the DRQ status by resetting. Figure 5.3 shows an example of READ SECTOR(S) command protocol, andFigure 5.4 shows an example protocol for command abort. Fi...

Interface 5-72 C141-E050-02EN sector in multiple-sector reading. If the timing to read the Status register does not meetabove condition, normal data transfer operation is not guaranteed. When the host new command even if the device requests the data transfer (setting in DRQbit), the correct device o...

Interface 5-76 C141-E050-02EN f) When the command execution is completed, the device clears both BSY andDRQ bits and asserts the INTRQ signal. Then, the host reads the Statusregister. g) The host resets the DMA channel. Figure 5.7 shows the correct DMA data transfer protocol. Figure 5.7 Normal DMA d...

5.5 Ultra DMA Feature Set C141-E050-02EN 5-77 5.5 Ultra DMA Feature Set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITEDMA commands. When this protocol is enabled it shall be used instead of theMultiword DMA protocol when these commands are issued by the host. T...

Interface 5-80 C141-E050-02EN f) Once the transmitting side has outputted the ending request, the output stateof STROBE signal should not be changed unless the receiving side hasconfirmed it. Then, if the STROBE signal is not in asserted state, Thetransmitting side should assert the STROBE signal. H...

5.5 Ultra DMA Feature Set C141-E050-02EN 5-89 13) The host shall neither negate STOP nor HSTROBE until at least t ACK after negating DMACK-. 14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t ACK after negating DMACK. 5.5.5 Ultra DMA CRC rules The following is a list ...

Interface 5-90 C141-E050-02EN Note: Since no bit clock is available, the recommended approach forcalculating CRC is to use a word clock derived from the bus strobe. Thecombinational logic shall then be equivalent to shifting sixteen bits seriallythrough the generator polynominal where DD0 is shifted...

5.5 Ultra DMA Feature Set C141-E050-02EN 5-91 5.5.6 Series termination required for Ultra DMA Series termination resistors are required at both the host and the device foroperation in any of the Ultra DMA Modes. The following table describesrecommended values for series termination at the host and t...

5.6 Timing C141-E050-02EN 5-93 Figure 5.10 Data transfer timing

Interface 5-96 C141-E050-02EN 5.6.4 Transfer of Ultra DMA data Figures 5.13 to 5.22 define the timings concerning every phase for the Ultra DMABurst. Table 5.13 includes the timing for each Ultra DMA mode. 5.6.4.1 Starting of Ultra DMA data In Burst The timing for each Ultra DMA mode is included in ...

5.6 Timing C141-E050-02EN 5-99 5.6.4.3 Sustained Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and DSTROBE are shown at both the host and the deviceto emphasize that cable setting time as well as cable propagationdelay shall not ...

Interface 5-100 C141-E050-02EN 5.6.4.4 Host pausing an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: 1) The host may assert STOP to request termination of the Ultra DMAburst no sooner than t RP after HDMARDY- is negated. 2) If the t SR ti...

5.6 Timing C141-E050-02EN 5-101 5.6.4.5 Device terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signallines are no longer in effect after DMARQ and DMACK arenegated. Figure 5.1...

Interface 5-102 C141-E050-02EN 5.6.4.6 Host terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signallines are no longer in effect after DMARQ and DMACK arenegated. Figure 5.17 H...

5.6 Timing C141-E050-02EN 5-103 5.6.4.7 Initiating an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signallines are not in effect until DMARQ and DMACK are asserted. Figure 5.18 Initiatin...

Interface 5-104 C141-E050-02EN 5.6.4.8 Sustained Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and HSTROBE signals are shown at both the device andthe host to emphasize that cable setting time as well as cablepropagation delay s...

5.6 Timing C141-E050-02EN 5-105 5.6.4.9 Device pausing an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: 1) The device may negate DMARQ to request termination of the UltraDMA burst no sooner than t RP after DDMARDY- is negated. 2) If the ...

Interface 5-106 C141-E050-02EN 5.6.4.10 Host terminating an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signallines are no longer in effect after DMARQ and DMACK arenegated. Figure 5.21...

5.6 Timing C141-E050-02EN 5-107 5.6.4.11 Device terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signallines are no longer in effect after DMARQ and DMACK arenegated. Figure 5....

Interface 5-108 C141-E050-02EN 5.6.5 Power-on and reset Figure 5.11 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present (2) Master and slave devices are present (2-drives configulation) Figure 5.23 Power on Reset Timing 31 Power-on Reset RESET – PDIAG- ne...

C141-E050-02EN 6-1 CHAPTER 6 Operations 6.1 Device Response to the Reset 6.2 Address Translation 6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache 6.6 Write Cache

Operations 6-2 C141-E050-02EN 6.1 Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when thepower of the IDD is turned on or the IDD receives a reset or diagnostic command. 6.1.1 Response to power-on After the master device (device 0) releases its own powe...

6.1 Device Response to the Reset C141-E050-02EN 6-3 Figure 6.1 Response to power-on 31 sec. 30 sec.

Operations 6-4 C141-E050-02EN 6.1.2 Response to hardware reset Response to RESET- (hardware reset through the interface) is similar to thepower-on reset. Upon receipt of hardware reset, the master device checks a DASP- signal for up to450 ms to confirm presence of a slave device. The master device r...

6.1 Device Response to the Reset C141-E050-02EN 6-5 6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If aslave device is present, the master device checks the PDIAG- signal for up to 15seconds to see if the slave device has completed the self-d...

Operations 6-6 C141-E050-02EN 6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTICcommand and the slave device is present, the master device checks the PDIAG-signal for up to 6 seconds to see if the slave device has completed the self-diagnosis successful...

6.2 Address Translation C141-E050-02EN 6-7 6.2 Address Translation When the IDD receives any command which involves access to the disk medium,the IDD always implements the address translation from the logical address (ahost-specified address) to the physical address (logical to physical addresstrans...

6.3 Power Save C141-E050-02EN 6-9 (2) LBA mode Logical address assignment in the LBA mode starts from physical cylinder 0,physical head 0, and physical sector 1. If the last sector in a zone of a physicalhead is used, the track is switched and the next LBA is assigned to the initialsector in the sam...

6.4 Defect Management C141-E050-02EN 6-11 When one of following commands is issued, the command is executed normallyand the device is still stayed in the standby mode. • Reset (hardware or software) • STANDBY command • STANDBY IMMEDIATE command • INITIALIZE DEVICE PARAMETERS command • CHECK POWER MO...

Operations 6-12 C141-E050-02EN 6.4.1 Spare area Following two types of spare area are provided for every physical head. 1) Spare cylinder for sector slip: used for alternating defective sectors at formatting in shipment (4 cylinders) 2) Spare cylinder for alternative assignment: used for automatic a...

6.4 Defect Management C141-E050-02EN 6-13 (2) Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder. This processing is performed when the alternate assignment is specified in theFORMAT TRACK command or when the automatic alternate processing ispe...

Operations 6-14 C141-E050-02EN 6.5 Read-Ahead Cache After read command which involes read data from the disk medium is completed,the read-ahead cache function reads the subsequent data blocks automatically andstores the data to the data buffer. When the next command requests to read the read-ahead d...

Operations 6-18 C141-E050-02EN 1) At receiving the sequential read command, the disk drive sets the DAP andHAP to the start address of the segment and reads the requested data from theload of the segment. Empty area Mis-hit data 2) The disk drive transfers the requested data that is already read to ...

Operations 6-22 C141-E050-02EN 3) The cache data for next read command is as follows. Cache data 6.6 Write Cache The write cache function of the drive makes a high speed processing in the casethat data to be written by a write command is physically sequent the data ofprevious command and random writ...

C141-E050-02EN GL-1 Glossary Actuator Head positioning assembly. The actuator consists of a voice coil motor and headarm. If positions the read-write (R-W) head. AT bus A bus between the host CPU and adapter board ATA (AT Attachment) standard The ATA standard is for a PC AT interface regulated to es...

Glossary C141-E050-02EN GL-3 Status The status is a piece of one-byte information posted from the drive to the hostwhen command execution is ended. The status indicates the commandtermination state. VCM Voice coil motor. The voice coil motor is excited by one or more magnets. Inthis drive, the VCM i...

C141-E050-02EN AB-1 Acronyms and Abbreviations A ABRT Abored command AIC Automatic idle control AMNF Address mark not found ATA AT attachment AWG American wire gage B BBK Bad block detected BIOS Basic input-output system C CORR Corrected data CH Cylinder high register CL Cylinder low register CM Com...

C141-E050-02EN IN-1 Index 1-drive connection 2-42-drive connection 2-58/8 GCR 4-108/9 GCR decoder 4-13 A Acceleration mode 4-21Acoustic noise 1-7Acoustic noise specification 1-7Active mode 6-10Actuator 2-3, 4-3Actuator motor control 4-19Adaptability 1-2Adaptive equalizer circuit 4-12ADC 4-17A/D conv...

C141-E050-01EN Comment Form We would appreciate your comments and suggestions regarding this manual. Manual code C141-E050-02EN Manual name MHC2032AT, MHC2040AT, MHD2032AT, MHD2021AT DISKDRIVES PRODUCT MANUAL Please mark each item: E(Excellent), G(Good), F(Fair), P(Poor). General appearance ( ) Tech...