Fujitsu MB91401 - Manuals

MB91401 5 ■ ■ ■ ■ PIN NUMBER TABLE Pin Number Pin name Pin Number Pin name Pin Number Pin name Pin Number Pin name 1 VSS 61 UDP 121 EXD11 181 SDA 2 CFD15 62 CFWEX 122 EXD14 182 USBINS 3 ICLK 63 CFCE1X 123 CFCD2X 183 UDM 4 ICS0 64 CFIORDX 124 UCLKSEL 184 CFRESET 5 TDI 65 CFA1 125 CFWAITX 185 CFREGX 6...

MB91401 6 ■ ■ ■ ■ PIN DESCRIPTION XINI 1 TXCLK 1 INITXI 1 TXD3 to TXD0 4 NMIX 1 TXEN 1 INT7 to INT5 3 RXCLK 1 MDI2 to MDI0 3 RXER 1 RXD3 to RXD0 4 OSCEA 1 RXDV 1 OSCC 1 RXCRS 1 OSCEB 1 COL 1 MDCLK 1 PLLS 1 MDIO 1 PLLSET1, PLLSET0 2 PLLBYPAS 1 EXCSX 1 CLKSEL 1 EXA 1 EXD15 to EXD0/GPIO7 to GPIO0 16 BR...

MB91401 9 UART (6 pin) MEMORY IF (66 pin) (Continued) Pin name Pin no. Polarity I/O Circuit Function/application SIN1SIN0 8515  IN D Serial data input pinsSerial data input pin of UART built-in FR core. SOUT1SOUT0 149 86  OUT F Serial data output pinsSerial data output pin of UART built-in FR core...

MB91401 10 (Continued) Pin name Pin no. Polarity I/O Circuit Function/application D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0 169110168109 42 218167108 41 166107 40 106 3938 105 36 165104 35 164103 34 216163102 33 162101 32 100 31  I/O B Data input/output ...

MB91401 19 ■ ■ ■ ■ HANDLING DEVICES Preventing Latch-up When a voltage that is higher than V DDE and a voltage that is lower than V SS are impressed to the input terminal and the output terminal in CMOS IC or the voltage that exceeds ratings between V DDE to V SS is impressed, the latch-up phenomeno...

MB91401 20 Figure When you share the power supply for digital and for VCO Treatment of the unused pins Leaving unused input pins open results in a malfunction, so process the pull-up or pull-down. Treatment of OPEN pins Be sure to use open pins in open state. Treatment of output pins A large current...

MB91401 21 ■ ■ ■ ■ CONNECTED SPECIFICATION OF MB91401 AND ICE Recommended type and circuit configuration of the emulator interface connector mounting on the user system,attention when designing and wiring regulation are shown.When the flat cable is used, the combination of the connectors with housin...

MB91401 26 CPU • The instruction fetch is not done from D-bus, and does not set the code area on D-bus RAM.• Set neither stack area nor the vector table on the instruction RAM.• The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS instruction is (a) ha...

MB91401 28 ■ ■ ■ ■ NOTES OF DEBUG Step execution of RETI instruction In an environment where interrupts frequently occur during single-step execution, only the relevant interruptprocessing routines are executed repeatedly during single-step execution of the RETI instruction. This will preventthe mai...

MB91401 29 ■ ■ ■ ■ BLOCK DIAGRAM FR core : CPU, U-Timer, UART, Timer, Interrupt controller, DMAC, Bit search, External interrupt, Memory_IF, Data-RAM, Cache, Bus controller Peripheral resources : LAN, External_IF, GPIO, Card, Encryption/Authentication, I 2 C, USB (Peripheral resource is connected to...

MB91401 30 ■ ■ ■ ■ MEMORY SPACE • Memory space The FR family has 4 GByte of logical addresses (2 32 address) which can be linearly accessed by the CPU. Direct Addressing Areas The following address space areas are used as I/O areas. These areas are called direct addressing areas, in which the addres...

MB91401 31 ■ ■ ■ ■ GENERAL PURPOSE REGISTERS Registers R0 to R15 are general-purpose registers. The registers are used as the accumulator and memoryaccess pointers for CPU operations. Of these 16 registers, the registers listed below are intended for special applications, for which some instructions...

MB91401 32 ■ ■ ■ ■ MODE SETTINGS The FR family uses the mode pins (MDI2 to MDI0) and the mode register (MODR) to set the operation mode. •••• Mode Pins Three mode pins MDI[2], MDI[1], and MDI[0] are used to specify a mode vector fetch or test mode. Setting MDI2 to MDI0 to "010", USRTEST is s...

MB91401 40 (Continued) * : The attribute is different according to the bit. Address Register Block ++++ 0 ++++ 1 ++++ 2 ++++ 3 0110_0028 H SMI_CMD[R/W] 00000000-00000000   SIM IF 0110_002C H SMI_CMD_ST [R/W] 00XXXXXX     0110_0030 H SMI_DATA [R/W] 00000000-00000000   0110_0034 H SMI_POLLINTV...

MB91401 42 (Continued) Address Register Block ++++ 0 ++++ 1 ++++ 2 ++++ 3 0540_0000 H FIFO0out[R] XXXXXXXX-XXXXXXXX FIFO0in[W] XXXXXXXX-XXXXXXXX USB 0540_0004 H FIFO1[R] XXXXXXXX-XXXXXXXX FIFO2[W] XXXXXXXX-XXXXXXXX 0540_0008 H FIFO3[W] XXXXXXXX-XXXXXXXX   0540_000C H to 0540_001F H (Reserved)  05...

MB91401 44 ■ ■ ■ ■ INTERRUPT VECTOR (Continued) Interrupt source Interrupt number Interrupt level Offset Address of TBR default RN Decimal Hexa- decimal Reset 0 00  3FC H 000FFFFC H  Mode vector 1 01  3F8 H 000FFFF8 H  System reserved 2 02  3F4 H 000FFFF4 H  System reserved 3 03  3F0 H 000FFF...

MB91401 47 ■ ■ ■ ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings *1 : This parameter is based on VSS = PLLVSS = 0 V. *2 : Note that analog power supply voltage and input voltage do not exceed VDDE + 0.3 V at power on. *3 : The maximum output current is the peak value for a single pin. *4 : ...

MB91401 48 2. Recommended Operating Conditions (VSS = PLLVSS = 0 V) WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device isoperated within these ran...

MB91401 49 3. DC Characteristics • Other than USB (VSS = PLLVSS = 0 V) Parameter Symbol Pin Conditions Value Unit Min Typ Max “H” level input voltage V IH   2.0  VDDE + 0.3 V “L” level input voltage V IL   VSS − 0.3  0.8 V “H” level output voltage V OH  V DDE = 3.0 V, I OH = 4.0 mA VDDE − 0.5...

MB91401 50 • USB (VSS = PLLVSS = 0 V) *1 : <About the output shor t-circuit current> Output short-circuit current I OS is the maximum current that flows when the output pin is connected to V DDE or V SS (within the maximum rating) . The current is “the short-circuit current per differential ou...

MB91401 52 *4 : <Output Levels V CRS > The cross voltage of the external differential output signals (D + and D − ) falls within the range from 1.3 V to 2.0 V. *5 : < Terminations V TERM > V TERM indicates the pull-up voltage at the upstream por t. D + Max 2.0 V Max 1.3 V D − V CRS stand...

MB91401 53 4. AC Characteristics The following measurement conditions depending on the supply voltage apply to the MB91401 unless otherwise specified. (1) Clock * : The clock frequency must be set to over 25 MHz for the Ethernet MAC interface to perform 100 Base communication. Parameter Symbol Pin C...

MB91401 54 (2) Reset Note : tcp is internal CPU and clock cycle period for peripheral module. Parameter Symbol Pin Conditions Value Unit Remarks Min Max Reset input time trstl INITXI After power supply & input clock stabilization At unusing of PLL 5 tcp  ns At using of PLL 600 + 1  µ s PLL res...

MB91401 60 • Reception RXCLK RXDV RXD3 to RXD0 thd_rxdv tsu_rxdv tsu_rxd thd_rxdv 0 5 5 RXCLK RXDV RXD3 to RXD0 thd_rxdv tsu_rxdv tsu_rxd thd_rxdv 0 n n − 1 RXCLK RXER tsu_rxer tsu_rxer thd_rxer thd_rxer Prelminary 2004.11.12

MB91401 61 (7) MDIO interface Parameter Symbol Pin typical timing Value Unit Remarks Min Max MDIO setup time tsu_mdio MDIO MDCLK ↑ 10  ns MDIO Hold Time thd_mdio MDIO MDCLK ↑ 0  ns MDIO delay time tdel_mdio MDIO MDCLK ↑ 10 30 ns MDIO switching time (IN → OUT) tdel_turnon MDIO MDCLK ↑ 10 30 ns MDIO...

MB91401 62 (8) External IF • Read access Note : tcp is internal CPU and operational clock period for peripheral module. Parameter Symbol Pin Value Unit Remarks Min Max EX Read Cycle time texrc EXA, EXCSX 6 × tcp  ns EXA to Data Valid texadv EXA, EXD 5 × tcp  ns EXCSX to Data Valid texcsdv EXCSX, E...

MB91401 64 (9) USB interface *1 : The AC characteristics of the USB interface conform to USB Specification Revision 1.1. *2 : < Driver Characteristics TFR, TFF, TFRFM> These items specify the differential data signal rise (trise) and fall (tfall) times.These are defined as the times between 10...

MB91401 65 T × D + T × D − 3-State Full-speed Buffer Rs Rs 28 Ω to 44 Ω Equiv. Imped 28 Ω to 44 Ω Equiv. Imped CL = 50 pF CL = 50 pF Notes : • Driver output impedance 3 Ω to 19 Ω • Rs series resistance: 25 Ω to 30 Ω • Add a series resistor of preferably 27 Ω Prelminary 2004.11.12

MB91401 69 ■ ■ ■ ■ ORDERING INFORMATION Part number Package Remarks MB91401 240-pin plastic FBGA (BGA-240P-M01) Prelminary 2004.11.12

MB91401 70 ■ ■ ■ ■ PACKAGE DIMENSION 240-pin plastic FBGA (BGA-240P-M01) Note: The actual shape of coners may differ from the dimension. Dimensions in mm (inches).Note : The values in parentheses are reference values. C 1999 FUJITSU LIMITED B240001S-2C-2 10.00±0.10(.394±.004)SQ (INDEX AREA) .044 Ð.0...

MB91401 FUJITSU LIMITED For fur ther information please contact: Japan FUJITSU LIMITEDMarketing DivisionElectronic DevicesShinjuku Dai-Ichi Seimei Bldg. 7-1,Nishishinjuku 2-chome, Shinjuku-ku,Tokyo 163-0721, JapanTel: +81-3-5322-3353Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South Am...