Fujitsu MB86617A - Manuals

LSI Specification MB86617A Rev.1.0 Fujitsu VLSI v 9.2. D ESCRIPTION OF E ACH I NSTRUCTION ............................................................................................................................................... 103 CHAPTER 10 INTERRUPT ............................................

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 1 Chapter 1 Overview This chapter explains the overview of MB86617A. MB86617A is Fujitsu’s IEEE1394 serial bus controller based on both IEEE1394 Standard (IEEE Std. 1394-1995) and P1394.a Standard Draft (rev.2.0). This MB86617A has three ports for net...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 2 Chapter 2 Features This chapter explains the features of MB86617A. > Compliant with IEEE1394 high performance serial bus standard and P1394.a standard draft > Integrates PHY and LINK layers into single-chip > 1394 port number : 3 ports >...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 3 Chapte r 3 Chip Block This chapter explains the MB86617A block diagram and the function of each block. 3.1. Block Diagram 3.2. Function of Each Block

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 4 3.1. Block Diagram MB86617A block diagram is shown below. < < Normal Operation Mode Fig.3.1.1 Block Diagram - Normal Operation Mode - 1394 Interface (Port 0) TPA0 XTPA0 TPB0 XTPB0 TPBIAS0 1394 Interface (Port 1) TPA1 XTPA1 TPB1 XTPB1 TPBIAS1 1...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 5 < < Asynchronous Transmit FIFO Extended Mode Fig.3.1.2 Block Diagram - Asynchronous Transmit FIFO Extended Mode - 1394 Interface (Port 0 ) TPA0 XTPA0 TPB0 XTPB0 TPBIAS0 1394 Interface (Port 1) TPA1 XTPA1 TPB1 XTPB1 TPBIAS1 1394 Interface (Port...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 6 < < Asynchronous Receive FIFO Extended Mode Fig.3.1.3 Block Diagram - Asynchronous Receive FIFO Extended Mode - 1394 Interface (Port 0) TPA0 XTPA0 TPB0 XTPB0 TPBIAS0 1394 Interface (Port 1) TPA1 XTPA1 TPB1 XTPB1 TPBIAS1 1394 Interface (Port 2)...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 7 3.2. Function of Each Block This section explains the function of each block for MB86617A. < < PHY Layer Control Circuit This circuit is for the Physical layer of IEEE 1394 with the following functions. > Asynchronous transfer is supported ...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 8 Chapter 4 Pin Assignment This chapter explains the pin assignment and table of pin function of MB86617A. 4.1. Pin Assignment 4.2. Corresponding Table of MB86617A Pin 4.3. Outline Drawing of Package

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 12 Chapter 5 Pin Function This chapter explains the MB86617A pin function. 5.1. IEEE1394 Interface 5.2. Isochronous (TSP-IC,DV-IC) Interface 5.4. MPU Interface 5.5. Other Pins 5.6. Power/GND Pin

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 19 Chapter 6 Internal Register This chapter explains the MB86617A internal register. Note that the access of internal register is applied only 16 bits access. WRITE READ Address (HEX) Register Name Register Name 0 0 mode-con trol mode-control 0 2 (res...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 25 Chapter 7 Internal Register Function Description This chapter explains the details of the internal register of MB86617A. 7.1. mode-control Register 7.2. flag & status Register 7.3. instruction fetch Register 7.4. interrupt-factor Indicate Regis...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 31 7.3. instruction-fetch Register instruction -fetch register is the register that writes in instructions for this LSI, and consists of the instruction code and operand. Refer to “Chapter 9 Instruction ” for each instruction code and operand code. AD...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 33 7.5. Receive Acknowledge Indicate Register Receive Acknowledge indicate register is the register that indicates received Acknowledge packet addressed to itself. Read out this register after interrupt report of “Asynchronous packet send”. AD R/W Bit...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 41 7.11. TSP Receive Information Setting Register T SP receive information setting register performs the setting for outputting received packet to TSP -IC AD R/W Bit 1 5 Bit 1 4 Bit 1 3 Bit 1 2 Bit 1 1 Bit 1 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 52 7.19. Data Bridge Receive Information Setting Register Data bridge receive information register performs the setting of receive packet. AD R/W Bit 1 5 Bit 1 4 Bit 1 3 Bit 1 2 Bit 1 1 Bit 1 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 68 7.30. Isochronous Channel Monitor Register Isochronous channel monitor register is the register that indicates Isochronous packet channel flowing through 1394 bus. AD R/W Bit 1 5 Bit 1 4 Bit 1 3 Bit 1 2 Bit 1 1 Bit 1 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 76 7.38. Transmit CGMS/TSCH Indicate Status Register Transmit CGMS/TSCH indicate status register indicates validity of source packet input from TSP IC I/F. AD R/W Bit 1 5 Bit 1 4 Bit 1 3 Bit 1 2 Bit 1 1 Bit 1 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit ...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 78 7.39. Transmit EMI/OE Setting Register Transmit EMI/OE setting register sets EMI information and Odd/Even value added to empty packet until valid data is transmitted. AD R/W Bit 1 5 Bit 1 4 Bit 1 3 Bit 1 2 Bit 1 1 Bit 1 0 Bit 9 Bit 8 Bit 7 Bit 6 Bi...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 80 Chapter 8 PHY/INK Register Function Description This chapter explains the Physical Register and Link register that enables to access from PHY/LINK register access port (address 62h) by setting PHYT/LINK register address setting register (address 60...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 83 8.2. Physical register #0 0 (read) Physical Register#00 is the register that indicates Physical ID, root status, and cable power st atus of this node. phy/ link - addr R/W Bit 1 5 Bit 1 4 Bit 1 3 Bit 1 2 Bit 1 1 Bit 1 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit ...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 85 8.4. Physical register #02 (read) Physical Register#02 is the register that indicates if the extended PHY register map is in existence or not, and the number of ports (3 port). phy/ link - addr R/W Bit 1 5 Bit 1 4 Bit 1 3 Bit 1 2 Bit 1 1 Bit 1 0 Bi...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 99 8.17. Link register #02 (read/write) Link Register#02 is the register that sets transfer mode of acknowledge packet transmitted by this node and disable setting of Link layer. phy/ link - addr R/W Bit 1 5 Bit 1 4 Bit 1 3 Bit 1 2 Bit 1 1 Bit 1 0 Bit...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 101 Chapter 9 Instruction This chapter explains the instruction codes and details for respective instructions. 9.1. Instruction Code Table 9.2. Description of Each Instruction

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 106 Chapter 10 Interrupt This chapter explains the inturrput -factors and method for interrupt-mask. 10.1. Interrupt-factor Indicator Register & interrupt-mask Setting Register 10.2. Interrupt 10.3. Description of Interrupt

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 112 Chapter 11 Operation This chapter explains the operation of this device and displays the examples of control flow. 11.1. Initialization 11.2. Self-ID Packet Receiving 11.3. Asynchronous Packet Transmitting 11.4. Asynchronous Packet Receiving 11.5....

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 113 11.1. Initialization The example of control flow from the system power on to the packet transmitting/receiving possible state is shown below. In this examle, the device is not operated with cable power supply before turning on the power of system....

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 115 11.2.1 Self-ID Packet Receive at Bus Reset Process This section explains the receiving process of Self-ID packet. The MB86617A device is capable of receiving self-ID packets that each mode transmit in the self-identity stage of bus reset process. ...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 116 < < Flow chart before bus reset completion <Host> <Device> Figure 11.2.1.1 Flow example for Self-ID packet receiving before bus reset completion Start bus reset. -ID store END ‘0’ Report Bus reset detected (INT4) interrupt. (asse...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 117 < < Flow chart after bus reset completion <Host> <Device> Figure 11.2.1.2 Flow example for Self-ID packet receiving after bus reset completed Note1: When Asyn- FIFO sel (mode-control register[3]) is 1 and send/rec (mode-control r...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 118 11.2.2 Self-ID Packet Receive after Transmitting Ping Packet Ping Regardless of s-ID store bit setting in the mode- cont rol register (refer to 7.1), the device receives self -ID packet after a ping packet transmitted and stores the data removing ...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 119 < < Flow chart after receiving Self-ID packet <Host> <Device> Figure 11.2.2.2 Flow example after receiving Self-ID packet. START Issue Asynchronous receive (03h) instruction. Read the data of one word from receive Asynchronous da...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 120 11.3. Asynchronous Packet Transmitting The example of control flow for transmitting of Asynchronous packet is shown below. < < Flow chart before storing transmitting data into Asynchronous transmit FIFO <Host> <Device> Figure 11....

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 130 Chapter 12 System Configuration This chapter explains the system configuration of this chip. 12.1. Recommended Connection for 1934 Port (for one port) 12.2. Recommended Connection for Cable Power Supply 12.3. Recommended Connection for Build-in PL...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 131 12.1. Recommended Connection for 1934 Port (for one port) The example of recommended connection of 1934 port terminal for one port is shown below. Figure 12.1 Recommended connection for 1934 port (for one port) For unused 1394 port, TPBIAS should ...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 132 12.2 Recommended Connection for Cable Power Supply The example of recommended connection of cable power supply for 1394 cable is shown below. Figure 12.2 Recommended connection for cable power supply 510K Ω ± 5% 91K Ω ± 5% CPS Cable Power (max 33V...

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 133 12.3. Recommended Connection for Build-in PLL Loop Filter The example of recommended connection for build-in PLL loop filter is shown below. FIL RF Figure 12.3 Recommended connection for build-in PLL loop filter 390 Ω ± 5% 3300pF ± 5% 5.1K Ω ± 5%

LSI S pecification MB86617A Rev.1.0 Fujitsu VLSI 134 12.4. Configuration of Feedback Circuit at Crystal Oscillator The example of configuration of feedback circuit at crystal oscillator is shown below. No outside resistance is needed because the feedback resistance is built -in.??? Figure 12.4 Confi...