Analog Devices ADSP-2183 - Manual
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Table of Contents:
- Page 5 – Table I. Interrupt Priority & Interrupt Vector Addresses; Interrupt Vector; IRQE
- Page 6 – Figure 3. External Crystal Connections; Reset
- Page 7 – PMOVLAY Memory; INTERNAL 8K; Data Memory; Figure 6. Data Memory; Memory Architecture; K INTERNAL
- Page 9 – Table VI. Boot Summary Table; MMAP; Bus Request & Bus Grant; BDMA Booting
- Page 10 – Description: The I/O space read and write instructions move
- Page 11 – Target Board Connector for EZ-ICE Probe; GND; Figure 7. Target Board Connector for EZ-ICE; Target Memory Interface
- Page 13 – ESD SENSITIVITY; ADSP-2181 TIMING PARAMETERS; GENERAL NOTES
- Page 14 – ENVIRONMENTAL CONDITIONS; Package; POWER DISSIPATION; Total Power Dissipation = P; = internal power dissipation from Power vs. Frequency; Pins; DMS; n MODES
- Page 15 – from which; Output Enable Time; ) is the interval from when; (at Maximum Ambient Operating Temperature); (at Maximum Ambient Operating; ) is the difference of t; and t
- Page 17 – ADSP-2183 TIMING PARAMETERS
- Page 19 – CAPACITIVE LOADING
- Page 20 – NOTE; Figure 22. Clock Signals
- Page 21 – NOTES; IRQx; Figure 23. Interrupts and Flags
- Page 22 – Figure 24. Bus Request–Bus Grant
- Page 23 – Figure 25. Memory Read
- Page 24 – Figure 26. Memory Write
- Page 25 – Figure 27. Serial Ports
- Page 26 – IACK; IS; Figure 28. IDMA Address Latch
- Page 31 – 28-Lead TQFP Package Pinout
- Page 32 – TQFP Pin Configurations
- Page 33 – OUTLINE DIMENSIONS
- Page 34 – 28-Lead PQFP Package Pinout
- Page 35 – PQFP Pin Configurations
- Page 37 – ORDERING GUIDE
FUNCTIONAL BLOCK DIAGRAM
a
DSP Microcomputers
ADSP-2181/ADSP-2183
FEATURES
PERFORMANCE
30 ns Instruction Cycle Time @ 5.0 Volts
33 MIPS Sustained Performance
34.7 ns Instruction Cycle Time @ 3.3 Volts
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 100 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
80K Bytes of On-Chip RAM, Configured as
16K Words On-Chip Program Memory RAM
16K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, & Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping
Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
128-Lead TQFP/128-Lead PQFP
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory
4 MByte Memory Interface for Storage of Data Tables &
Program Overlays
8-Bit DMA to Byte Memory for Transparent
Program and Data Memory Transfers
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals
Programmable Memory Strobe & Separate I/O Memory
Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
ICE-Port™ Emulator Interface Supports Debugging
in Final Systems
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
ICE-Port is a trademark of Analog Devices, Inc.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
GENERAL DESCRIPTION
The ADSP-2181/ADSP-2183 is a single-chip microcomputer
optimized for digital signal processing (DSP) and other high
speed numeric processing applications.
The ADSP-2181/ADSP-2183 combines the ADSP-2100 family
base architecture (three computational units, data address gen-
erators and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
Flag I/O, extensive interrupt capabilities, and on-chip program
and data memory.
The ADSP-2181/ADSP-2183 integrates 80K bytes of on-chip
memory configured as 16K words (24-bit) of program RAM,
and 16K words (16-bit) of data RAM. Power down circuitry is
also provided to meet the low power needs of battery operated
portable equipment. The ADSP-2181 is available in 128-pin
TQFP and 128-pin PQFP packages; the ADSP-2183 is avail-
able in the TQFP package only.
In addition, the ADSP-2181/ADSP-2183 supports new instruc-
tions, which include bit manipulations—bit set, bit clear, bit toggle,
bit test—new ALU constants, new multiplication instruction
(x squared), biased rounding, result free ALU operations, I/O memory
transfers, and global interrupt masking, for increased flexibility.
Fabricated in a high speed, double metal, low power, 0.5
µ
m
CMOS process, the ADSP-2181 operates with a 30 ns instruc-
tion cycle time (34.7 ns for the ADSP-2183). Every instruction
can execute in a single processor cycle.
The ADSP-2181/ADSP-2183’s flexible architecture and com-
prehensive instruction set allow the processor to perform multiple
operations in parallel. In one processor cycle the ADSP-2181/
ADSP-2183 can:
• generate the next program address
• fetch the next instruction
• perform one or two data moves
• update one or two data address pointers
• perform a computational operation
SERIAL PORTS
MEMORY
FLAGS
PROGRAMMABLE
I/O
BYTE DMA
CONTROLLER
PROGRAM
MEMORY
DATA
MEMORY
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
DMA
BUS
INTERNAL
DMA
PORT
TIMER
SPORT 1
SPORT 0
ADSP-2100 BASE
ARCHITECTURE
SHIFTER
MAC
ALU
ARITHMETIC UNITS
POWERDOWN
CONTROL
PROGRAM
SEQUENCER
DAG 0
DAG 1
DATA ADDRESS
GENERATORS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
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Summary
ADSP-2181/ADSP-2183 REV. 0 – 5 – Table I. Interrupt Priority & Interrupt Vector Addresses Interrupt Vector Source of Interrupt Address (Hex) Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority) Power Down (Nonmaskable) 002C IRQ2 0004 IRQL1 0008 IRQL0 000C SPORT0 Transmit 0010 SPORT0 Receive...
ADSP-2181/ADSP-2183 REV. 0 – 6 – When the IDLE (n) instruction is used, it effectively slows downthe processor’s internal clock and thus its response time to in-coming interrupts. The one-cycle response time of the standardidle state is increased by n, the clock divisor. When an enabledinterrupt is ...
ADSP-2181/ADSP-2183 REV. 0 – 7 – Table II. PMOVLAY Memory A13 A12:0 0 Internal Not Applicable Not Applicable 1 External 0 13 LSBs of Address Overlay 1 Between 0x2000and 0x3FFF 2 External 1 13 LSBs of Address Overlay 2 Between 0x2000and 0x3FFF This organization provides for two external 8K overlay se...
