Page 3 - Table of Contents
© 2008 Advanced Micro Devices, Inc. Table of Contents AMD SB600 Register Reference Manual Proprietary Page 3 Table of Contents 1 Introduction ............................................................................................................. 7 1.1 About this Manual............................
Page 5 - List of Figures
© 2008 Advanced Micro Devices, Inc. List of Figures AMD SB600 Register Reference Manual Proprietary Page 5 List of Figures Figure 1 SB600 PCI Internal Devices .......................................................................................................................... 11 Figure 2 SB600 ...
Page 6 - List of Tables
© 2008 Advanced Micro Devices, Inc. List of Tables AMD SB600 Register Reference Manual Proprietary Page 6 List of Tables Table 1-1: Register Description Table Notation—Example ............................................................................................ 7 Table 2-1 HcRevision Register...
Page 7 - Introduction; About this Manual; Updates; Table 1-1: Register Description Table Notation—Example; Field Name; time granularity of 8 clocks.
© 2008 Advanced Micro Devices, Inc. About this Manual AMD SB600 Register Reference Manual Proprietary Page 7 1 Introduction 1.1 About this Manual This manual is a register reference guide for the AMD SB600 Southbridge. It integrates the key I/O, communications, and audio features required in a state...
Page 8 - Register Information; the system to behave in unexpected manners.
© 2008 Advanced Micro Devices, Inc. Nomenclature and Conventions AMD SB600 Register Reference Manual Proprietary Page 8 Register Information Value/Content in the Example Register name Latency Timer Read / Write capability R = Readable W = Writable RW = Readable and Writable RW Register size 8 bits R...
Page 10 - AC Link interface
© 2008 Advanced Micro Devices, Inc. Features of the SB600 AMD SB600 Register Reference Manual Proprietary Page 10 AC Link interface Supports for both audio and modem codecs Compliant with AC-97 codec Rev. 2.3 6/8 channel support on audio codec Multiple functions for audio and modem Codec ope...
Page 11 - Block Diagrams; This section contains two block diagrams for the SB600.; Figure 1 SB600 PCI Internal Devices
© 2008 Advanced Micro Devices, Inc. Block Diagrams AMD SB600 Register Reference Manual Proprietary Page 11 1.4 Block Diagrams This section contains two block diagrams for the SB600. Figure 1 shows the SB600 internal PCI devices with their assigned bus, device, and function numbers. Figure 2 shows th...
Page 12 - Figure 2 SB600 PCI Internal Devices and Major Function Blocks
© 2008 Advanced Micro Devices, Inc. Block Diagrams AMD SB600 Register Reference Manual Proprietary Page 12 SATA Controller AC97 Audio IDE LPC PCI Bridge SMBUS /ACPI AB AC97 Modem HD Audio PORT 1 PORT 0 USB:OHCI USB:EHCI 8250 TIMER GPIO BM RTC ACPI / HW Monitor SMBUS ROM BUS Controler PIC APIC INTERR...
Page 13 - Register Descriptions: PCI Devices; SATA; PCI Configuration Space; Register Name
© 2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 13 2 Register Descriptions: PCI Devices 2.1 SATA Registers (Device 18, Function 0) Note: Some SATA functions are controlled by, and associated with, certain PCI configurati...
Page 19 - PCI Power
© 2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 19 MSI Control - RW- 32 bits - [PCI_Reg:50h] Field Name Bits Default Description Capability ID 7:0 05h Read-Only. Capability ID. It indicates that this is and MSI capabilit...
Page 20 - All register accesses to IDP Data are Dword granularity
© 2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 20 PCI Power Management Control And Status - RW- 16 bits - [PCI_Reg:64h] Field Name Bits Default Description Power State 1:0 00b This field is used both to determine the cu...
Page 21 - Port0 PHY
© 2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 21 PHY Port0 Control - RW- 32 bits - [PCI_Reg:88h] Field Name Bits Default Description Port0 PHY 23:0 B40014h PHY port0 fine-tune register. TX main driver swing 4:0 10100b ...
Page 22 - TX pre-emphasis enable
© 2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 22 PHY Port1 Control - RW- 32 bits - [PCI_Reg:8Ch] Field Name Bits Default Description TX pre-emphasis driver swing 7:5 000b Port1 Tx driving swing[7:5] is valid for both S...
Page 23 - Port3 PHY
© 2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 23 PHY Port3 Control - RW- 32 bits - [PCI_Reg:94h] Field Name Bits Default Description Port3 PHY 23:0 B40014h PHY port3 fine-tune register. TX main swing 4:0 10100b Port3 T...
Page 25 - Reserved; Host
© 2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 25 Bus-master IDE Status - RW- 8 bits - [IO_Reg: BAR4 + 02/0Ah] Field Name Bits Default Description Bus Master Active 0 0b Bus Master IDE active. This bit is set to 1 when ...
Page 27 - 3:20 2h Indicates the maximum speed the HBA can support on its; HBA supports the PxSNTF
© 2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 27 HBA Capabilities – R - 32bits [Mem_reg: ABAR + 00h] Field Name Bits Default Description Supports Port Multiplier (SPM) 17 1b Indicates whether the HBA can support a Port...
Page 28 - by hardware when any of the
© 2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 28 HBA Capabilities – R - 32bits [Mem_reg: ABAR + 00h] Field Name Bits Default Description Supports Native Command Queuing (SNCQ) 30 1b Indicates whether the HBA supports S...
Page 29 - Write 1 to clear these status bits.
© 2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 29 Global HBA Control – RW - 32bits [Mem_reg: ABAR + 04h] Field Name Bits Default Description AHCI Enable (AE) 31 0b When set, indicates that communication to the HBA shall...
Page 31 - Port-N Command List Base Address Upper 32-
© 2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 31 2.1.4.2 Port Registers (One Set Per Port) The algorithm for the software to determine the offset is as follows: • Port offset = 100h + (PI Asserted Bit Position * 80h) R...
Page 32 - Current Connect Status
© 2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 32 Port-N FIS Base Address Upper –RW – 32 bits [Mem_reg: ABAR + port offset + 0Ch] Field Name Bits Default Description FIS Base Address Upper (FBU) 31:0 0000_ 0000h Indicat...
Page 42 - This field is not used by
© 2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 42 Port-N Serial ATA Error – RW – 32 bits [Mem_reg: ABAR + port offset + 30h] Field Name Bits Default Description Diagnostics (DIAG) 31:16 0000h Contains diagnostic error i...
Page 43 - PMN
© 2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 43 Port-N Serial ATA Active – RW – 32 bits [Mem_reg: ABAR + port offset + 34h] Field Name Bits Default Description Device Status (DS) 31:0 00000000h This field is bit signi...
Page 44 - OCHI USB 1.1 and EHCI USB 2.0 Controllers; USB; OHCI0 – PCI config
© 2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 44 2.2 OCHI USB 1.1 and EHCI USB 2.0 Controllers Note: Some USB functions are controlled by, and associated with, certain PCI configuration registers in the SMBus/ACPI d...
Page 45 - ID
© 2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 45 Register Name Offset Address Device / Vendor ID 00h Command 04h Status 06h Revision ID / Class Code 08h Miscellaneous 0Ch BAR_OHCI 10h Subsystem Vendor ID / Subsystem...
Page 53 - HcBulkCurrentED; HostControllerFunctionalState; HcInterruptStatus
© 2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 53 HcControl - 32 bits - [MEM_Reg : 04h] Field Name Bits Default HCD HC Description IE 3 0b RW R IsochronousEnable This bit is used by HCD to enable/disable processing o...
Page 54 - HcInterruptStatu; InterruptRouting
© 2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 54 HcControl - 32 bits - [MEM_Reg : 04h] Field Name Bits Default HCD HC Description IR 8 0b RW R InterruptRouting This bit determines the routing of interrupts generated...
Page 55 - OwnershipChangeRequest
© 2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 55 HcCommandStatus - 32 bits - [MEM_Reg : 08h] Field Name Bits Default HCD HC Description CLF 1 0b RW RW ControlListFilled This bit is used to indicate whether there are...
Page 58 - PeriodCurrentED
© 2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 58 HcPeriodCurrentED - 32 bits - [MEM_Reg : 1Ch] Field Name Bits Default HCD HC Description Reserved 3:0 Reserved PCED 31:4 0000000 h R RW PeriodCurrentED This is used b...
Page 59 - FSLargestDataPacket
© 2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 59 HcBulkCurrentED - 32 bits - [MEM_Reg : 2Ch] Field Name Bits Default HCD HC Description BCED 31:4 0000000 h RW RW BulkCurrentED This is advanced to the next ED after t...
Page 60 - PeriodicStart
© 2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 60 HcFmRemaining - 32 bits - [MEM_Reg : 38h] Field Name Bits Default HCD HC Description FR 13:0 0000h R RW FrameRemaining This counter is decremented at each bit time. W...
Page 61 - NumberDownstreamPorts
© 2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 61 HcRhDescriptorA - 32 bits - [MEM_Reg : 48h] Field Name Bits Default HCD HC Description NDP 7:0 02h R R NumberDownstreamPorts These bits specify the number of downstre...
Page 67 - Host Controller Mapping
© 2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 67 standard OpenHCI descriptor-based accesses. The emulation code sets up the appropriate Endpoint Descriptors and Transfer Descriptors that cause data to be sent to or ...
Page 70 - HceControl Register; Registers
© 2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 70 HceControl Register Table 2-7 HceControl Register HceControl - 32 bits Field Name Bits Reset Description EmulationEnable 0 0b When set to 1, the HC is enabled for leg...
Page 79 - Interrupt on Async
© 2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 79 USBLEGCTLSTS – RW - 32 bits - [PCI_Reg : EECP + 04h] Field Name Bits Default Description SMI on OS Ownership Enable 13 0b When this bit is a one AND the OS Ownership ...
Page 81 - Frame List Size
© 2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 81 HCSPARAMS – R - 32 bits - [MEM_Reg : 04h] Field Name Bits Default Description Reserved 19:17 These bits are reserved and should be set to zero. Debug Port Number 23:2...
Page 82 - Port Routing Rules
© 2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 82 HCSP-PORTROUTE – R - 60 bits - [MEM_Reg : 0Ch] Description This optional field is valid only if Port Routing Rules field in the HCSPARAMS register is set to a one. Th...
Page 83 - HCHalted
© 2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 83 USBCMD – RW - 32 bits - [EOR_Reg : EHCI_EOR + 00h] Field Name Bits Default Description Host Controller Reset (HCRESET) 1 0b This control bit is used by software to re...
Page 84 - Asynchronous Park Capability
© 2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 84 USBCMD – RW - 32 bits - [EOR_Reg : EHCI_EOR + 00h] Field Name Bits Default Description Asynchronous Schedule Park Mode Count (Optional) 9:8 00b If the Asynchronous Pa...
Page 94 - Port
© 2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 94 Control / Status – RW - 32 bits - [DBUG_Reg : DBase + 00h] Field Name Bits Default Description Enabled 28 0b This bit is a one if the debug port is enabled for operat...
Page 113 - SmartVoltEnable2
© 2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 113 SmartPowerControl2C - RW – 8 bits - [PCI_Reg: 9Ah] Field Name Bits Default Description SmartVoltEnable2 7 0b Enable bit for the SmartPower2 function. When ...
Page 126 - Control; Dma_WriteRequest 09h
© 2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 126 2.3.3 Legacy ISA and ACPI Controller 2.3.3.1 Legacy Block Registers There are two sets of registers in the ACPI/SMBus module. The first set is in the PCI c...
Page 159 - AzaliaStatus
© 2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 159 SmiSciSts2 - RW – 8 bits - [PM_Reg: 5Ch] Field Name Bits Default Description ExtEvent0Status 0 0b This bit indicates the SMI# status of ExtEvent0 to SCI/Wa...
Page 165 - FFh
© 2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 165 S0S3ToS5Enable0 – RW – 8 bits – [PM_Reg:76h] Field Name Bits Default Description S0S3ToS5Enable0 register S0S3ToS5Enable1 – RW – 8 bits – [PM_Reg:77h] Fiel...
Page 195 - Bus-master IDE Command Register; Primary – Base + 00h
© 2008 Advanced Micro Devices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Reference Manual Proprietary Page 195 IDE Dynamic Clocking - RW- 20 bits - [PCI_Reg:6Ch] Field Name Bits Default Description IDE Power Down Counter 19:0 FFFFFh The IDE power down counter can be programmed t...
Page 196 - Bus-master IDE Status Register; Primary – Base + 02h; Descriptor Table Pointer Register
© 2008 Advanced Micro Devices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Reference Manual Proprietary Page 196 Bus-master IDE Command - RW- 8 bits - [IDE:00h] Field Name Bits Default Description Bus Master IDE Start/Stop 0 0b Bus Master IDE Start (1)/Stop (0). This bit will not ...
Page 197 - Name and Function
© 2008 Advanced Micro Devices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Reference Manual Proprietary Page 197 Address (hex) Name and Function Compatibility Mode Native Mode (Offset) Read Function Write Function 1F1 Base Address 0 + 1 Error register Features register 1F2 Base Ad...
Page 198 - AC ’97 Controller Functional Descriptions; PCI Configuration Registers
© 2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 198 2.5 AC ’97 Controller Functional Descriptions 2.5.1 Audio Registers (Device 20, Function 5) The PCI based registers for Audio are defined according to the PCI 2.1 sp...
Page 203 - Audio Memory Mapped Registers; Name
© 2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 203 UnMask Latency Timer Expiration W - 32 bits - [PCI_Reg: 50h] Field Name Bits Default Description UnMask Latency Timer Expiration 0 0b When this bit is set to 0, late...
Page 212 - Audio Phy semaphore
© 2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 212 Audio Phy Semaphore Reg- RW - 8 bits - [MEM_Reg: A8h] Field Name Bits Default Description Audio Phy semaphore 0 0b PHY is ready for Audio to access: 0 = PHY is not r...
Page 226 - Output DMA3 Fifo Flush
© 2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 226 Modem Fifo Flush– W - 32 bits - [MEM_Reg: 88h] Field Name Bits Default Description Output DMA3 Fifo Flush 2 0b Writing to this bit flushes modem output DMA3 fifo, i....
Page 227 - HD Audio Controllers Registers; Vendor ID
© 2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 227 2.6 HD Audio Controllers Registers Note: Some HD Audio functions are controlled by, and associated with, certain PCI configuration registers in the SMBus/ACPI device. For more ...
Page 237 - Stream Interrupt Enable
© 2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 237 Input Stream Payload Capability – R – 16 bits - [Mem_Reg: Base + 1Ah] Field Name Bits Default Description Input Stream Payload Capability 15:0 0000h This field indicates the ma...
Page 239 - CORB Write Pointer
© 2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 239 CORB Upper Base Address – RW – 32 bits – [Mem_Reg: Base + 44h] Field Name Bits Default Description CORB Upper Base Address 31:0 00000000 h Upper 32 bits address of the CORB. Th...
Page 242 - Immediate Result Valid
© 2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 242 Immediate Command Output Interface – RW – 32 bits – [Mem_Reg: Base + 60h] Field Name Bits Default Description Immediate Command Write 31:0 00000000 h The value written into thi...
Page 243 - Stream Descriptor Control – RW – 24 bits; Stream Reset
© 2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 243 DMA Position Lower Base Address – RW – 32 bits – [Mem_Reg: Base + 70h] Field Name Bits Default Description DMA Position Lower Base Address 31:7 0000000h Contains the upper 25 b...
Page 244 - Stripe Control
© 2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 244 Stream Descriptor Control – RW – 24 bits Input Stream 0 - [Mem_Reg: Base + 80h] Input Stream 1 - [Mem_Reg: Base + A0h] Input Stream 2 - [Mem_Reg: Base + C0h] Input Stream 3 - [...
Page 245 - Stream Descriptor Status – RW – 8 bits
© 2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 245 Stream Descriptor Status – RW – 8 bits Input Stream 0 - [Mem_Reg: Base + 83h] Input Stream 1 - [Mem_Reg: Base + A3h] Input Stream 2 - [Mem_Reg: Base + C3h] Input Stream 3 - [Me...
Page 246 - Stream Descriptor Cyclic Buffer Length – RW – 32 bits; Cyclic Buffer Length; Stream Descriptor Last Valid Index – RW – 16 bits; Last Valid Index
© 2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 246 Stream Descriptor Cyclic Buffer Length – RW – 32 bits Input Stream 0 - [Mem_Reg: Base + 88h] Input Stream 1 - [Mem_Reg: Base + A8h] Input Stream 2 - [Mem_Reg: Base + C8h] Input...
Page 247 - Stream Descriptor FIFO Size – R – 16 bits
© 2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 247 Stream Descriptor FIFO Size – R – 16 bits Input Stream 0 - [Mem_Reg: Base + 90h] Input Stream 1 - [Mem_Reg: Base + B0h] Input Stream 2 - [Mem_Reg: Base + D0h] Input Stream 3 - ...
Page 248 - Stream Descriptor BDL Pointer Lower Base Address – RW – 32 bits; Stream Descriptor BDL Pointer Upper Base Address – RW – 32 bits; Wall Clock Counter Alias; Stream Descriptor Link Position in Buffer Alias – R – 32 bits
© 2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 248 Stream Descriptor BDL Pointer Lower Base Address – RW – 32 bits Input Stream 0 - [Mem_Reg: Base + 98h] Input Stream 1 - [Mem_Reg: Base + B8h] Input Stream 2 - [Mem_Reg: Base + ...
Page 249 - Register Descriptions: PCI Bridges; LPC; Interface
© 2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 249 3 Register Descriptions: PCI Bridges 3.1 LPC ISA Bridge (Device 20, Function 3) Note: Some LPC functions are controlled by, and associated with, certain PCI configurati...
Page 256 - Rom Start Address 1
© 2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 256 LPC ROM Address Range 1 (Start Address) - RW - 16 bits - [PCI_Reg: 68h] Field Name Bits Default Description Rom Start Address 1 15:0 0eh (if iLpc_Rom strap is enabled),...
Page 257 - Read
© 2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 257 Firmware Hub Select – RW* - 32 bits - [PCI_Reg: 70h] Field Name Bits Default Description FWH_D8_IDSEL 15:12 4h IDSEL for two 512 KB FWH memory ranges. The IDSEL program...
Page 258 - Msi On
© 2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 258 Miscellaneous Control Bits- RW - 8 bits - [PCI_Reg: 78h] Field Name Bits Default Description Msi On 1 0b When this bit is set to 1, it turns on LPC MSI capability. The ...
Page 260 - IO Base Address 2; SPI ROM Controller Registers
© 2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 260 TMKBC_Remap Register- RW - 16 bits - [PCI_Reg: 8Ch] Field Name Bits Default Description TMKBC_Remap 15:8 00h This register defines the remap address [15:8] on the LPC b...
Page 264 - Supported peripherals and address:; Memory address devices:
© 2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 264 3.1.4 Features of the LPC Block Bus Speed: LPC bus—33MHz Supported peripherals and address: • I/O address devices: • Parallel Ports: 378~37fh, 778~77fh, 278~27fh, 678~6...
Page 265 - PCI
© 2008 Advanced Micro Devices, Inc. Host PCI Bridge Registers (Device 20, Function 4) AMD SB600 Register Reference Manual Proprietary Page 265 3.2 Host PCI Bridge Registers (Device 20, Function 4) Note: Some PCI functions are controlled by, and associated with, certain PCI configuration registers in...
Page 276 - PCI5 Enable
© 2008 Advanced Micro Devices, Inc. Host PCI Bridge Registers (Device 20, Function 4) AMD SB600 Register Reference Manual Proprietary Page 276 Misc Control Register - 32 bits - [PCI_Reg: 64h] Field Name Bits Default Description Prefetch Enable For Upstream Read Line and Read Multiple 7 1h 0: Prefetc...
Page 277 - Register Descriptions: General Purpose Functions/Interrupt; section; Power
© 2008 Advanced Micro Devices, Inc. GPIO/GPOC AMD SB600 Register Reference Manual Proprietary Page 277 4 Register Descriptions: General Purpose Functions/Interrupt Controllers/Support Function Pins 4.1 GPIO/GPOC Note: Some GPIO functions are controlled by, and associated with, certain PCI configurat...
Page 278 - Input/Output pin only
© 2008 Advanced Micro Devices, Inc. GPIO/GPOC AMD SB600 Register Reference Manual Proprietary Page 278 Pin Name (Note 1) Multi-function Selection Output Enable (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Input if GPI (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Output if GPO (On SMBus Controller) B...
Page 281 - GPIO if internal RTC
© 2008 Advanced Micro Devices, Inc. GPIO/GPOC AMD SB600 Register Reference Manual Proprietary Page 281 Pin Name (Note 1) Multi-function Selection Output Enable (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Input if GPI (On SMBus Controller) Bus 00h/ Dev14h/ Fun00 Output if GPO (On SMBus Controller) B...
Page 283 - Configure Bit
© 2008 Advanced Micro Devices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Reference Manual Proprietary Page 283 4.2 GEVENT/GPE/GPM/ExtEvent 4.2.1 GEVENT as GPIO GEVENT[1:0] are inputs only. Their status can be read from PM I/O Reg 92h Bit[1:0]. GEVENT[7:2] can be programmed either as GPIO lines...
Page 285 - Always falling edge ACPI
© 2008 Advanced Micro Devices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Reference Manual Proprietary Page 285 Pin Name (*Note 1) Multi-Function Selection Configure Bit 00 – SCI or SMI#01 – SMI# 10 – SMI# followed by SCI11 - IRQ13 Trigger Configure 0–Falling edge 1–Rising edge Enable ACPI Even...
Page 286 - GPM as GPIO
© 2008 Advanced Micro Devices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Reference Manual Proprietary Page 286 Pin Name (*Note 1) Multi-Function Selection Configure Bit 00 – SCI or SMI#01 – SMI# 10 – SMI# followed by SCI11 - IRQ13 Trigger Configure 0–Falling edge 1–Rising edge Enable ACPI Even...
Page 288 - Temperature Alert – TALERT; Pin Name
© 2008 Advanced Micro Devices, Inc. THRMTRIP/TALERT AMD SB600 Register Reference Manual Proprietary Page 288 4.3 THRMTRIP/TALERT 4.3.1 Thermal Trip – THRMTRIP The thermal trip function is multiplexed on the GEVENT2 pin. The THRMTRIP status cannot be used to generate SCI or SMI#. Table 4-6: THRMTRIP ...
Page 289 - RTC; bit of
© 2008 Advanced Micro Devices, Inc. Real Time Clock (RTC) AMD SB600 Register Reference Manual Proprietary Page 289 4.4 Real Time Clock (RTC) Note: Some RTC functions are controlled by, and associated with, certain PCI configuration registers in the SMBus/ACPI device. For more information refer to se...
Page 290 - Figure 5 Register Bank Definition and Memory Address Mapping; Seconds Alarm
© 2008 Advanced Micro Devices, Inc. Real Time Clock (RTC) AMD SB600 Register Reference Manual Proprietary Page 290 . Figure 5 Register Bank Definition and Memory Address Mapping The analog portion consists of two major parts: one is a 256-byte CMOS RAM and the other a 44-bit ripple counter. Register...
Page 293 - Rate Selection Bits
© 2008 Advanced Micro Devices, Inc. Real Time Clock (RTC) AMD SB600 Register Reference Manual Proprietary Page 293 Register A - RW – 8 bits - [RTC_Reg: 0Ah] Field Name Bits Default Description Rate Selection(RS1) 1 0b Rate Selection(RS2) 2 0b Rate Selection(RS3) 3 0b 15-stage frequency divider or di...
Page 296 - Direct Access Registers
© 2008 Advanced Micro Devices, Inc. IOXAPIC Registers AMD SB600 Register Reference Manual Proprietary Page 296 4.5 IOXAPIC Registers Note: Some IOXAPIC functions are controlled by, and associated with, certain PCI configuration registers in the SMBus/ACPI device. For more information refer to sectio...
Page 297 - IOAPIC ID Register [Indirect Address Offset
© 2008 Advanced Micro Devices, Inc. IOXAPIC Registers AMD SB600 Register Reference Manual Proprietary Page 297 4.5.2 Indirect Access Registers Software needs to first select the register to access using the IO Register Select Register, and then read or write using the IO Window Register. IOAPIC ID R...
Page 298 - Destination ID
© 2008 Advanced Micro Devices, Inc. IOXAPIC Registers AMD SB600 Register Reference Manual Proprietary Page 298 Redirection Table Entry [0–23] [Indirect Address Offset = 11/10H–3F/3EH] RW Field Name Bits Default Description Destination ID 63:56 0 Bits [19:12] of the address field of the interrupt mes...
Page 299 - Appendix A: AC97 Audio FAQs
© 2008 Advanced Micro Devices, Inc. Appendix A: AC97 Audio FAQs AMD SB600 Register Reference Manual Proprietary Page 299 Appendix A: AC97 Audio FAQs Q: What is the descriptor table (DT) data structure in memory? A: Data Pointer (first dword); Size, Status (2nd dword); Next descriptor pointer (3rd dw...
Page 300 - Appendix B: Revision History; Date; First release of the public version.
© 2008 Advanced Micro Devices, Inc. Appendix B: Revision History AMD SB600 Register Reference Manual Proprietary Page 300 Appendix B: Revision History Date Rev. Comment September, 2008 3.03 First release of the public version.
