AMD 8151 - Manual
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Table of Contents:
- Page 2 – AGP Tunnel Data Sheet
- Page 3 – Table of Contents
- Page 4 – List of Figures
- Page 5 – List of Tables
- Page 7 – Tunnel Link Signals; The following are signals associated with the HyperTransport
- Page 8 – AGP Signals
- Page 10 – Test and Miscellaneous Signals; volt power plane for the HyperTransport; technology pins. VDD12A provides power to; Power Plane Sequencing
- Page 11 – Functional Operation; link interface. The other side; HyperTransport; AGP3.0 Graphics Tunnel Design Guide for addi-; Reset And Initialization; cold reset; Clocking
- Page 12 – Tunnel Links; The IC requires three HyperTransport
- Page 13 – Various Behaviors; Table 2: Translation from AGP requests to link requests.
- Page 14 – Registers; busses; Register Naming and Description Conventions; AGP Device
- Page 15 – AGP Device Configuration Registers
- Page 18 – AGP Miscellaneous Control Register
- Page 19 – AGP PHY Control Register; NCTL; NDATA: AGP falling edge drive strength control.; Read only. This provides the calculated value of the
- Page 20 – AGP PHY Skew Control Register; PCTL; PDATA: AGP rising edge drive strength control.; Read only. This provides the calculated value of the ris-; Bits
- Page 22 – AGP Command Register; Specifies the period between calibration cycles as follows:
- Page 25 – Link Configuration And Control Register; side A and 8 bits wide for side B.
- Page 26 – EXTCTL: extended control time during initialization.; receivers are disabled and the pins may float.
- Page 28 – Link PHY Compensation Control Registers
- Page 29 – Clock Control Register
- Page 31 – AGP Bridge Bus Numbers And Secondary Latency Register; AGP prefetchable memory window =; Secondary latency timer. These bits control no hardware.
- Page 32 – 6:16 Read only. These bits are fixed in their default state.
- Page 34 – Electrical Data; deg C
- Page 35 – DC Characteristics; See the HyperTransport; Table 9: DC characteristics for signals on the VDD33 power plane.
- Page 37 – AC Characteristics; The following table shows AC specification data for clocks.; Table 13: AC data for common clock operation of AGP signals.
- Page 38 – SymbolParameter Description; Table 14: AC data for clock-forwarded operation of AGP signals.
- Page 39 – Ball Designations
- Page 41 – Table 16: Power and ground BGA positions.
- Page 42 – Package Specification
- Page 43 – Test; The IC includes the following test modes.; High Impedance Mode; Operational; NAND Tree Mode
- Page 45 – Appendix; • Removed Preliminary.; CMPOVR
24888 Rev 3.03 - July 12, 2004
AMD-8151
TM
AGP Tunnel Data Sheet
1
Cover page
AMD-8151
TM
HyperTransport
TM
AGP3.0 Graphics Tunnel
Data Sheet
1
Overview
The
AMD-8151
TM
HyperTransport
TM
AGP3.0 Graphics Tunnel
(referred to as
the IC
in this document) is a
HyperTransport™ technology (referred to as
link
in this document) tunnel developed by AMD that provides an
AGP 3.0 compliant (8x transfer rate) bridge.
1.1
Device Features
•
HyperTransport technology tunnel with side A
and side B.
•
Side A is 16 bits (input and output); side B is
8 bits.
•
Either side may connect to the host or to a
downstream HyperTransport technology
compliant device.
•
Each side supports HyperTransport technol-
ogy-defined reduced bit widths: 8-bit, 4-bit,
and 2-bit.
•
Side A supports transfer rates of 1600, 1200,
800, and 400 mega-transfers per second.
Side B supports transfer rates of 800 and
400 mega-transfers per second.
•
Maximum bandwidth is 6.4 gigabytes per
second across side A (half upstream and half
downstream) and 1.6 gigabytes per second
across side B.
•
Independent transfer rate and bit width
selection for each side.
•
Link disconnect protocol supported.
•
AGP 8x bridge.
•
Compliance with AGP 3.0 specification sig-
naling, supporting 4x and 8x transfer rates.
•
Compliance with AGP 2.0 specification 1.5-
volt signaling, supporting 1x, 2x, and 4x
data-transfer modes.
•
Supports up to 32 outstanding requests.
•
31 x 31 millimeter, 564-ball BGA package.
•
1.5 volt AGP signaling; some 3.3 volt IO; 1.2
volt link signaling; 1.8 volt core.
Figure 1: System block diagram.
AMD-8151
TM
Device
Host
HyperTransport
TM
Link
16 bits upstream,
16 bits downstream
HyperTransport
Link
8 bits upstream,
8 bits downstream
Downstream
Device
tunnel
Side A
Side B
AGP
Bridge
AGP Graphics
Controller
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Summary
24888 Rev 3.03 - July 12, 2004 AMD-8151 TM AGP Tunnel Data Sheet 2 Trademarks AMD, the AMD Arrow logo, and combinations thereof, and AMD-8151 are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. Other product names used in...
3 24888 Rev 3.03 - July 12, 2004 AMD-8151 TM AGP Tunnel Data Sheet Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Device Features . . . . . . . . . . . . . . . . . . . . ...
24888 Rev 3.03 - July 12, 2004 AMD-8151 TM AGP Tunnel Data Sheet 4 List of Figures Figure 1: System block diagram. .................................................................................................................. 1 Figure 2: Configuration space. ........................................
