AMD K Manual - Free PDF Download

Page 1 - Processor Revision Guide Identification

Cover information for the AMD Athlon™ Processor Model 4 Revision Guide, including product identification and support resources.

Page 2 - Legal and Trademark Information

Preliminary legal information regarding warranties, usage restrictions, disclaimers about product accuracy, and a list of AMD trademarks.

Page 3 - Processor Revision History

Details on the revision history of the AMD Athlon™ Processor Model 4, listing updates and errata from April 2001 to October 2003.

Page 4 - Revision Guide Structure and Policy

Introduction to the guide explaining its purpose: communicating updated product information and errata to designers, covering Product Errata, Revision Determination, and Technical Support sections.

Page 5 - Product Errata Cross-Reference

Table detailing specific product errata for the processor, cross-referencing errata descriptions with various processor revision levels (A4, A5, A6, A7, A9).

Page 6 - MCA Bus Unit Control Register Error

Details regarding the MCA Bus Unit Control Register (MSR 408h) returning incorrect data across affected processor models and a suggested workaround.

Page 7 - Pin Resistance and Impedance

Specification of resistance values for ZN and ZP pins, non-conformance regarding driver impedance, potential system effects, and a suggested resistor setting workaround for models A4 and A5.

Page 8 - PLL Frequency Overshoot and Workaround

Hardware issue where PLL frequency may overshoot upon disconnect, causing auto-compensation failure and system hangs, along with a BIOS workaround using CLKCTRL MSR.

Page 9 - Instruction Execution Deadlock Issue

Details on Instruction Execution Deadlock occurring under rare conditions in certain processor units, affecting models A4, A5, A6, and A7, with no suggested workaround.

Page 10 - Low-Power State Hangs

Issue where processors with half-frequency multipliers hang upon waking from C2 or C3 low-power states, along with a workaround involving BIOS FADT settings.

Page 11 - A9 Microcode Patch Instability

Known issue where the A9 processor model does not support reliable microcode patch mechanisms due to disabled patch RAM BIST, recommending against loading patches.

Page 12 - INVLPG Instruction TLB Bug

Bug related to the INVLPG instruction causing improper TLB flushing under specific page mappings, potentially leading to access of stale memory, with a suggested workaround.

Page 13 - Self-Modifying Code and TLB Behavior

Non-conformance scenario where self-modifying code coinciding with Level 2 instruction TLB translations may cause stale code execution, with no fix planned.

Page 14 - Speculative Store Instruction Execution

Issue where a speculative SMC store followed by an actual SMC store may result in the execution of stale instructions due to cache and instruction buffer interactions.

Page 15 - RDPMC Instruction Fault Handling

Bug where the RDPMC instruction can cause the processor to enter the general protection fault handler when executed with illegal ECX values, suggesting a workaround by restricting counter values.

Page 16 - Task Gates and Breakpoint Faults

Non-conformance issue where using task gates with breakpoints enabled may result in unexpected general protection faults, with a suggested workaround to disable breakpoints.

Page 17 - I/O Instruction Single-Stepping Behavior

Issue where single-stepping across an I/O instruction that triggers an SMI may skip the debug trap handler instead of entering it, with a suggested workaround involving modifying the SMM handler.

Page 18 - Prefetch Instructions and Page Faults

Hardware erratum where software prefetch instructions may report a page fault under certain conditions, including workarounds for the kernel and general cases.

Page 19 - Prefetch Instruction Cache Alignment Errata

Errata related to prefetch instructions and cache-line alignment that are infrequent, do not significantly impact performance, and include software workarounds to minimize occurrence.

Page 20 - Processor Revision Identification via CPUID

Method for identifying different processor revisions using the CPUID instruction, presenting a table listing CPUID values for revisions A4 through A9.

Page 21 - Technical Documentation and Support Resources

Listing of technical documentation, data sheets, and a code optimization guide for the AMD Athlon™ Processor Model 4, including order numbers and update instructions.