Sun Microsystems SME5224AUPA-400 - Manual

Sun Microsystems SME5224AUPA-400

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Table of Contents:

  • Page 2 – UltraSPARC; Sun Microsystems, Inc; CPU D; ESCRIPTION; sions of the SPARCTM microprocessor family; CPU Features; Architecture
  • Page 3 – Advanced Version
  • Page 4 – ODULE; • UltraSPARCTM-II CPU at 400 MHz; Block Diagram; Figure 1. Module Block Diagram
  • Page 5 – YSTEM; for the; Figure 2. Uniprocessor System Configuration
  • Page 6 – supplies the
  • Page 7 – IGNAL; System Interface; Clock Interface
  • Page 8 – Initialization Interface
  • Page 9 – UPA; AND; CPU C; LOCKS; Module Clocks; UltraSPARC-II CPU Module
  • Page 10 – Figure 3. Clock Signal Distribution
  • Page 11 – LECTRICAL; Absolute Maximum Ratings; Recommended Operating Conditions
  • Page 12 – Module Power Consumption; and V; DC Characteristics
  • Page 13 – UPA Data Bus SPICE Model
  • Page 14 – UPA AC T; IMING; UPA_CLK Module Clocks
  • Page 15 – Timing Measurement Waveforms; Setup and Hold Time Specifications; Figure 5. Timing Measurement Waveforms
  • Page 16 – ECHANICAL; Figure 6. CPU Module Components
  • Page 17 – Figure 8. CPU Module Side View; Maximum
  • Page 18 – HERMAL; Two Step Approach to Thermal Design
  • Page 19 – Thermal Definitions and Specifications; Term
  • Page 20 – Temperature Estimating and Measuring Methods; Airflow Cooling Measurement Method; Air Velocity
  • Page 22 – JTAG T; ESTABILITY; AC Characteristics - JTAG Timing
  • Page 23 – Figure 10. Voltage Waveforms - Setup and Hold Times; Figure 11. Voltage Waveforms - Propagation Delay Times
  • Page 24 – UPA C; ONNECTOR
  • Page 26 – ANDLING; CPU M; ODULES; Parameter
  • Page 27 – RDERING; Part Number; OCUMENT; Date
  • Page 29 – DATASHEET; Module Features; Ease of System Design
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DATASHEET

1

SME5224AUPA-400

UltraSPARC

™

-II CPU Module

400 MHz CPU, 4.0 MB E-Cache

M

ODULE

D

ESCRIPTION

The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400) delivers high performance
computing in a compact design. Based on the UltraSPARC™-II CPU, this module is designed using a small
form factor board with an integrated external cache. It connects to the high bandwidth Ultra™ Port Architec-
ture UPA bus via a high speed sturdy connector. The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, can
plug into any UPA connector, saving system design costs and reducing the production time for new systems.

Heatsinks are attached to components on the module board. The module board is encased in a plastic shroud.
The purpose of this shroud is to protect the components and channel airflow. Module design is geared
towards ease of upgrade and field support.

Module Features

Module Benefits

Ease of System Design

•

Small form factor board with integrated external cache
and UPA interface

•

JTAG boundary scan and performance instrumentation

•

PCB provides a multi-power plane bypass, reducing
systemboard design requirements

Performance

•

High performance UltraSPARC™ CPU at 400MHz

•

Four megabytes of external cache using high speed
register-latch SRAMs

•

Dedicated high bandwidth bus to processor

Glueless MP Support

•

•

Implements the high performance AUPA interface

•

Supports up to 16 Mbyte of external cache in a
four-way MP system

Simplify System Qualifications by
Complying with Industry and Government
Standards

•

Backwards compatibility with systems implementing a
UPA interface

•

Plastic shroud protects components and channels
airflow

•

Multi-layer PCB controls EMI radiation

•

Edge connectors and ejectors

•

Small form factor board encased in a heat resistant
shroud

•

On-board voltage regulator accepts 2.6 volts for the
Vdd_core; compatible with existing systems

July 1999

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Summary

Page 2 - UltraSPARC; Sun Microsystems, Inc; CPU D; ESCRIPTION; sions of the SPARCTM microprocessor family; CPU Features; Architecture

2 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc CPU D ESCRIPTION UltraSPARC-II CPU The UltraSPARC™-II CPU is the second generation in the UltraSPARC™ s-series microprocessor family.A complete implementation of the SPARC  V9 architecture, it ...

Page 3 - Advanced Version

3 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module SME5224AUPA-400 Advanced Version July 1999 Sun Microsystems, Inc D ATA B UFFER D ESCRIPTION UltraSPARC-II Data Buffer (UDB-II) The UltraSPARC™-II module has two UltraSPARC-II data buffers (UDB-II) - each a 256 pin BGA device - fora UPA Interc...

Page 4 - ODULE; • UltraSPARCTM-II CPU at 400 MHz; Block Diagram; Figure 1. Module Block Diagram

4 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UltraSPARC ™ -II CPU Module July 1999 Sun Microsystems, Inc M ODULE C OMPONENT O VERVIEW The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400), (see Figure 1), consists of thefollowing components: • UltraSPARC™-II CPU at 400 MHz • UltraSPA...

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