Summit Appliance S93WD463 - Manual
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Table of Contents:
- Page 2 – PIN FUNCTIONS; Pin Name; PIN CONFIGURATION; DI
- Page 3 – or t; Figure 1. Sychronous Data Timing
- Page 4 – ). The falling edge of CS will start the self clocking; ). The falling edge of CS will start the self
- Page 7 – ABSOLUTE MAXIMUM RATINGS*; Temperature
- Page 9 – VCC
- Page 10 – Inches
- Page 11 – PURST
- Page 13 – ORDERING INFORMATION; TRIP; Base Part Number
© SUMMIT MICROELECTRONICS, Inc. 2001 • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com
1
S93WD462/S93WD463
Characteristics subject to change without notice
Precision Supply-Voltage Monitor and Reset Controller
With a Watchdog Timer and 1k-bit Microwire Memory
S U M M I T
M I C R O E L E C T R O N I C S , I n c .
2029 2.2 1/23/01
FEATURES
•
Precision Monitor & RESET Controller
— RESET and RESET Outputs
— Guaranteed RESET Assertion to V
CC
= 1V
— 150ms Reset Pulse Width
— Internal 1.26V Reference with ±1% Accuracy
— ZERO External Components Required
•
Watchdog Timer
— Nominal 1.6 Second Time-out Period
— Reset by Any Transition of CS
•
Memory
— 1K-bit Microwire Memory
— S93WD462
– Internally Ties ORG Low
– 100% Compatible With all 8-bit
Implementations
– Sixteen Byte Page Write Capability
— S93WD463
– Internally Ties ORG High
– 100% Compatible With all 16-bit
Implementations
– Eight Word Page Write Capability
OVERVIEW
The S93WD462 and S93WD463 are precision power
supervisory circuits providing both active high and
active low reset output. Both devices also incorporate a
watchdog timer with a nominal time-out value of 1.6
seconds.
Both devices have 1k-bits of E
2
PROM memory that is
accessible via the industry standard microwire bus. The
S93WD462 is configured with an internal ORG pin tied
low providing a 8-bit byte organization and the
S93WD463 is configured with an internal ORG pin tied
high providing a 16-bit word organization. Both the
S93WD462 and S93WD463 have page write capabil-
ity. The devices are designed for a minimum 100,000
program/erase cycles and have data retention in ex-
cess of 100 years.
BLOCK DIAGRAM
+
–
GND
VCC
8
5
RESET#
6
VTRIP
RESET
PULSE
GENERATOR
5kHz
OSCILLATOR
RESET
CONTROL
MODE
DECODE
ADDRESS
DECODER
WRITE
CONTROL
DATA I/O
E2PROM
MEMORY
ARRAY
RESET
7
1.26V
SK
2
DI
3
WATCHDOG
TIMER
CS
1
2029 T BD 2.0
DO
4
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Summary
2 S93WD462/S93WD463 2029 2.2 1/23/01 SUMMIT MICROELECTRONICS, Inc. PIN FUNCTIONS Pin Name Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output V CC +2.7 to 6.0V Power Supply GND Ground RESET/RESET# RESET I/O PIN CONFIGURATION DEVICE OPERATION APPLICATIONSThe S93WD462/WD4...
3 S93WD462/S93WD463 2029 2.2 1/23/01 SUMMIT MICROELECTRONICS, Inc. Instructions, addresses, and write data are clocked intothe DI pin on the rising edge of the clock (SK). The DOpin is normally in a high impedance state except whenreading data from the device, or when checking theready/busy status a...
4 S93WD462/S93WD463 2029 2.2 1/23/01 SUMMIT MICROELECTRONICS, Inc. EraseUpon receiving an ERASE command and address, theCS (Chip Select) pin must be deselected for a minimumof 250ns (t CSMIN ). The falling edge of CS will start the auto erase cycle of the selected memory location. Theready/busy stat...
