NEC uPD78P078Y - Manual
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Table of Contents:
- Page 3 – NOTES FOR CMOS DEVICES; to be taken for PW boards with semiconductor devices on it.; or GND with a resistor, if it is considered to have a possibility of
- Page 4 – The customer must judge the need for license:
- Page 5 – Regional Information; • Device availability
- Page 6 – Major Revisions in This Edition; The mark
- Page 7 – INTRODUCTION
- Page 10 – • Development Tool Documents (User’s Manuals); version when starting design.
- Page 13 – PROM programming mode pins (
- Page 14 – CHAPTER 4 PIN FUNCTION (
- Page 16 – Outline of Timers Incorporated into
- Page 20 – APPENDIX A DIFFERENCES BETWEEN
- Page 21 – Data Memory Addressing (
- Page 22 – Control Register Settings for Two Pulse Width Measurements with
- Page 23 – Timing of One-Shot Pulse Output Operation Using External Trigger
- Page 24 – Handling of AV
- Page 25 – Serial Bus Configuration Example Using I
- Page 26 – Example of Serial Bus Configuration Using I
- Page 30 – Differences between
- Page 31 – Signals in I
- Page 32 – Relationship between ASCK Pin Input Frequency and Baud Rate
- Page 33 – CHAPTER 1 OUTLINE (; Program Memory
- Page 34 – Application Fields; Note; Under development; Caution Two types of packages are available for the; xxx indicates ROM code suffix.
- Page 35 – mass-produced and require high reliability.
- Page 37 – pin to V; Remark; Pin connection in parentheses is for the; AV; AV; RESET
- Page 39 – Pin Identifications
- Page 40 – : Connect independently to V
- Page 41 – : Programming Power Supply
- Page 42 – Planned
- Page 44 – Pin connection in parentheses is for the
- Page 45 – Outline of Function
- Page 47 – Table 1-1. Mask Options of Mask ROM Versions; Differences with
- Page 49 – CHAPTER 2 OUTLINE (; Notes
- Page 50 – Application Fields
- Page 59 – Major differences among Y subseries are tabulated below.
- Page 61 – Outline of Function
- Page 63 – Table 2-1. Mask Options of Mask ROM Versions; Differences with
- Page 66 – CHAPTER 3 PIN FUNCTION (
- Page 70 – Description of Pin Functions
- Page 71 – Caution
- Page 72 – output and buzzer output.
- Page 73 – Port 5 can drive LEDs directly.
- Page 74 – to the function the user requires.
- Page 76 – that are not used as analog outputs must be set as follows:
- Page 77 – Connect IC pins to V
- Page 84 – CHAPTER 4 PIN FUNCTION (
- Page 88 – Description of Pin Functions
- Page 89 – The following operating modes can be specified bit-wise.
- Page 93 – P90 to P93 can drive LEDs directly.
- Page 101 – CHAPTER 5 CPU ARCHITECTURE; The
- Page 102 – internal memory size switching register.
- Page 103 – by the internal memory size switching register.
- Page 104 – The internal program memory space
- Page 106 – Caution Do not access addresses where the SFR is not assigned.
- Page 107 – For details of addressing, refer to 5.4 Operand Address Addressing.
- Page 110 – Processor Registers; Figure 5-7. Program Counter Configuration; RESET input sets the PSW to 02H.; Figure 5-8. Program Status Word Configuration
- Page 111 – These are 2-bit flags to select one of the four register banks.
- Page 112 – area can be set as the stack area.; instruction execution.
- Page 113 – processing and a register for interruption for each bank.; Figure 5-12. General Register Configuration; FEFFH
- Page 114 – • 16-bit manipulation
- Page 117 – unless external device expansion function is used with the
- Page 118 – PC; Instruction Address Addressing; instruction is executed.
- Page 119 – CALLF !addr11 instruction branches to the area from 0800H to 0FFFH.
- Page 121 – rp
- Page 122 – Operand Address Addressing; during instruction execution.
- Page 123 – Identifier; MOV A, C when selecting C register as r; Register specify code
- Page 124 – Operation code
- Page 131 – CHAPTER 6 PORT FUNCTIONS
- Page 136 – Port Configuration; A port consists of the following hardware:; Item; Port; for subsystem clock oscillation.; the output mode is used, set the interrupt mask flag to 1.
- Page 137 – Figure 6-2. Block Diagram of P00 and P07; Internal bus
- Page 138 – WR; RD; Selector
- Page 139 – Format and Figure 19-3. Serial Operating Mode Register 1 Format.
- Page 140 – Figure 6-6. Block Diagram of P22 and P27
- Page 142 – Figure 6-8. Block Diagram of P22 and P27
- Page 144 – Figure 6-11. Block Diagram of Falling Edge Detection Circuit
- Page 146 – on the port pin and the device version.; Mask ROM version; Pins P60 to P63 can drive LEDs directly.; each of these pins depends on the following conditions:
- Page 151 – Pins P90 to P93 can drive LEDs directly.; of these pins depends on the following conditions:
- Page 156 – pins that are not used as analog outputs must be set as follows:
- Page 157 – Port Function Control Registers; The following four types of registers control the ports.; be set to 1 beforehand.
- Page 158 – set the function with the memory extension mode register (MM).; Remarks x; PMxx : Port mode register
- Page 160 – RESET input sets this register to 00H.; Cautions 1. P00 and P07 pins do not incorporate a pull-up resistor.
- Page 161 – This register is used to set input/output of port 4.; Figure 6-26. Memory Expansion Mode Register Format; device is switched to the multiplexed bus mode.
- Page 162 – KRM is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 6-27. Key Return Mode Register Format
- Page 163 – Port Function Operations; output latch contents are output from the pins.; than the manipulated bit.
- Page 164 – Selection of Mask Option; The following mask option is provided in mask ROM version. The; Table 6-7. Comparison between Mask ROM Version and the; Pin Name
- Page 165 – types of system clock oscillators are available.
- Page 166 – CHAPTER 7 CLOCK GENERATOR; Clock Generator Configuration; The clock generator consists of the following hardware.; Table 7-1. Clock Generator Configuration
- Page 167 – Clock Generator Control Register; The clock generator is controlled by the following two registers:; Figure 7-2. Subsystem Clock Feedback Resistor
- Page 168 – Figure 7-3. Processor Clock Control Register Format; system clock oscillation. A STOP instruction should not be used.; Caution Bit 3 must be set to 0.; or f; : Subsystem clock oscillation frequency
- Page 169 – The fastest instruction of the; ) and the minimum instruction execution time is shown in Table 7-2.; : Main system clock oscillation frequency; : Subsystem clock oscillation frequency
- Page 170 – OSMS is set with 8-bit memory manipulation instruction.; fx
- Page 171 – System Clock Oscillator; connected to the X1 and X2 pins.; Figure 7-6. External Circuit of Main System Clock Oscillator; when a STOP instruction is executed and MCC is set
- Page 172 – and an antiphase clock signal to the XT2 pin.; resistors in series on the side of XT2.
- Page 173 – resistors in series on the XT2 side.
- Page 174 – connect the XT1 and XT2 pins as follows.
- Page 175 – Clock Generator Operations
- Page 176 – (b) Operation when MCC is set in case of main system clock operation
- Page 177 – the following operations are carried out.
- Page 178 – Changing System Clock and CPU Clock Settings; Table 7-3. Maximum Time Required for CPU Clock Switchover
- Page 179 – System clock and CPU clock switching procedure
- Page 181 – Outline of Timers Incorporated into; Subseries and the related circuits are outlined below.
- Page 183 – Figures in parentheses apply to operation with f
- Page 184 – Figures in parentheses operation with f
- Page 185 – The 16-bit timer/event counter consists of the following hardware.
- Page 186 – Notes 1. Edge detection circuit
- Page 188 – count operation cannot be executed.; CR01 is set with a 16-bit memory manipulation instruction.; by the detection of a valid edge.
- Page 189 – TM0 is a 16-bit register which counts the count pulses.
- Page 192 – Remarks; Figures in parentheses apply to operation with f
- Page 193 – CRC0 is set with a 1-bit or 8-bit memory manipulation instruction.; Cautions 1. Timer operation must be stopped before setting CRC0.
- Page 194 – If LVS0 and LVR0 are read after data is set, they will be 0.
- Page 196 – Figure 8-8. External Interrupt Mode Register 0 Format
- Page 198 – the description of the respective control registers for details.; Clear & start on match TM0 and CR00
- Page 200 – Figures in parentheses apply to operation with f; and the
- Page 201 – PWM mode
- Page 202 – The analog output voltage (V; : External switching circuit reference voltage; Figure 8-14. Example of D/A Converter Configuration with PWM Output; synthesizer type TV tuner.; Figure 8-15. TV Tuner Application Circuit Example
- Page 204 – Pulse width measurement operations; thus eliminating noise with a short pulse width.; Free-Running Counter and One Capture Register
- Page 205 – and One Capture Register (with Both Edges Specified); Count Clock
- Page 206 – detected twice, thus eliminating noise with a short pulse width.; CR00 set as capture register
- Page 207 – Figure 8-21. Timing of Pulse Width Measurement Operation with
- Page 208 – Free-Running Counter and Two Capture Registers
- Page 209 – Counter and Two Capture Registers (with Rising Edge Specified)
- Page 210 – (4) Pulse width measurement by means of restart; pulse width noise to be eliminated.
- Page 211 – Clear & start with match of TM0 and CR00
- Page 212 – Figure 8-27. External Event Counter Configuration Diagram; Clear
- Page 213 – frequency to be output.; Figure 8-29. Control Register Settings in Square-Wave Output Mode; One-shot pulse output disabled
- Page 217 – the TO0/P30 pin with a TI00/P00 valid edge as an external trigger.; FFFFH
- Page 220 – (4) Capture register data retention timings; detection of the valid edge.; Figure 8-37. Capture Register Data Retention Timing
- Page 221 – Figure 8-38. Operation Timing of OVF0 Flag
- Page 223 – CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2; • Interval timer
- Page 224 – Interrupt requests are generated at the preset time intervals.
- Page 226 – Interrupt requests can be generated at the preset time intervals.
- Page 227 – Figures in parentheses apply to operation with at f
- Page 229 – The section in the broken line is an output control circuit.; : Serial clock frequency
- Page 230 – FFFFH values can be set.; stopping timer operation.; These are 8-bit registers to count count pulses.
- Page 231 – This register sets count clocks of 8-bit timer registers 1 and 2.
- Page 232 – Figure 9-4. Timer Clock Select Register 1 Format; Figures in parentheses apply to operation with f
- Page 233 – TMC1 is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 234 – bit timer registers 1 and 2.; Cautions 1. Stop the timer operation before setting TOC1.
- Page 235 – PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 236 – Figure 9-8. Interval Timer Operation Timing
- Page 239 – is input. Either the rising or falling edge can be selected.; TI1 Pin Input
- Page 240 – a square wave with any selected frequency to be output.
- Page 241 – Figure 9-10. Timing of Square Wave Output Operation
- Page 242 – Figure 9-11. Interval Timer Operation Timing
- Page 243 – Figures in parentheses apply to operation with at f
- Page 245 – selected frequency to be output.
- Page 246 – with the count pulse.; Figure 9-14. External Event Counter Operation Timing
- Page 249 – CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6
- Page 253 – memory manipulation instruction. The 00H to FFH values can be set.
- Page 254 – This register sets count clocks of 8-bit timer register 5.; Figure 10-3. Timer Clock Select Register 5 Format; Figures in parentheses apply to operation with f
- Page 255 – This register sets count clocks of 8-bit timer register 6.; Figure 10-4. Timer Clock Select Register 6 Format
- Page 256 – TMC5 is set with a 1-bit or 8-bit memory manipulation instruction.; Cautions 1. Timer operation must be stopped before setting TMC5.
- Page 257 – TMC6 is set with a 1-bit or 8-bit memory manipulation instruction.; Cautions 1. Timer operation must be stopped before setting TMC6.
- Page 258 – PM10 is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 10-7. Port Mode Register 10 Format
- Page 259 – Figure 10-9. Interval Timer Operation Timings
- Page 261 – and TCL6) is input. Either rising or falling edge can be selected.
- Page 262 – This enables a square wave of any selected frequency to be output.
- Page 263 – Minimum Pulse Time
- Page 267 – Figure 10-20. External Event Counter Operation Timings
- Page 268 – to restart the timer after changing CR50 and CR60.
- Page 269 – Table 11-1. Interval Timer Interval Time
- Page 270 – CHAPTER 11 WATCH TIMER; Watch Timer Configuration; The watch timer consists of the following hardware.
- Page 271 – Watch Timer Control Registers; • Watch timer mode control register (TMC2)
- Page 272 – Figure 11-2. Timer Clock Select Register 2 Format
- Page 273 – Figure 11-3. Watch Timer Mode Control Register Format
- Page 274 – Watch Timer Operations; Watch timer operation
- Page 275 – Table 12-1. Watchdog Timer Runaway Times
- Page 276 – CHAPTER 12 WATCHDOG TIMER
- Page 277 – Watchdog Timer Configuration; The watchdog timer consists of the following hardware.; Table 12-3. Watchdog Timer Configuration; Figure 12-1. Watchdog Timer Block Diagram; Control register
- Page 278 – Watchdog Timer Control Registers; This register sets the watchdog timer count clock.
- Page 279 – Figure 12-2. Timer Clock Select Register 2 Format
- Page 280 – WDTM is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 12-3. Watchdog Timer Mode Register Format; Thus, once counting starts, it can only be stopped by RESET input.
- Page 281 – Watchdog Timer Operations; Table 12-4. Watchdog Timer Runaway Detection Time
- Page 282 – requests, the INTWDT default has the highest priority.; timer mode is not set unless RESET input is applied.; Interval Time
- Page 283 – Follow the procedure below to output clock pulses.; CLOE
- Page 284 – CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT; Clock Output Control Circuit Configuration; Table 13-1. Clock Output Control Circuit Configuration; Figure 13-2. Clock Output Control Circuit Block Diagram
- Page 285 – Clock Output Function Control Registers; This register sets PCL output clock.
- Page 286 – Figure 13-3. Timer Clock Select Register 0 Format
- Page 287 – Figure 13-4. Port Mode Register 3 Format
- Page 289 – Follow the procedure below to output the buzzer frequency.; Buzzer Output Control Circuit Configuration; Table 14-1. Buzzer Output Control Circuit Configuration; Figure 14-1. Buzzer Output Control Circuit Block Diagram; Timer Clock Select Register 2
- Page 290 – CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT; Buzzer Output Function Control Registers; This register sets the buzzer output frequency.; watchdog timer count clock.
- Page 291 – Figure 14-2. Timer Clock Select Register 2 Format
- Page 292 – Figure 14-3. Port Mode Register 3 Format
- Page 293 – CHAPTER 15 A/D CONVERTER
- Page 294 – Tap Selector
- Page 296 – pin when not using; pin when not
- Page 297 – Setting prohibited because A/D conversion time is less than 19.1
- Page 298 – ADIS is set with an 8-bit memory manipulation instruction.; Cautions 1. Set the analog input channel in the following order.
- Page 299 – This register sets the valid edge for INTP3 to INTP6.; Figure 15-4. External Interrupt Mode Register 1 Format
- Page 300 – • Analog input voltage
- Page 301 – After RESET input, the value of ADCR is undefined.; SAR
- Page 302 – Input voltage and conversion results
- Page 303 – The following two ways are available to start A/D conversion.
- Page 304 – tinues repeatedly until new data is written to ADM.
- Page 305 – pin at this time, this current must
- Page 306 – and ANI0 to ANI7. Since; Figure 15-10. Analog Input Pin Disposition; adjacent to the pin undergoing A/D conversion.
- Page 307 – pin input impedance; pin; Pin
- Page 309 – CHAPTER 16 D/A CONVERTER; The conversion method used is the R-2R resistor ladder method.
- Page 310 – The D/A converter consists of the following hardware.
- Page 311 – RESET input sets these registers to 00H.; trigger and before the next output trigger.; DACSn
- Page 312 – The DAM is set with a 1-bit or 8-bit memory manipulation instruction.; a pull-up resistor should be disconnected.
- Page 313 – synchronously with the output triggers.; Caution Set DACE0 and DACE1 after setting data in DACS0 and DACS1.
- Page 314 – Figure 16-3. Use Example of Buffer Amplifier; When only either one of the D/A converter channels is used with AV; , the other pins that are not; low level from the pin.; ANOn
- Page 315 – CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (
- Page 316 – Serial Interface Channel 0 Functions
- Page 318 – Serial Interface Channel 0 Configuration; Table 17-2. Serial Interface Channel 0 Configuration
- Page 319 – SIO0 is set with an 8-bit memory manipulation instruction.
- Page 320 – SBI mode, this latch is set upon termination of the 8th serial clock.; When WUP
- Page 321 – Serial Interface Channel 0 Control Registers
- Page 322 – Figure 17-3. Timer Clock Select Register 3 Format
- Page 323 – function and displays the address comparator match signal.
- Page 324 – Figure 17-4. Serial Operating Mode Register 0 Format; PMxx : Port mode register
- Page 325 – SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 327 – SINT is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 17-6. Interrupt Timing Specify Register Format; SVA
- Page 328 – Serial Interface Channel 0 Operations; • Operation stop mode
- Page 329 – CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 331 – input to the SI0 pin is latched in SIO0 at the rising edge of SCK0.
- Page 332 – Figure 17-9. Circuit of Switching in Transfer Bit Order; two conditions are satisfied.
- Page 333 – the board can be decreased.; Figure 17-10. Example of Serial Bus Configuration with SBI
- Page 334 – controlled by software, the software must be heavily loaded.; (b) Chip select function by address transmission; The busy signal to report the slave busy state is controlled.
- Page 335 – The broken lines indicate the READY state.
- Page 336 – This signal is output by the master device.
- Page 337 – in order to select a particular slave device.; Figure 17-15. Slave Selection with Address; Master; Slave 2; Slave 3
- Page 338 – selected by address transmission.; Command
- Page 339 – [When output in synchronization with 11th clock SCK0]; The brokens lines indicate the READY state.
- Page 343 – Caution Set bits 0 to 3 to 0.
- Page 345 – Caution Do not set ACKT before termination of transfer.; ACKT
- Page 346 – (b) When set after completion of transfer
- Page 347 – (a) When ACK signal is output at 9th clock of SCK0; ACKD; BUSY
- Page 349 – Synchronous clock to output; In BUSY state, transfer starts after the READY state is set.
- Page 350 – it is not necessary to write FFH to SIO0.
- Page 351 – device matches the value set to SVA.; instead of using the address match detection method.; two or more devices by outputting an “address” to the serial bus.
- Page 354 – Figure 17-29. Data Transmission from Master Device to Slave Device
- Page 355 – Figure 17-30. Data Transmission from Slave Device to Master Device
- Page 356 – write FFH to SIO0 in advance.; serial transfer of the first byte.; (10) How to detect the busy state in a slave
- Page 357 – serial transfer of the 1st byte after RESET input.
- Page 360 – CSIIF0 : Interrupt request flag corresponding to INTCSI0
- Page 361 – is carried out bit-wise in synchronization with the serial clock.; Transfer Start at the Falling Edge of SCK0
- Page 362 – state for data reception, write FFH to SIO0 in advance.
- Page 363 – Latch; to normal serial clock output.
- Page 365 – CHAPTER 18 SERIAL INTERFACE CHANNEL 0 (
- Page 366 – Serial Interface Channel 0 Functions; Serial interface channel 0 employs the following four modes.; C bus) while the operation; the data transfer processing time.
- Page 367 – This mode is in compliance with the I; Figure 18-1. Serial Bus Configuration Example Using I
- Page 368 – Serial Interface Channel 0 Configuration; Table 18-2. Serial Interface Channel 0 Configuration
- Page 369 – Figure 18-2. Serial Interface Channel 0 Block Diagram
- Page 370 – Caution In the I
- Page 372 – Serial Interface Channel 0 Control Registers; • Serial operating mode register 0 (CSIM0)
- Page 373 – This register sets the serial clock of serial interface channel 0.; Figure 18-3. Timer Clock Select Register 3 Format
- Page 374 – changing the operation mode.
- Page 375 – Figure 18-4. Serial Operating Mode Register 0 Format; C bus mode, the clock frequency becomes 1/16 of that output from TO2.
- Page 377 – Notes 1. Setting should be performed before transfer.
- Page 378 – RESET input sets SINT to 00H.; When not using the I
- Page 379 – Notes 1. When using wake-up function in the I
- Page 380 – Serial Interface Channel 0 Operations
- Page 384 – Figure 18-9. Circuit of Switching in Transfer Bit Order
- Page 386 – PMxxx : Port mode register
- Page 387 – Caution Set bits 0 to 3 to 0 when the 2-wire serial I/O mode is selected.
- Page 389 – Figure 18-12 shows RELT and CMDT operations.
- Page 390 – C bus mode operation; The I; Figure 18-13. Example of Serial Bus Configuration Using I
- Page 391 – C bus mode functions
- Page 392 – C bus mode, for details of the start condition output.; If it is 1, it is the slave device which will send data to the master.; Figure 18-17. Transfer Direction Specification
- Page 393 – as a stop condition signal.
- Page 394 – state due to preparing for transmitting or receiving data.
- Page 396 – SBIC is set by a 1-bit or 8-bit memory manipulation instruction.; This setting must be performed prior to transfer start.
- Page 397 – SINT is set by the 1-bit or 8-bit memory manipulation instruction.; Remark SVA; : Slave address register
- Page 398 – A list of signals in the I; C Bus Mode
- Page 407 – conditions have been satisfied:; does not initiate transfer operation.
- Page 408 – C bus mode
- Page 409 – to 1 after execution of an SIO0 write instruction.
- Page 410 – as shown in Figure 18-26 to receive data correctly.
- Page 412 – • Example of program releasing serial transfer status
- Page 415 – Serial interface channel 1 employs the following three modes.
- Page 416 – CHAPTER 19 SERIAL INTERFACE CHANNEL 1; Serial Interface Channel 1 Configuration; Table 19-1. Serial Interface Channel 1 Configuration
- Page 417 – SIO1 is set with an 8-bit memory manipulation instruction.
- Page 418 – Serial Interface Channel 1 Control Registers
- Page 419 – CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 19-3. Serial Operation Mode Register 1 Format
- Page 420 – ADTC is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 421 – Notes 1. The interval is dependent only on CPU processing.
- Page 422 – , the minimum interval time
- Page 425 – Serial Interface Channel 1 Operations; Notes 1. Can be used freely as port function.
- Page 427 – to the SI1 pin is latched into SIO1 at the rising edge of SCK1.; Caution SO1 pin becomes low level by SIO1 write.
- Page 428 – Figure 19-7. Circuit of Switching in Transfer Bit Order
- Page 431 – ADTI is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 435 – subtracting 1 from the number of transmit data bytes.; the written value has no meaning.
- Page 436 – CSIIF0 : Interrupt request flag; Figure 19-8. Basic Transmission/Reception Mode Operation Timings
- Page 437 – ADTP : Automatic data transmit/receive address pointer
- Page 438 – is transferred from SIO1 to the buffer RAM, and ADTP is decremented.
- Page 440 – BUSY pins can be used as normal input/ports.; Figure 19-11. Basic Transmission Mode Operation Timings; CSIIF1 : Interrupt request flag
- Page 441 – Figure 19-12. Basic Transmission Mode Flowchart
- Page 444 – are transmitted again.; Figure 19-14. Repeat Transmission Mode Operation Timing
- Page 445 – Figure 19-15. Repeat Transmission Mode Flowchart
- Page 446 – The first pointer value is set to ADTP again.
- Page 447 – (b) Upon completion of transmission of 6 bytes
- Page 448 – is suspended upon completion of 8-bit data transfer.; Suspend
- Page 449 – device and slave device.; simultaneously, busy control becomes invalid.; Master Device
- Page 450 – Caution When TRF is cleared, the SO1 pin becomes low level.
- Page 451 – or receiving can wait while the busy signal is being input.
- Page 453 – (c) Bit slippage detection function through the busy signal; during sending, bit slippage can be detected.
- Page 454 – interval may be longer than the value indicated by paragraph (b).
- Page 455 – Internal Clock
- Page 456 – or longer
- Page 457 – Serial interface channel 2 has the following three modes.
- Page 458 – CHAPTER 20 SERIAL INTERFACE CHANNEL 2; Serial Interface Channel 2 Configuration; Table 20-1. Serial Interface Channel 2 Configuration
- Page 459 – Figure 20-2. Baud Rate Generator Block Diagram
- Page 460 – write is performed, the value is written to TXS.
- Page 461 – Serial Interface Channel 2 Control Registers; Figure 20-3. Serial Operating Mode Register 2 Format
- Page 462 – ASIM is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 20-4. Asynchronous Serial Interface Mode Register Format
- Page 463 – Table 20-2. Serial Interface Channel 2 Operating Mode Settings
- Page 464 – serial interface mode.
- Page 465 – BRGC is set with an 8-bit memory manipulation instruction.
- Page 466 – -Bit Counter Source Clock Selection; must not be written to during a communication operation.
- Page 467 – scaled from the clock input from the ASCK pin.; Table 20-3. Relationship between Main System Clock and Baud Rate
- Page 468 – : Frequency of clock input to ASCK pin
- Page 469 – Serial Interface Channel 2 Operation; Caution Ensure that bit 0 and bits 3 through 6 are set to 0.
- Page 471 – CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 473 – ASIS is set with an 8-bit memory manipulation instruction.
- Page 476 – or a signal scaled from the clock input from the ASCK pin.; Table 20-5. Relationship between Main System Clock and Baud Rate
- Page 478 – One data frame consists of the following bits.
- Page 479 – Even parity
- Page 481 – bit, reception of one frame of data ends.; the receive error state will continue indefinitely.; Parity
- Page 482 – INTSR; STOP
- Page 483 – the TXE to 1, before executing the next transmission.; Whether Interrupt Request (INTSR) is Generated or Not
- Page 489 – SRIF; received bit by bit in synchronization with the serial clock.
- Page 490 – Figure 20-13. Circuit of Switching in Transfer Bit Order; following two conditions are satisfied.
- Page 491 – Details; Countermeasures
- Page 492 – T2 : The amount of time for 2 clocks of 5-bit counter source clock (f; BRGC; Example of countermeasures; An example of the countermeasures is shown below.
- Page 493 – INTSER is generated
- Page 495 – The real-time output port consists of the following hardware.
- Page 496 – CHAPTER 21 REAL-TIME OUTPUT PORT
- Page 497 – Real-Time Output Port Control Registers; The following three registers control the real-time output port.; Figure 21-3. Port Mode Register 12 Format; RTPM is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 498 – Table 21-3. Real-time Output Port Operating Mode and Output Trigger
- Page 499 – The following three types of interrupt functions are used.
- Page 500 – CHAPTER 22 INTERRUPT FUNCTIONS; Interrupt Sources and Configuration; is the highest priority and 20 is the lowest priority.
- Page 504 – Interrupt Function Control Registers; to interrupt request sources.
- Page 505 – or upon application of RESET input.; Figure 22-2. Interrupt Request Flag Register Format
- Page 506 – RESET input sets these registers to FFH.; Figure 22-3. Interrupt Mask Flag Register Format
- Page 507 – Figure 22-4. Priority Specify Flag Register Format
- Page 508 – These registers set the valid edge for INTP0 to INTP6.; Figure 22-5. External Interrupt Mode Register 0 Format
- Page 509 – Figure 22-6. External Interrupt Mode Register 1 Format
- Page 511 – Sampling Clock; Sampling Clock
- Page 512 – interrupt servicing are mapped.
- Page 513 – Interrupt Servicing Operations; if multiple non-maskable interrupt requests are generated.
- Page 514 – WDTM; Figure 22-11. Non-Maskable Interrupt Request Acknowledge Timing; Watchdog timer interrupt request flag
- Page 515 – If a new non-maskable interrupt request is generated during
- Page 516 – Maskable interrupt request acknowledge operation
- Page 517 – Start
- Page 518 – Software interrupt request acknowledge operation; and 003FH) are loaded into PC and branched.
- Page 519 – ISP and IE are the flags contained in PSW
- Page 520 – Example 1. Two multiple interrupts generated; IE = 0 : Interrupt request acknowledge disable
- Page 522 – requests are acknowledged.; CPU processing
- Page 523 – Figure 22-18. Basic Configuration of Test Function
- Page 524 – It indicates whether a clock timer overflow is detected or not.; Figure 22-19. Format of Interrupt Request Flag Register 1L; It is set to FFH by the RESET signal input.; Figure 22-20. Format of Interrupt Mask Flag Register 1L
- Page 525 – Figure 22-21. Key Return Mode Register Format; has been applied can be checked from the KRIF status.
- Page 527 – Table 23-1. Pin Functions in External Memory Expansion Mode
- Page 528 – CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION; Table 23-3. Pin Functions in Separate Bus Mode
- Page 529 – Memory map of
- Page 530 – 8P078Y when internal ROM capacity (PROM)
- Page 531 – External Device Expansion Function Control Register; RESET input sets this register to 10H.; Figure 23-2. Memory Expansion Mode Register Format; for the internal ROM, RAM, and SFR areas and the reserved area.
- Page 532 – Figure 23-3. Internal Memory Size Switching Register Format
- Page 533 – It is set by an 8-bit memory manipulation instruction.; Figure 23-4. External Bus Type Select Register Format
- Page 534 – External Device Expansion Function Timing; from external memory.
- Page 536 – Figure 23-6. External Memory Read Timing in Multiplexed Bus Mode
- Page 537 – Figure 23-7. External Memory Write Timing in Multiplexed Bus Mode
- Page 541 – Figure 23-10. External Memory Read Timing in Separate Bus Mode
- Page 542 – Figure 23-11. External Memory Write Timing in Separate Bus Mode
- Page 545 – out intermittent operations such as watch applications.; request, it enables intermittent operations to be carried out.; the main system clock or the subsystem clock.
- Page 546 – CHAPTER 24 STANDBY FUNCTION; Standby function control register; OSTS is set with an 8-bit memory manipulation instruction.; input or by interrupt request generation.
- Page 547 – Standby Function Operations; Notes 1. Including case when external clock is supplied.
- Page 548 – (a) Release by unmasked interrupt request; standby status is acknowledged.
- Page 549 – Figure 24-3. HALT Mode Released by RESET Input; Figures in parentheses apply to operation with f
- Page 550 – The operating status in the STOP mode is described below.
- Page 552 – Figure 24-5. STOP Mode Released by RESET Input
- Page 553 – CHAPTER 25 RESET FUNCTION; External reset input with RESET pin; Cautions 1. For an external reset, input a low level for 10
- Page 554 – CHAPTER 25 RESET FUNCTION; Figure 25-2. Timing of Reset by RESET Input
- Page 555 – The values after reset depend on the product.
- Page 556 – Serial interface
- Page 559 – Table 26-1. ROM Correction Configuration
- Page 560 – CHAPTER 26 ROM CORRECTION; RESET input sets CORAD0 and CORAD1 to 0000H.; Figure 26-2. Correction Address Registers 0 and 1 Format
- Page 561 – ROM Correction Control Registers; RESET input sets CORCN to 00H.; Figure 26-3. Correction Control Register Format
- Page 562 – EEPROM; ROM Correction Application; as EEPROM; the correction branch.
- Page 563 – expansion RAM with the main program.; Yes; ROM correction
- Page 565 – ROM Correction Example; fetch address value after the main program is started.; BR; Internal ROM
- Page 566 – Program Execution Flow; Area filled with diagonal lines : Internal expansion RAM
- Page 567 – (2) Branches to branch destination judgment program
- Page 568 – Cautions on ROM Correction
- Page 569 – Table 27-1. Differences between PROM and Mask ROM Versions; bytes by RESET input.; consumer samples (not engineering samples) of the mask ROM version.
- Page 570 – Internal Memory Size Switching Register; Figure 27-1. Internal Memory Size Switching Register Format
- Page 571 – Internal Extension RAM Size Switching Register; Caution When the
- Page 572 – PROM Programming; Table 27-4. PROM Programming Operating Modes
- Page 574 – N = Last address of program; Figure 27-3. Page Program Mode Flowchart
- Page 576 – Figure 27-5. Byte Program Mode Flowchart
- Page 577 – before applying V; , and remove it after removing V; applied to V; may have an adverse affect on reliability.
- Page 578 – and V; Address Input
- Page 579 – Screening of One-Time PROM Versions
- Page 581 – CHAPTER 28 INSTRUCTION SET; This chapter describes each instruction set of the
- Page 582 – Legends Used in Operation List; Operand identifiers and description methods
- Page 583 – Description of “operation” column
- Page 584 – ) selected by the processor
- Page 592 – Instructions Listed by Addressing Type
- Page 597 – The major differences between the; Not available in the Y subseries
- Page 599 – APPENDIX B DEVELOPMENT TOOLS
- Page 600 – APPENDIX B DEVELOPMENT TOOLS
- Page 602 – B.1 Language Processing Software
- Page 604 – B.2 PROM Writing Tools
- Page 610 – I J K; note: Product by TOKYO ELETECH CORPORATION.
-
Page 613 – APPENDIX C EMBEDDED SOFTWARE;
- Page 614 – APPENDIX C EMBEDDED SOFTWARE
- Page 616 – APPENDIX D REGISTER INDEX
- Page 619 – D.2 Register Symbol Index
- Page 623 – APPENDIX E REVISION HISTORY; Differences with; of AV; CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION
- Page 625 – Table 7-2. Relationship between CPU clock and Minimum
- Page 627 – Thank you for your kind support.; Document Rating; Name; Facsimile
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PD78076
µ
PD78078
µ
PD78P078
µ
PD78076Y
µ
PD78078Y
µ
PD78P078Y
µ
PD78078, 78078Y Subseries
8-bit Single-chip Microcontrollers
Document No. U10641EJ4V0UM00 (4th edition)
Date Published December 1997 N
1994
User’s Manual
Printed in Japan
©
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Summary
Page 3 - NOTES FOR CMOS DEVICES; to be taken for PW boards with semiconductor devices on it.; or GND with a resistor, if it is considered to have a possibility of
3 FIP, EEPROM, IEBus, and QTOP are trademarks of NEC Corporation. MS-DOS, Windows, and WindowsNT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, IBM PC/AT, and PC DOS are trademarks of International Business Machines Corpo...
Page 4 - The customer must judge the need for license:
4 The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. Purchase of NEC I 2 C components conveys a license under the Philips I 2 C Patent Rights to use these components in an I 2 C system, provided that the system conforms to the I 2 ...
Page 5 - Regional Information; • Device availability
5 NEC Electronics Inc. (U.S.) Santa Clara, CaliforniaTel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Duesseldorf, GermanyTel: 0211-65 03 02Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UKTel: 01908-691-133Fax: 01908-670-290 NEC Electronics ...
