NEC PD78058FY - Manual
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Table of Contents:
- Page 3 – NOTES FOR CMOS DEVICES; unused pin should be connected to V; or GND with a resistor, if it is considered to have a
- Page 5 – Regional Information; • Device availability
- Page 6 – MAJOR REVISIONS IN THIS EDITION; Page; Figure 19-3 Serial Operating Mode Register 2 Format was changed.; The mark
- Page 7 – PREFACE; Readers
- Page 9 – Chapter Organization; This manual divides the descriptions for the
- Page 11 – Related Documents; versions. However, preliminary versions are not marked as such.; Related Documents for
- Page 16 – CHAPTER 4 PIN FUNCTION (
- Page 18 – Overview of the
- Page 19 – CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
- Page 20 – CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (
- Page 22 – APPENDIX A DIFFERENCES AMONG
- Page 35 – Notes
- Page 36 – CHAPTER 1 OUTLINE (; In the case of the; Ordering Information; Remark; indicates ROM code suffix.
- Page 38 – Cautions 1. Be sure to connect Internally Connected (IC) pin to V; electrical potential as V; separate from V; Pin connection in parentheses is intended for the
- Page 39 – Pin Identifications
- Page 40 – : Connect independently to V; : Programming Power Supply; PGM
- Page 41 – Note; Under planning
- Page 43 – Pin connection in parentheses is intended for the
- Page 44 – Outline of Function
- Page 45 – Differences Between the
- Page 46 – There are mask options in the mask ROM versions (; Table 1-2. Mask Options of Mask POM Versions; Pin Names
- Page 48 – CHAPTER 2 OUTLINE (; Ordering Information; Under development
- Page 50 – Note Under development
- Page 56 – Outline of Function
- Page 57 – Under development for the; Differences Between the
- Page 58 – The mask ROM versions (; Table 2-2. Mask Options of Mask ROM Versions
- Page 59 – CHAPTER 3 PIN FUNCTION (
- Page 60 – CHAPTER 3 PIN FUNCTION (
- Page 61 – Cautions
- Page 63 – connect it to a ground line which is separate from V
- Page 65 – Description of Pin Functions
- Page 67 – Serial interface automatic transmit/receive busy input pins; Caution; output and buzzer output.
- Page 69 – The following operating modes can be specified bit-wise.; according to the function the user requires.
- Page 70 – that are not used as analog outputs must be set as follows:
- Page 72 – Connect it directly to the V; with the shortest possible wire in the normal operating mode.; pin because the wiring between those two pins; Connect IC pins to V; IC
- Page 78 – CHAPTER 4 PIN FUNCTION (
- Page 81 – same electrical potential as V; p i n i s u s e d a s t h e g r o u n d p o t e n t i a l f o r t h e A / D c o n v e r t e r a n d
- Page 83 – Description of Pin Functions
- Page 95 – CHAPTER 5 CPU ARCHITECTURE; 4-Kbyte memory spaces can be accessed in the
- Page 96 – CHAPTER 5 CPU ARCHITECTURE
- Page 98 – The
- Page 99 – Caution Do not access addresses where the SFR is not assigned.
- Page 100 – to Section 5.4 Operand Address Addressing.
- Page 101 – memory size switching register.
- Page 103 – Processor Registers; PC
- Page 104 – These are 2-bit flags to select one of the four register banks.
- Page 105 – instruction execution.
- Page 106 – Register
- Page 107 – Figure 5-12. General Register Configuration
- Page 110 – This register is provided only in the
- Page 112 – Instruction Address Addressing; the next instruction.
- Page 113 – instruction branches to an area of addresses 0800H through 0FFFH.; In the case of CALLF !addr11 instruction
- Page 115 – rp
- Page 116 – Operand Address Addressing; manipulation during instruction execution.
- Page 117 – Identifier
- Page 118 – Operation code; Memory
- Page 120 – Short Direct Memory
- Page 123 – can be carried out for all the memory spaces.
- Page 125 – CHAPTER 6 PORT FUNCTIONS
- Page 126 – CHAPTER 6 PORT FUNCTIONS
- Page 127 – If it is used as a port, rewriting the output latch of its output.
- Page 130 – Port Configuration; A port consists of the following hardware:; connec-tion for subsystem clock oscillation.; the output mode is used, set the interrupt mask flag to 1.
- Page 131 – PM
- Page 133 – Format and Figure 18-3 Serial Operating Mode Register 1 Format.
- Page 135 – and Figure 18-3 Serial Operating Mode Register 1 Format.
- Page 138 – Figure 6-11. Block Diagram of Falling Edge Detection Circuit
- Page 140 – Pins P60 to P63 can drive LEDs directly.; depending on the following conditions:
- Page 146 – Port Function Control Registers; The following four types of registers control the ports.
- Page 149 – RESET input sets this register to 00H.; Cautions 1. P00 and P07 pins do not incorporate a pull-up resistor.
- Page 150 – This register is used to set input/output of port 4.; Figure 6-21. Memory Expansion Mode Register Format
- Page 151 – KRM is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 6-22. Key Return Mode Register Format
- Page 152 – Port Function Operations
- Page 153 – latch contents are output from the pins.; than the manipulated bit.; Selection of Mask Option; Table 6-6. Comparison Between Mask ROM Version and PROM Version; Pin Name
- Page 155 – types of system clock oscillators are available.; Clock Generator Configuration; The clock generator consists of the following hardware.; Table 7-1. Clock Generator Configuration
- Page 156 – CHAPTER 7 CLOCK GENERATOR; Figure 7-1. Block Diagram of Clock Generator; Selector
- Page 157 – Clock Generator Control Register; The clock generator is controlled by the following two registers:; Figure 7-2. Subsystem Clock Feedback Resistor; FRC
- Page 158 – Figure 7-3. Processor Clock Control Register Format; system clock oscillation. A STOP instruction should not be used.; Caution Bit 3 must be set to 0.; or f; : Subsystem clock oscillator frequency
- Page 159 – Figure 7-4. Oscillation Mode Selection Register Format
- Page 160 – Figure 7-5. Main System Clock Waveform due to Writing to OSMS; must be 2.7 V or higher before the write execution.; : Main system clock oscillation frequency
- Page 161 – System Clock Oscillator; connected to the X1 and X2 pins.; Figure 7-6. External Circuit of Main System Clock Oscillator
- Page 162 – and an antiphase clock signal to the XT2 pin.; resistors in series on the side of XT2.
- Page 163 – (d) Current flows through the grounding line; in series on the XT2 side.; to V
- Page 164 – The scaler divides the main system clock oscillator output (f; connect the XT1 and XT2 pins as follows.; pins as described above.
- Page 165 – Clock Generator Operations
- Page 166 – (b) Operation when MCC is set in case of main system clock operation
- Page 167 – the following operations are carried out.; Changing System Clock and CPU Clock Settings
- Page 168 – Table 7-3. Maximum Time Required for CPU Clock Switchover; Figures in parentheses apply to operation with f
- Page 169 – System clock and CPU clock switching procedure
- Page 171 – Overview of the; related devices of the
- Page 173 – Values in parentheses when operated at f
- Page 174 – The 16-bit timer/event counter consists of the following hardware.
- Page 175 – Notes 1. Edge detection circuit
- Page 180 – : Subsystem clock oscillation frequency; Figures in parentheses apply to operation with f; TMC0 is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 181 – CR00 : Compare register 00
- Page 183 – If LVS0 and LVR0 are read after data is set, they will be 0.
- Page 184 – PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 185 – Figure 8-8. External Interrupt Mode Register 0 Format
- Page 186 – SCS is set with an 8-bit memory manipulation instruction.
- Page 187 – the description of the respective control registers for details.
- Page 188 – Figure 8-11. Interval Timer Configuration Diagram
- Page 189 – : Main system clock oscillation frequency; Figures in parentheses apply to operation with f; and the sub-cycle determined by 2; Be sure to write 0 to bits 0 and 1 of CR00.
- Page 190 – Figure 8-13. Control Register Settings for PWM Output Operation
- Page 191 – The analog output voltage (V; : External switching circuit reference voltage; Figure 8-14. Example of D/A Converter Configuration with PWM Output; synthesizer type TV tuner.; Figure 8-15. TV Tuner Application Circuit Example
- Page 193 – Pulse width measurement operations; eliminating noise with a short pulse width.; Free-Running Counter and One Capture Register
- Page 194 – Internal Bus; and One Capture Register (with Both Edges Specified)
- Page 195 – (2) Measurement of two pulse widths with free-running counter; thus eliminating noise with a short pulse width.
- Page 196 – Figure 8-21. Timing of Pulse Width Measurement Operation with
- Page 197 – Free-Running Counter and Two Capture Registers
- Page 198 – Counter and Two Capture Registers (with Rising Edge Specified)
- Page 199 – (4) Pulse width measurement by means of restart; with a short pulse width.; compare register 00 (CR00) cannot perform the capture operation.
- Page 201 – Clear; Figure 8-27. External Event Counter Configuration Diagram
- Page 202 – One-shot pulse output disabled; frequency to be output.; Figure 8-29. Control Register Settings in Square-Wave Output Mode
- Page 206 – P30 pin with a TI00/P00 valid edge as an external trigger.
- Page 209 – (4) Capture register data retention timings; detection of the valid edge.; Figure 8-37. Capture Register Data Retention Timing
- Page 210 – OFV0 flag is set to 1 in the following case.; Figure 8-38. Operation Timing of OVF0 Flag
- Page 216 – Note See Figure 6-9 P30 to P37 Block Diagram.
- Page 218 – The section in the broken line is an output control circuit.; : Serial clock frequency
- Page 219 – operation before setting data.
- Page 221 – Figures in parentheses apply to operation with f
- Page 222 – should be set with TCE1.
- Page 223 – Cautions 1. Be sure to stop the timer operation before setting TOC1.
- Page 226 – Values in parentheses when operated at f
- Page 228 – is input. Either the rising or falling edge can be selected.
- Page 230 – overflow signal of TM1 is used as the count clock of TM2.
- Page 236 – with the count pulse.; Figure 9-15. Event Counter Operation Timing
- Page 237 – is necessary to restart the timer after changing CR10 and CR20.
- Page 240 – CHAPTER 10 WATCH TIMER; Watch Timer Configuration
- Page 241 – Prescaler; INTWT
- Page 242 – Figure 10-2. Timer Clock Select Register 2 Format; : Subsystem clock oscillation frequency
- Page 243 – Figure 10-3. Watch Timer Mode Control Register Format
- Page 244 – Watch Timer Operations; Table 10-3. Interval Timer Interval Time
- Page 246 – CHAPTER 11 WATCHDOG TIMER; Interrupt requests are generated at the preset time intervals.
- Page 247 – Watchdog Timer Configuration; The watchdog timer consists of the following hardware.; Table 11-3. Watchdog Timer Configuration; Item; Figure 11-1. Watchdog Timer Block Diagram; Control register
- Page 248 – Watchdog Timer Control Registers; This register sets the watchdog timer count clock.
- Page 249 – Figure 11-2. Timer Clock Select Register 2 Format
- Page 250 – WDTM is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 11-3. Watchdog Timer Mode Register Format; Thus, once counting starts, it can only be stopped by RESET input.; regardless of the contents of WDTM3.
- Page 251 – Watchdog Timer Operations; Table 11-4. Watchdog Timer Runaway Detection Time
- Page 252 – requests, the INTWDT default has the highest priority.; timer mode is not set unless RESET input is applied.; Interval Time; Figures in parentheses apply to operation with f
- Page 253 – CLOE; CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT; Follow the procedure below to output clock pulses.
- Page 254 – CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT; Clock Output Control Circuit Configuration; Table 12-1. Clock Output Control Circuit Configuration; Clock Output Function Control Registers
- Page 255 – Figure 12-3. Timer Clock Select Register 0 Format
- Page 256 – Figure 12-4. Port Mode Register 3 Format; Address
- Page 257 – CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT; Follow the procedure below to output the buzzer frequency.; Buzzer Output Control Circuit Configuration; Table 13-1. Buzzer Output Control Circuit Configuration; Figure 13-1. Buzzer Output Control Circuit Block Diagram
- Page 258 – CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT; Buzzer Output Function Control Registers; This register sets the buzzer output frequency.; watchdog timer count clock.
- Page 259 – Figure 13-2. Timer Clock Select Register 2 Format
- Page 260 – Figure 13-3. Port Mode Register 3 Format
- Page 261 – CHAPTER 14 A/D CONVERTER
- Page 262 – CHAPTER 14 A/D CONVERTER
- Page 263 – Bits 0 and 1 of External Interrupt Mode Register 1 (INTM1)
- Page 264 – adversely affect the converted values of other channels.
- Page 266 – Setting prohibited because A/D conversion time is less than 19.1
- Page 267 – ADIS is set with an 8-bit memory manipulation instruction.; Cautions 1. Set the analog input channel in the following order.
- Page 268 – This register sets the valid edge for INTP3 to INTP6.; Figure 14-4. External Interrupt Mode Register 1 Format
- Page 269 – by the tap selector.
- Page 270 – After RESET input, the value of ADCR is undefined.
- Page 271 – Input voltage and conversion results
- Page 272 – • Software start: Conversion is started by setting ADM.
- Page 273 – tinues repeatedly until new data is written to ADM.
- Page 274 – pin at this time, this current must
- Page 275 – Figure 14-10. Connection of Analog Input Pin
- Page 276 – the analog input after the change has been completed.
- Page 277 – pin; Pin
- Page 279 – CHAPTER 15 D/A CONVERTER; The conversion method used is the R-2R resistor ladder method.
- Page 280 – CHAPTER 15 D/A CONVERTER; The D/A converter consists of the following hardware.
- Page 281 – to pins ANO0 and ANO1.; trigger and before the next output trigger.; DACSn
- Page 282 – The DAM is set with a 1-bit or 8-bit memory manipulation instruction.; a pull-up resistor should be disconnected.
- Page 283 – the next trigger is generated.
- Page 284 – Cautions Related to D/A Converter; Figure 15-3. Use Example of Buffer Amplifier; When only either one of the D/A converter channels is used with AV; , the pin that is not used as; low level from the pin.
- Page 286 – CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (; Serial Interface Channel 0 Functions
- Page 288 – Serial Interface Channel 0 Configuration; Table 16-2. Serial Interface Channel 0 Configuration
- Page 289 – Figure 16-2. Serial Interface Channel 0 Block Diagram
- Page 290 – SIO0 is set with an 8-bit memory manipulation instruction.
- Page 291 – is used, the circuit also controls clock output to the SCK0/P27 pin.; When WUP
- Page 292 – Serial Interface Channel 0 Control Registers
- Page 293 – Figure 16-3. Timer Clock Select Register 3 Format
- Page 294 – function and displays the address comparator match signal.; PMXX : Port Mode Register
- Page 296 – SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 298 – SINT is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 16-6. Interrupt Timing Specify Register Format; SVA
- Page 299 – Serial Interface Channel 0 Operations; • Operation stop mode
- Page 300 – CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 303 – RELT; SI0 pin is latched in SIO0 at the rising edge of SCK0.
- Page 304 – Figure 16-9. Circuit of Switching in Transfer Bit Order; conditions are satisfied.
- Page 305 – the board can be decreased.; Figure 16-10. Example of Serial Bus Configuration with SBI
- Page 306 – software, the software must be heavily loaded.; (b) Chip select function by address transmission; The busy signal to report the slave busy state is controlled.
- Page 307 – The dotted line indicates READY status.; Address Transfer
- Page 308 – This signal is output by the master device.
- Page 309 – in order to select a particular slave device.; Figure 16-15. Slave Selection with Address
- Page 310 – by address transmission.; Data
- Page 311 – [When output in synchronization with 11th clock SCK0]
- Page 312 – terminates the output of SCK0 serial clock.
- Page 313 – impossible to use it as a normal port.
- Page 315 – Busy mode can be cleared by starting serial interface transfer.
- Page 318 – ACKT
- Page 319 – (b) When set after completion of transfer
- Page 320 – (a) When ACK signal is output at 9th clock of SCK0; ACKD; BUSY
- Page 322 – In BUSY state, transfer starts after the READY state is set.
- Page 324 – instead of using the address match detection method.; two or more devices by outputting an “address” to the serial bus.
- Page 327 – Figure 16-29. Data Transmission from Master Device to Slave Device
- Page 328 – Figure 16-30. Data Transmission from Slave Device to Master Device
- Page 330 – (10) How to determine the slave busy state; transfer of the 1st byte after RESET input.
- Page 331 – Master
- Page 333 – CSIIF0 : Interrupt request flag corresponding to INTCSI0
- Page 334 – is carried out bit-wise in synchronization with the serial clock.
- Page 335 – Figure 16-33 shows RELT and CMDT operations.; receiving data, so write FFH in SIO0 in advance.
- Page 336 – normal serial clock output.
- Page 338 – CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (; Serial Interface Channel 0 Functions; Serial interface channel 0 employs the following four modes.; transfer processing time.
- Page 339 – This mode is in compliance with the I; Figure 17-1. Serial Bus Configuration Example Using I
- Page 340 – Serial Interface Channel 0 Configuration; Table 17-2. Serial Interface Channel 0 Configuration
- Page 341 – Figure 17-2. Serial Interface Channel 0 Block Diagram
- Page 345 – Serial Interface Channel 0 Control Registers
- Page 346 – Figure 17-3. Timer Clock Select Register 3 Format
- Page 348 – Figure 17-4. Serial Operating Mode Register 0 Format; C bus mode, the clock frequency becomes 1/16 of that output from TO2.
- Page 350 – Notes 1. Setting should be performed before transfer.; However, the BSYE flag is not cleared to 0.
- Page 351 – RESET input sets SINT to 00H.; When not using the I
- Page 352 – Notes 1. When using wake-up function in the I
- Page 353 – Serial Interface Channel 0 Operations
- Page 357 – Figure 17-9. Circuit of Switching in Transfer Bit Order
- Page 360 – CSIIF0: Interrupt request flag corresponding to INTCSI0
- Page 362 – Figure 17-12 shows RELT and CMDT operations.
- Page 363 – C bus mode operation; The I; Figure 17-13. Example of Serial Bus Configuration Using I
- Page 364 – C bus mode functions
- Page 365 – C bus mode for details of the start condition output.; If it is 1, it is the slave device which will send data to the master.; Figure 17-17. Transfer Direction Specification
- Page 366 – as a stop condition signal.
- Page 367 – state due to preparing for transmitting or receiving data.
- Page 369 – SBIC is set by a 1-bit or 8-bit memory manipulation instruction.; This setting must be performed prior to transfer start.
- Page 370 – SINT is set by the 1-bit or 8-bit memory manipulation instruction.
- Page 371 – A list of signals in the I; C Bus Mode
- Page 372 – In the I
- Page 373 – (a) Comparison of SIO0 data before and after transmission
- Page 374 – Figure 17-22. Data Transmission from Master to Slave
- Page 377 – Figure 17-23. Data Transmission from Slave to Master
- Page 380 – C bus mode
- Page 381 – P27 output latch to 1 after execution of an SIO0 write instruction.
- Page 383 – Note Maintenance product
- Page 384 – • Example of program releasing serial transfer status
- Page 385 – To Internal Logic
- Page 386 – CLC (manipulated by bit manipulation instruction); Figure 17-29. Logic Circuit of SCL Signal
- Page 387 – Serial interface channel 1 employs the following three modes.
- Page 388 – CHAPTER 18 SERIAL INTERFACE CHANNEL 1; Serial Interface Channel 1 Configuration; Table 18-1. Serial Interface Channel 1 Configuration
- Page 389 – Figure 18-1. Serial Interface Channel 1 Block Diagram
- Page 390 – SIO1 is set with an 8-bit memory manipulation instruction.; RESET input sets ADTP to 00H.
- Page 391 – Serial Interface Channel 1 Control Registers; Automatic data transmit/receive interval specify register (ADTI)
- Page 392 – Figure 18-2. Timer Clock Select Register 3 Format
- Page 393 – CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 18-3. Serial Operating Mode Register 1 Format
- Page 394 – ADTC is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 395 – Notes 1. The interval is dependent only on CPU processing.
- Page 396 – , the minimum interval time
- Page 399 – Serial Interface Channel 1 Operations; Notes 1. Can be used freely as port function.
- Page 401 – pin is latched into SIO1 at the rising edge of SCK1.
- Page 406 – Main system clock frequency (f
- Page 410 – subtracting 1 from the number of transmit data bytes.
- Page 411 – TRF; are transmitted or received.; Figure 18-8. Basic Transmission/Reception Mode Operation Timings
- Page 412 – Automatic data transmit/receive address pointer
- Page 413 – FADFH
- Page 415 – BUSY pins can be used as normal input/ports.; Figure 18-11. Basic Transmission Mode Operation Timings; CSIIF1 : Interrupt request flag
- Page 416 – Figure 18-12. Basic Transmission Mode Flowchart
- Page 417 – Figure 18-13. Internal Buffer RAM Operation in 6-Byte Transmission
- Page 419 – and P24/BUSY pins can be used as ordinary input/output ports.; Figure 18-14. Repeat Transmission Mode Operation Timing; Interval
- Page 420 – Figure 18-15. Repeat Transmission Mode Flowchart
- Page 421 – initial pointer value is reset in ADTP.; Figure 18-16. Internal Buffer RAM Operation in 6-Byte Transmission
- Page 423 – is suspended upon completion of 8-bit data transfer.
- Page 424 – device and slave device.; Master Device
- Page 425 – The busy signal cannot be controlled with an external clock.; CSIIF1: Interrupt request flag
- Page 426 – or receiving can wait while the busy signal is being input.
- Page 427 – STB
- Page 428 – (c) Bit Slippage Detection Function Through the Busy Signal; bit slippage can be detected.
- Page 429 – interval may be longer than the value indicated in Table 18-3.
- Page 430 – Internal Clock
- Page 433 – Serial interface channel 2 has the following three modes.
- Page 434 – CHAPTER 19 SERIAL INTERFACE CHANNEL 2; Serial Interface Channel 2 Configuration; Table 19-1. Serial Interface Channel 2 Configuration
- Page 435 – to f; Figure 19-1. Serial Interface Channel 2 Block Diagram; See Figure 19-2 for the baud rate generator configuration.
- Page 436 – Figure 19-2. Baud Rate Generator Block Diagram
- Page 437 – Writing data to TXS starts the transmit operation.; RXS cannot be directly manipulated by a program.
- Page 438 – Serial Interface Channel 2 Control Registers; Figure 19-3. Serial Operating Mode Register 2 Format
- Page 439 – ASIM is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 19-4. Asynchronous Serial Interface Mode Register Format
- Page 440 – Table 19-2. Serial Interface Channel 2 Operating Mode Settings
- Page 441 – will continue to be generated until RXB is read.
- Page 442 – BRGC is set with an 8-bit memory manipulation instruction.
- Page 444 – scaled from the clock input from the ASCK pin.; Table 19-3. Relationship Between Main System Clock and Baud Rate
- Page 445 – Frequency of clock input to ASCK pin
- Page 446 – Serial Interface Channel 2 Operation
- Page 448 – CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
- Page 450 – ASIS is set with 8-bit memory manipulation instruction.
- Page 453 – a signal scaled from the clock input from the ASCK pin.; Table 19-5. Relationship Between Main System Clock and Baud Rate
- Page 455 – data frame is composed of each of the bits shown below.
- Page 456 – Even parity
- Page 457 – Request Generation Timing
- Page 458 – is enabled and sampling of the RxD pin input is performed.; Parity
- Page 460 – set TXE to 1 before executing the next transmission.; Request (INTSR) Generation When Receiving Is Terminated
- Page 466 – received bit by bit in synchronization with the serial clock.
- Page 467 – Figure 19-13. Circuit of Switching in Transfer Bit Order; following two conditions are satisfied.
- Page 468 – Details; Countermeasures
- Page 469 – T2 : The amount of time for 2 clocks of 5-bit counter source clock (f; BRGC; Example of countermeasures; An example of the countermeasures is shown below.
- Page 470 – INTSER is Generated
- Page 471 – CHAPTER 20 REAL-TIME OUTPUT PORT
- Page 472 – CHAPTER 20 REAL-TIME OUTPUT PORT; Real-Time Output Port Configuration; The real-time output port consists of the following hardware.
- Page 474 – Real-Time Output Port Control Registers; The following three registers control the real-time output port.; Figure 20-3. Port Mode Register 12 Format; RTPM is set with a 1-bit or 8-bit memory manipulation instruction.; Symbol
- Page 475 – Table 20-3. Real-time Output Port Operating Mode and Output Trigger
- Page 477 – The following three types of interrupt functions are used.
- Page 478 – CHAPTER 21 INTERRUPT AND TEST FUNCTIONS; Interrupt Sources and Configuration; highest priority and 18 is the lowest priority.
- Page 482 – Interrupt Function Control Registers; to interrupt request sources.
- Page 483 – or upon application of RESET input.; Figure 21-2. Interrupt Request Flag Register Format
- Page 484 – RESET input sets these registers to FFH.; Figure 21-3. Interrupt Mask Flag Register Format
- Page 485 – Figure 21-4. Priority Specify Flag Register Format
- Page 486 – These registers set the valid edge for INTP0 to INTP6.; Figure 21-5. External Interrupt Mode Register 0 Format
- Page 487 – Figure 21-6. External Interrupt Mode Register 1 Format
- Page 489 – is active twice in succession.; Sampling Clock; Sampling Clock
- Page 490 – processing are mapped.
- Page 491 – Interrupt Servicing Operations; loaded into PC and branched.
- Page 492 – It Is Received; WDTM; Figure 21-11. Non-Maskable Interrupt Request Acknowledge Timing; TMIF4: Watchdog Timer Interrupt Request Flag
- Page 493 – If a new non-maskable interrupt request is generated during
- Page 494 – Maskable Interrupt request reception
- Page 495 – XXIF : Interrupt Request Flag
- Page 497 – Software interrupt request acknowledge operation; are loaded in the PC and branched.; during interrupt processing and permit interrupt reception.
- Page 498 – ISP and IE are the flags contained in PSW
- Page 499 – and the interrupt request reception permitted status must exist.
- Page 500 – IE = 0 : Interrupt Request Reception Prohibited
- Page 501 – CPU processing
- Page 502 – Figure 21-18. Basic Configuration of Test Function
- Page 503 – It indicates whether a watch timer overflow is detected or not.
- Page 504 – Figure 21-21. Key Return Mode Register Format; function can be realized.
- Page 505 – Table 22-1. Pin Functions in External Memory Expansion Mode
- Page 506 – CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION
- Page 507 – map when internal ROM (PROM) size is 56 Kbytes
- Page 508 – External Device Expansion Function Control Register; MM is set with an 1-bit or 8-bit memory manipulation instruction.; Figure 22-2. Memory Expansion Mode Register Format
- Page 509 – Figure 22-3. Memory Size Switching Register Format
- Page 510 – External Device Expansion Function Timing; External wait signal input pin.
- Page 511 – Figure 22-4. Instruction Fetch from External Memory
- Page 512 – Figure 22-5. External Memory Read Timing
- Page 513 – Figure 22-6. External Memory Write Timing
- Page 514 – Figure 22-7. External Memory Read Modify Write Timing
- Page 515 – intermittent operations such as in watch applications.; request, it enables intermittent operations to be carried out.; the main system clock or the subsystem clock.
- Page 516 – CHAPTER 23 STANDBY FUNCTION; Standby function control register; OSTS is set with an 8-bit memory manipulation instruction.; Values in parentheses apply to operating at f
- Page 517 – Standby Function Operations; The operating status in the HALT mode is described below.; Notes 1. Including when external clock is not supplied
- Page 518 – (a) Clear upon unmasked interrupt request; status is acknowledged.
- Page 519 – is executed after branching to the reset vector address.; Figure 23-3. HALT Mode Release by RESET Input; : main system clock oscillation frequency; Table 23-2. Operation After HALT Mode Release
- Page 520 – via a pull-up resistor; The operating status in the STOP mode is described below.
- Page 521 – (a) Release by unmasked interrupt request
- Page 522 – reset operation is performed.; Figure 23-5. Release by STOP Mode RESET Input; Table 23-4. Operation After STOP Mode Release
- Page 523 – CHAPTER 24 RESET FUNCTION; External reset input with RESET pin; Cautions 1. For an external reset, input a low level for 10
- Page 524 – Figure 24-2. Timing of Reset Input by RESET Input
- Page 525 – CHAPTER 24 RESET FUNCTION; The values after reset depend on the product.
- Page 527 – ROM Correction Configuration; Table 25-1. ROM Correction Configuration
- Page 528 – CHAPTER 25 ROM CORRECTION; RESET input sets CORAD0 and CORAD1 to 0000H.; Figure 25-2. Correction Address Registers 0 and 1 Format
- Page 529 – ROM Correction Control Registers; correction status flags show the values are matched.; Figure 25-3. Correction Control Register Format
- Page 530 – ROM Correction Application; EEPROM; EEPROM
- Page 531 – Yes; ROM correction; expansion RAM with the main program.
- Page 533 – BR; Internal ROM; EFFFH; ROM Correction Example
- Page 534 – Program Execution Flow; Area filled with diagonal lines : Internal expansion RAM
- Page 535 – (2) Branches to branch destination judgment program
- Page 536 – Cautions on ROM Correction
- Page 537 – RAM capacity becomes 1024 bytes.; Only the
- Page 538 – Memory Size Switching Register; Figure 26-1. Memory Size Switching Register Format
- Page 539 – Internal Expansion RAM Size Switching Register
- Page 540 – PROM Programming; a write address specification function.; Table 26-4. PROM Programming Operating Modes
- Page 542 – Figure 26-3. Page Program Mode Flowchart; N = Last address of program
- Page 544 – Figure 26-5. Byte Program Mode Flowchart
- Page 545 – Cautions 1. Be sure to apply V; before applying V; , and remove it after removing V; to the V; pin may have an adverse affect on device reliability.
- Page 546 – pin. Unused pins are handled as shown in paragraph,; and V; (3) Input the address of data to be read to pins A0 through A16.
- Page 547 – Screening of One-Time PROM Versions; Storage Temperature
- Page 549 – CHAPTER 27 INSTRUCTION SET; This chapter describes each instruction set of the
- Page 550 – CHAPTER 27 INSTRUCTION SET; Legends Used in Operation List; Operand identifiers and description methods
- Page 551 – Description of “operation” column
- Page 552 – When an area except the internal high-speed RAM area is accessed.; ) selected by the processor; This clock cycle applies to internal ROM program.; MOV
- Page 553 – When an area except the internal high-speed RAM area is accessed; ADD
- Page 554 – SUB
- Page 555 – OR
- Page 560 – Instructions Listed by Addressing Type
- Page 565 – APPENDIX A. DIFFERENCES AMONG; The major differences among the
- Page 567 – APPENDIX B DEVELOPMENT TOOLS; Figure B-1 shows the configuration of the development tools.
- Page 570 – B.1 Language Processing Software
- Page 571 – B.2 PROM Programming Tool
- Page 572 – Note Under development
- Page 576 – Note Only English mode is supported.
- Page 578 – I T E M
- Page 579 – Note Product of TOKYO ELETECH CORPORATION.
- Page 581 – APPENDIX C EMBEDDED SOFTWARE
- Page 582 – ITRON specifications.; permission in advance.; The part numbers; Notes 1. Can be operated in DOS environment.
- Page 583 – ITRON-specification subset OS. Nucleus of MX78K0 is supplied.
- Page 585 – APPENDIX D REGISTER INDEX
- Page 586 – APPENDIX D REGISTER INDEX
- Page 591 – APPENDIX E REVISION HISTORY; Major revisions by edition and revised chapters are shown below.
- Page 593 – Thank you for your kind support.; Document Rating; Name; Facsimile
Loading the manual
User’s Manual
Printed in Japan
©
µ
PD78058F, 78058FY Subseries
8-Bit Single-Chip Microcontrollers
µ
PD78056F
µ
PD78058F
µ
PD78P058F
µ
PD78058F(A)
µ
PD78056FY
µ
PD78058FY
µ
PD78P058FY
µ
PD78058FY(A)
Document No. U12068EJ2V0UM00 (2nd edition)
Date Published April 1998 N CP (K)
1997
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Summary
Page 3 - NOTES FOR CMOS DEVICES; unused pin should be connected to V; or GND with a resistor, if it is considered to have a
3 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and q...
Page 5 - Regional Information; • Device availability
5 NEC Electronics Inc. (U.S.) Santa Clara, CaliforniaTel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Duesseldorf, GermanyTel: 0211-65 03 02Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UKTel: 01908-691-133Fax: 01908-670-290 NEC Electronics ...
Page 6 - MAJOR REVISIONS IN THIS EDITION; Page; Figure 19-3 Serial Operating Mode Register 2 Format was changed.; The mark
6 MAJOR REVISIONS IN THIS EDITION Page Major Revision from Previous Edition Throughout The following products have already been developed: µ PD78056FGC- ××× -8BT, 78058FGC- ××× -8BT, 78P058FGC-8BT, 78056FYGC- ××× -8BT, 78058FYGC- ××× -8BT P133 to The block diagrams of the following ports were change...
