NEC PD750004 - Manual

NEC PD750004

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Table of Contents:

  • Page 3 – support systems or medical equipment for life support, etc.
  • Page 4 – Major Changes; Chapter 10 has been added.; The mark
  • Page 5 – PREFACE; Readers
  • Page 6 – Notation
  • Page 7 – Other documents
  • Page 9 – CONTENTS; CHAPTER 1
  • Page 11 – CHAPTER 7
  • Page 12 – OPERATING MODES WHEN WRITING TO AND VERIFYING
  • Page 13 – HARDWARE INDEX (ALPHABETICAL ORDER WITH RESPECT TO THE
  • Page 21 – CHAPTER 1 GENERAL; Model; Applications
  • Page 22 – FUNCTION OVERVIEW
  • Page 23 – Note Code orders on and after April 1, 1996 can be accepted.
  • Page 24 – DIFFERENCES AMONG SUBSERIES PRODUCTS
  • Page 26 – , keeping the wiring as short as possible.
  • Page 28 – Pin name
  • Page 29 – CHAPTER 2 PIN FUNCTIONS
  • Page 33 – Output; large-current output. These ports can directly drive the LED.
  • Page 36 – This is the positive power supply pin.; This is the ground pin.
  • Page 38 – Type A; Type D
  • Page 40 – CONNECTION OF UNUSED PINS
  • Page 41 – CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP; DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES
  • Page 42 – restoring the MBS with the PUSH or POP instruction.; Examples 1. The MBE is cleared, and a fixed memory bank is used.; MBE
  • Page 54 – GENERAL REGISTER BANK CONFIGURATION; (RB) enabled at instruction execution is determined as; Table 3-2. Register Bank to Be Selected with the RBE and RBS; Normal processing; Bank 0 is always selected.
  • Page 55 – restoring the RBS with the PUSH or POP instruction.; Example; SEL
  • Page 60 – Can also be manipulated as the BS in 8-bit units.
  • Page 62 – : Interrupt enable flag; Notes 1. Only bit 3 can be manipulated by an EI/DI instruction.
  • Page 64 – manipulation is performed.
  • Page 65 – CHAPTER 4 INTERNAL CPU FUNCTIONS; Mk I MODE/Mk II MODE SWITCH FUNCTIONS; It can be used in the 75XL CPUs having a ROM of up to 16KB.; Table 4-1. Differences between Mk I Mode and Mk II Mode
  • Page 66 – I mode, initialize the register to 10xxB; at the beginning of the program. To use the CPU in Mk II mode,; Figure 4-1. Stack Bank Selection Register Format
  • Page 67 – to the number of bytes in the instruction.
  • Page 69 – address with only the 8 low-order bits of the PC changed.
  • Page 70 – Note Can be used only in the MkII mode.
  • Page 73 – • Memory bank 15 (peripheral hardware area); Note Memory bank 0 or 1 can be selected as the stack area.
  • Page 74 – Specification of a Data Memory Bank; is addressed by 8-bit immediate data or a register pair.; • Peripheral hardware area : Chapter 5
  • Page 76 – GENERAL REGISTER: 8 x 4 BITS x 4 BANKS; be used as data pointers.; Data memory
  • Page 77 – Bit accumulator
  • Page 78 – Table 4-2. Stack Area to Be Selected by the SBS; boundaries is enabled only by resetting the SBS.
  • Page 80 – PSW bits other than MBE and RBE are not saved or restored.
  • Page 83 – MOV
  • Page 84 – Table 4-5. Information Indicated by the Interrupt Status Flag; before an interrupt occurs.
  • Page 85 – Figure 3-2 shows the range of addressing using MBE and MBS settings.
  • Page 86 – Table 4-6. Register Bank to Be Selected with the RBE and RBS
  • Page 87 – CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS; Figure 5-1. Data Memory Addresses of Digital Ports
  • Page 88 – Table 5-1. Types and Features of Digital Ports; is turned off so that these ports are in the input mode.
  • Page 92 – Figure 5-5. Configurations of Ports 4 and 5
  • Page 99 – output buffers kept off.; (2) Operation when the output mode is set; bits is executed, output latch data is manipulated.
  • Page 101 – is connected by software in the format shown in Figure 5-8.
  • Page 102 – latch data on the internal bus.
  • Page 104 – CLOCK GENERATOR; Figure 5-11 shows the configuration of the clock generator.; Figure 5-11. Block Diagram of the Clock Generator; : Main system clock frequency; : Subsystem clock frequency; ) is equal to one machine cycle of an instruction.
  • Page 107 – CPU operation mode control bits; : Output frequency from the main system clock oscillator; f; : Output frequency from the subsystem clock oscillator
  • Page 108 – Figure 5-13. Format of the System Clock Control Register; is needed to change the system clock. This means
  • Page 110 – poten tial as that of V; . It must not be grounded to a grounding pattern carry; a resistor must be added to XT2 in series.
  • Page 112 – (5) Control functions of subsystem clock oscillator; the operating supply voltage is high (V
  • Page 114 – Setting after switching; machine; machine
  • Page 115 – for stable oscillation.
  • Page 116 – (1) Configuration of the clock output circuit; Figure 5-20 shows the configuration of the clock output circuit.; (2) Functions of the clock output circuit; or to supply clock pulses to a peripheral LSI device.; Figure 5-20. Configuration of the Clock Output Circuit; or disabling clock output.
  • Page 117 – is the CPU clock selected by PCC.
  • Page 118 – Figure 5-22. Application to Remote Control Output
  • Page 119 – A 4-bit memory manipulation instruction is used to set the BTM.
  • Page 120 – Figure 5-24. Format of the Basic Interval Timer Mode Register; Basic interval timer/watchdog timer start control bit
  • Page 126 – Figure 5-26 shows the configuration of the clock timer.; Figure 5-26. Block Diagram of the Clock Timer; The values in parentheses are for f
  • Page 133 – Timer start indication bit
  • Page 137 – Table 5-6. Resolution and Longest Setup Time; Mode register
  • Page 138 – Caution Set a value other than 00H in the modulo register (TMODn).
  • Page 141 – a signal applied to the TI0 pin must have a pulse wider than that.
  • Page 142 – (5) Operation after the modulo register is changed; restarted after the contents of the modulo register are changed.
  • Page 143 – The functions of the four modes are outlined below.
  • Page 144 – Figure 5-39 shows the block diagram of the serial interface.
  • Page 147 – detect control signals generated in the SBI mode.; P01 output latch; When the RESET signal is entered, this latch is set to 1.
  • Page 148 – Serial interface operation enable/disable specification bit (W); undefined value may result during transfer.
  • Page 150 – Serial transfer dependent on the contents of CSIM is enabled.
  • Page 151 – of input data from the serial bus. SBIC is used mainly in the SBI mode.
  • Page 152 – Cautions 1. Never set ACKT before or during serial transfer.
  • Page 153 – RELD; after serial transfer; RELT; after serial transfer.
  • Page 154 – Figure 5-42. Peripheral Hardware of Shift Register
  • Page 155 – operation mode register.
  • Page 157 – Communication is performed using three lines:; Remark The μPD750008 can also be used as a slave CPU.; • Serial bus interface control register (SBIC)
  • Page 158 – Serial interface operation mode selection bit (W)
  • Page 159 – SBIC is manipulated using a bit memory manipulation instruction.; CMDT; in phase with the serial clock.
  • Page 160 – SO pin can be manipulated by setting the RELT bit and CMDT bit.
  • Page 161 – Figure 5-45 shows operations of RELT and CMDT.; Figure 5-45. Operations of RELT and CMDT; order of SIO is always the same.
  • Page 165 – manipulated bit by bit.
  • Page 166 – SBIC is manipulated using a bit manipulation instruction.
  • Page 168 – Figure 5-49. Operations of RELT and CMDT; conditions are satisfied:; written to SIO beforehand.
  • Page 169 – methods described below.; and μPD7225G are connected as slaves.
  • Page 170 – Figure 5-50. Example of SBI System Configuration
  • Page 171 – on a circuit board can be simplified.
  • Page 172 – Serial data forms one frame as shown below.; Address transfer
  • Page 173 – detect the bus release signal.
  • Page 174 – Figure 5-55. Slave Selection Using an Address; data to or from the slave.
  • Page 175 – [When output in phase with the 11th clock of SCK]
  • Page 177 – undefined value may be read during transfer.
  • Page 178 – Remark The value at 4.19 MHz is indicated in parentheses.
  • Page 180 – clock can be selected out of the following four clocks:
  • Page 186 – Notes
  • Page 187 – the master and a slave.
  • Page 188 – occurrence of a transmission error is assumed.
  • Page 193 – written to SIO beforehand for reception.; Exchanges transmit data with receive data and startstransfer; Notes on the SBI mode
  • Page 194 – SBI mode; The master can be switched to another CPU with a command.; Figure 5-71. Example of Serial Bus Configuration
  • Page 196 – The master sends ACK to the slave each time it receives one byte.; Figure 5-73. Transfer Format of the WRITE and END Commands; Figure 5-74. Transfer Format of the STOP Command; S: Output by the slave
  • Page 197 – The STATUS command reads the status of the current slave.; Figure 5-75. Transfer Format of the STATUS Command; The slave returns the status in the format shown in Figure 5-78.
  • Page 198 – Figure 5-78. Transfer Format of the CHGMST Command
  • Page 200 – Example To output one SCK/P01 pin clock cycle by software; before the instruction is executed.; Not allowed
  • Page 201 – the buffer is useful in processing long data bit by bit.; Figure 5-81. Format of the Bit Sequential Buffer; specifying BSB0 or BSB2.
  • Page 203 – CHAPTER 6 INTERRUPT AND TEST FUNCTIONS; interrupt processing.; CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT
  • Page 205 – s i m u l t a n e o u s l y g e n e r a t e d .
  • Page 208 – DI; Caution Disable interrupts before setting the IPS.
  • Page 209 – High-order interrupt selection
  • Page 210 – The edge to be detected can be selected.; The INT0 pin is supplied with sampling clock; Note When the frequency of a sampling clock is; , these cycles are equal to 2t; frequency of a sampling clock is f
  • Page 212 – Remark t
  • Page 214 – Table 6-3. Interrupt Processing Statuses of IST0 and IST1
  • Page 215 – start of interrupt are stored in each vector table.
  • Page 216 – MULTIPLE INTERRUPT PROCESSING CONTROL; double interrupt processing.
  • Page 217 – processing is enabled.
  • Page 218 – PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS; processing is started by the remaining interrupt request.; Table 6-4. Identifying Interrupt Sharing Vector Table Address; With higher priority
  • Page 220 – MACHINE CYCLES FOR STARTING INTERRUPT PROCESSING; service routine after an interrupt request flag (IRQn) is set.; cycles is executed, then the interrupt service routine is started.
  • Page 221 – D: Interrupt service routine is executed.
  • Page 222 – EFFECTIVE USE OF INTERRUPTS; PUSH BS instruction before selecting memory bank 1.; (3) Use of a software interrupt for debugging; To use the interrupt function, a main program must:
  • Page 224 – <3> Interrupts are enabled by the EI and EI IExxx instructions.; interrupts are disabled.
  • Page 225 – and all the interrupts are disabled.
  • Page 227 – start the interrupt service program for INTT0, which has been held.
  • Page 228 – priority and INTT0 and INTCSI have lower priority) –; the interrupt with the lower priority is kept pending.
  • Page 229 – is set to disable all interrupts.
  • Page 230 – Table 6-6 shows the signals which set test request flags.; Table 6-6. Signals Setting Test Request Flags
  • Page 231 – Figure 6-10 shows the configuration of INT2 and KR0 to KR7.; (a) Detection of a rising edge on the INT2 input pin; IRQ2 is set when a rising edge is detected on the INT2 input pin.
  • Page 232 – Figure 6-10. Block Diagram of the INT2 and KR0 to KR7 Circuits
  • Page 235 – CHAPTER 7 STANDBY FUNCTION; function is available in the two modes: the STOP mode and HALT mode.; the power consumption of the entire system.
  • Page 236 – as required to change the CPU clock pulse have elapsed.; Caution; STOP mode cannot be used with a system that uses an external clock.
  • Page 238 – BTM is to be set before the STOP mode is set.
  • Page 239 – instruction used to set the standby mode.; Wait time; Other than above
  • Page 242 –
  • Page 245 – CHAPTER 8 RESET FUNCTION; -1 shows the configuration of the reset circuit.; Figure 8-1. Configuration of Reset Functions; the reset operation timing.; Figure 8-2. Reset Operation by Generation of RESET Signal
  • Page 249 – CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM); ultraviolet radiation cannot be performed.
  • Page 250 – Remark X indicates L or H.
  • Page 252 – READING THE PROGRAM MEMORY; by means of resistors. Bring X1 to low level.
  • Page 253 – Storage Temperature
  • Page 255 – CHAPTER 10 MASK OPTION; The pins of the μPD750008 have the following mask options:; Table 10-1. Selecting Mask Option of Pin; Pin; The mask option can be specified in 1-bit units.; MASK OPTION OF STANDBY FUNCTION; The following two wait times can be selected:
  • Page 256 – MASK OPTION FOR FEEDBACK RESISTOR OF SUBSYSTEM CLOCK
  • Page 257 – CHAPTER 11 INSTRUCTION SET; (4) GETI instruction for reducing program sizes; UNIQUE INSTRUCTIONS; (a) Subroutine call instruction for the entire space
  • Page 259 – An overflow is set in the carry flag.; Example An accumulator is added to memory data in decimal.; subtraction to number system m.
  • Page 261 – For immediate data, a proper numeric value or label must be coded.
  • Page 263 – 0 indicates an addressable area.
  • Page 264 – (4) Explanation of the machine cycle column; a skip operation. S assumes one of the following values:; Caution The GETI instruction is skipped in one machine cycle.; One machine cycle is equal to one cycle (t
  • Page 265 – Transfer
  • Page 266 – MOVT; ADDS; Table reference
  • Page 267 – Comparison; Carry flag
  • Page 268 – Memory bit manipulation
  • Page 269 – Branch; BR; Note The shaded portion is supported in Mk II mode only.
  • Page 271 – CALLA; Note 1. The shaded portion is supported in Mk II mode only.
  • Page 272 – CALL; CALLF; Subroutine stack control
  • Page 273 – RET
  • Page 274 – RETS; RETI
  • Page 275 – supported in Mk I mode only.
  • Page 276 – Special
  • Page 277 – GETI
  • Page 278 – : Immediate data for n4 or n8
  • Page 279 – The table below lists the second byte
  • Page 284 – FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONS; in Mk II mode. Read the following explanation.; How to read; II; Examples 1. The data 0BH is set in the accumulator.; Data to be output to port 3 is selected from 0 to 2.
  • Page 285 – are processed as NOP instructions.
  • Page 287 – and transfers the data at the next address to the X register.
  • Page 289 – bit immediate data mem.
  • Page 290 – ) exchanged with the contents of the DE register pair.
  • Page 294 – Example The register pair is left-shifted.
  • Page 295 – instruction is skipped.; Example Data memory is compared with register pair rp’.
  • Page 296 – Example The high-order two bits of an accumulator are set to 0.
  • Page 297 – Example The low-order three bits of an accumulator are set to 1.; pair, then sets the result in the A register.
  • Page 298 – pair, then sets the result in register pair rp’1.; Example The high-order four bits of an accumulator is inverted.; HL register pair, then sets the result in the A register.
  • Page 300 – register pair match the 4-bit immediate data n4.
  • Page 301 – Clears the carry flag.; SKT CY
  • Page 303 – specified by the 8-bit immediate data mem is 1.
  • Page 304 – BR addr; Branches to the address specified by the immediate data addr.
  • Page 305 – Branches to the address specified by the immediate data addr1.
  • Page 306 – block 1 instead of block 0 occurs.
  • Page 307 – a branch to the next page instead of that page occurs.
  • Page 308 – BR BCDE; BR BCXA; of the B; TBR addr
  • Page 313 – The low-order part of a register pair (rp
  • Page 314 – DI IExxx; contents of the next port to the X register.; A number from 2 to 8 can be specified as n.
  • Page 320 – SOS register
  • Page 321 – APPENDIX B DEVELOPMENT TOOLS
  • Page 322 – PROM programming tools
  • Page 323 – Debugging Tools; The following system is shown below.; Notes 1. Maintenance service only; Hardware; OS
  • Page 324 – OS for IBM PC; The following IBM PC OSs are supported.; O S; IBM DOS; Only English version is supported.
  • Page 325 – Development Tool Configuration
  • Page 329 – APPENDIX C MASKED ROM ORDERING PROCEDURE; <1> Advance notice of an order for masked ROM
  • Page 331 – APPENDIX D INSTRUCTION INDEX
  • Page 337 – APPENDIX E HARDWARE INDEX; Pull-up resistor specification register
  • Page 341 – APPENDIX F REVISION HISTORY
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µPD750008

4 BIT SINGLE-CHIP MICROCOMPUTER

©

1995

USER'S MANUAL

µPD750004
µPD750006
µPD750008

µPD75P0016

Document No. U10740EJ2V0UM00 (2nd edition)
(Previous No. IEU-1421)
Date Published April 1996 P
Printed in Japan

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Summary

Page 3 - support systems or medical equipment for life support, etc.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibitedwithout governmental license, the need for which must be judged by the customer. The export or re-export of this productfrom a country other than Japan may also be prohibited withou...

Page 4 - Major Changes; Chapter 10 has been added.; The mark

Major Changes Page Description All The 44-pin plastic QFP package has been changed from µPD750008GB-xxx-3B4to µPD750008GB-xxx-3BS-MTX. The µPD75P0016 under development has been changed to the already-developedµPD75P0016. The input withstand voltage at ports 4 and 5 during open drain has been changed...

Page 5 - PREFACE; Readers

PREFACE Readers This manual is intended for engineers who want to learn the capabilities of the µPD750004, µPD750006, µPD750008, and µPD75P0016 to develop application systems based on them. Purpose The purpose of this manual is to help users understand the hardware capabilities (shown below) of the ...

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