NEC PD17062 - Manual

7 µ PD17062 8.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP) ...................... 57 8.6 GENERAL-PURPOSE REGISTER POINTER (RP) .......................................................................... 66 8.7 PROGRAM STATUS WORD (PSWORD) ...............................................

8 µ PD17062 11.5 RETURNING CONTROL FROM INTERRUPT PROCESSING ROUTINE ..................................... 116 11.6 INTERRUPT PROCESSING ROUTINE ........................................................................................... 117 11.7 EXTERNAL INTERRUPTS (INT NC PIN, V SYNC PIN) ............

14 µ PD17062 1.2 EQUIVALENT CIRCUITS OF THE PINS P0A (P0A 3 /SO, P0A 2 /SCK) P0B (P0B 1 , P0B 0 /SI) P1B (P1B 3 , P1B 2 , P1B 1 , P1B 0 ) P1C (P1C 3 /ADC 1 , P1C 2 , P1C 1 ) V DD V DD A/D converter (only for P1C/ADC) RESET signal (except for P1C)Read instruction (only for P1C) P0A (P0A 1 /SCL, P0A 0...

15 µ PD17062 P0C (P0C 3 , P0C 2 , P0C 1 , P0C 0 ) RED, GREEN, BLUE, BLANK, PSC (Output) PWM (PWM 3 , PWM 2 , PWM 1 , PWM 0 ) P1A (P1A 3 , P1A 2 , P1A 1 , P1A 0 ) (Output) P0D (P0D 3 /ADC 5 , P0D 2 /ADC 4 , P0D 1 /ADC 3 , P0D 0 /ADC 2 ) A/D Converter High on-state resistance (Input) ADC 0 A/D convert...

17 µ PD17062 H SYNC , V SYNC , INT NC , CE (Hysteresis input) X OUT , X IN X IN X OUT EO VCO (Input)

18 µ PD17062 2. PROGRAM MEMORY (ROM) Program memory stores the program to be executed by the CPU, as well as predetermined constant data. 2.1 CONFIGURATION OF PROGRAM MEMORY Fig. 2-1 shows the configuration of program memory. As shown in Fig. 2-1, the capacity of the program memory is 8K bytes (3968...

19 µ PD17062 2.2 FUNCTIONS OF PROGRAM MEMORY Program memory has two basic functions: (1) Program storage (2) Constant data storage A program is a set of instructions that control the CPU (Central Processing Unit: Device that actually controls the microcontroller). The CPU executes processing sequent...

20 µ PD17062 2.4 BRANCHING A PROGRAM A program is branched by execution of the branch instruction (BR). Fig. 2-2 illustrates the operation of the branch instruction. Branch instructions (BR) are divided into two types. Direct branch instructions (BR addr) transfer control to a program memory address...

21 µ PD17062 Fig. 2-2 Operation of Branch Instruction and Machine Code (a) Direct branch (BR addr) (b) Indirect branch (BR @AR) Address Program memory Label: Instruction (Machine code) Page 0 Page 1 0 0 0 0 H 0 5 0 0 H0 7 F F H 0 8 0 0 H 0 9 0 0 H 0 F 7 F H BR AAA (0C500) BR BBB (0D100) AAA: BBB: BR...

22 µ PD17062 2.5 SUBROUTINE If a subroutine is executed, the specialized subroutine call instruction (CALL) and subroutine return instruction (RET, RETSK) are used. Fig. 2-3 illustrates the operation of subroutine call. Subroutine call instructions are divided into two types. The direct subroutine c...

23 µ PD17062 Fig. 2-3 Operation of Subroutine Call Instruction (a) Direct subroutine call (CALL addr) (b) Indirect subroutine call (CALL @AR) Address Program memory Instruction CALL SUB1 Page 0 Page 1 0 0 0 0 H 0 7 F F H 0 8 0 0 H 0 F 7 F H CALL SUB1 Address Program memory Instruction Page 0 Page 1 ...

24 µ PD17062 2.6 TABLE REFERENCE The table reference instruction is used to reference the constant data in program memory. If the MOVT DBF, @AR instruction is executed, data at the program memory address specified in an address register is placed in a data buffer (DBF). Because each data item in pro...

25 µ PD17062 3. PROGRAM COUNTER (PC) The program counter addresses program memory or a program. It is a 12-bit binary counter. Fig. 3-1 Program Counter PC 11 PC 9 PC 10 PC 8 PC 6 PC 7 PC 5 PC 3 PC 4 PC 2 PC 0 PC 1 12 bits Priority Interrupt cause Vector address 1 INT NC pin 4H 2 Internal timer 3H 3 ...

26 µ PD17062 4. STACK The stack is a register used to save an address returned by a program or the contents of the system register, described later, when a subroutine call occurs or an interrupt is accepted. 4.1 COMPONENTS The stack consists of a stack pointer (SP), which is a 4-bit binary counter, ...

27 µ PD17062 4.3 ADDRESS STACK REGISTERS (ASRs) There are six address stack registers, each consisting of 13 bits. After a subroutine call instruction has been executed or an interrupt request accepted, the contents of the address stack register will contain a value that is equal to the contents of ...

29 µ PD17062 5. DATA MEMORY (RAM) Data memory is used to store data for operations and control. Simply by executing an appropriate instruction, data can be written to and read from data memory at any time. 5.1 STRUCTURE OF DATA MEMORY Fig. 5-1 shows the structure of data memory. As shown in Fig. 5-1...

30 µ PD17062 Fig. 5-1 Data Memory Structure 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 DBF3 DBF2 DBF1 DBF0 P0A (4 bits) System register P0B (4 bits) P0C (4 bits) P0D (4 bits) BANK0 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 P1A (4 bits) System register P1B (4 bits) P1C (4 bits) Fixed at 0 ...

31 µ PD17062 5.1.1 Structure of the System Register (SYSREG) The system register consists of 12 nibbles, located at addresses 74H to 7FH in data memory. The system register is allocated regardless of the bank. That is, the system register is always located at addresses 74H to 7FH, regardless of the ...

33 µ PD17062 5.1.4 Structure of Port Data Registers (port register) The port registers consist of 12 nibbles at addresses 70H to 73H of the banks of data memory. Fig. 5-5 shows the structure of the port registers. As shown in Fig. 5-5, the same port registers are allocated in BANK0 and BANK2. Thus, ...

36 µ PD17062 Table 5-1 Data Memory Manipulation Instructions Function Instruction ADD ADDC SUB SUBC AND OR XOR SKE SKGE SKLT SKNE MOV LD ST SKT SKF Addition Subtraction Logical operation Operation Comparison Transfer Decision

38 µ PD17062 5.3 NOTES ON USING DATA MEMORY 5.3.1 Addressing Data Memory If the 17K series assembler is being used and a numeric representing a data memory address is specified directly in an operand of a data memory manipulation instruction, as shown in example 1, an error will occur. This error oc...

39 µ PD17062 Example 2. 5.3.2 Notes on Using Unmounted Data Memory As shown in Fig. 5-6, nothing is actually assigned to bit 0 (LSB) of address 72H of BANK1 of the port registers. If a data memory manipulation instruction is executed for this address, the following operations are performed: (1) Devi...

40 µ PD17062 6. GENERAL-PURPOSE REGISTER (GR) The general-purpose register is allocated in data memory space, and is used to perform direct operations on the data in data memory and to transfer data to and from data memory. 6.1 STRUCTURE OF THE GENERAL-PURPOSE REGISTER Fig. 6-1 shows the structure o...

41 µ PD17062 Fig. 6-1 Structure of General-Purpose Register RPH RPL 7DH 7EH b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 0 0 0 0 b 2 b 1 b 0 BC D (RP) 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 2 3 4 5 6 7 1 0 2 3 4 5 6 7 1 0 2 3 4 5 6 7 1 Column address Row addresses 0H to 7H of BANK0 can be freely specified using the g...

42 µ PD17062 6.3 ADDRESS GENERATION FOR GENERAL-PURPOSE REGISTER AND DATA MEMORY IN INDIVIDUAL INSTRUCTIONS Table 6-1 lists the operation and transfer instructions that can be executed for the data in the general- purpose register and data memory. Consider the following instruction: ADD r, m ((r) ← ...

43 µ PD17062 Example 1. When BANK0 is selected AND RPL, #0001B ; RP ← 0000000B; The general-purpose register is allocated in row ; address 0H in BANK0. ADD 04H, 56H ; Executing the above instruction adds the contents of address 04H of BANK0, part of the general-purpose register, to the contents of d...

44 µ PD17062 Example 2. When BANK0 is selected and MPE = 0 is specified MOV 04H, #8 ; 04H ← 8 AND RPL, #0001B ; RP ← 0000000B; The general-purpose register is allocated in row ; address 0H in BANK0. MOV @04H, 52H Executing the above instruction transfers the contents of data memory address 52H to ad...

45 µ PD17062 Example 3 shows a program that transfers eight words of data from BANK2 to BANK0 data memory in units of four words, as shown in Fig. 6-4. If the general-purpose register is allocated in a fixed row address, for example, only in row address 0 of BANK0, instructions are needed to transfe...

47 µ PD17062 Fig. 6-5 Execution of the Above Example Also, note the following when the general-purpose register is being used. No arithmetic/logical instructions are provided for the general-purpose register and immediate data. That is, the execution of an arithmetic/ logical instruction that involv...

49 µ PD17062 7.2 CONFIGURATION AND FUNCTIONS OF THE COMPONENTS OF THE ALU BLOCK 7.2.1 ALU In response to a programmed instruction, the ALU performs 4-bit arithmetic or logic processing, bit discrimination, comparative discrimination, rotation, or transfer. 7.2.2 Temporary Storage Registers A and B T...

50 µ PD17062 Table 7-1 ALU Operations ALU function Addition Subtraction Logic operation Discrimi- nation Comparison Transfer Rotation ADD ADDC SUB SUBC OR AND XOR SKT SKF SKE SKNE SKGE SKLT LD ST MOV RORC r r, m m, #n4 r, m m, #n4 r, m m, #n4 r, m m, #n4 r, m m, #n4 r, m m, #n4 r, m m, #n4 m, #n m, ...

51 µ PD17062 Table 7-2 Modification of the Data Memory Address and Indirect Transfer Address by the Index Register and Data Memory Row Address Pointer BANK : Bank register IX : Index register IXE : Index enable flag IXH : Bits 10 to 8 of the index register IXM : Bits 7 to 4 of the index register IXL...

52 µ PD17062 Table 7-3 Converted Decimal Data Remark Correct decimal conversion is not possible in the shaded area. Operation result Hexadecimal addi- tion 0 0 0000B 0 0000B 1 0 0001B 0 0001B 2 0 0010B 0 0010B 3 0 0011B 0 0011B 4 0 0100B 0 0100B 5 0 0101B 0 0101B 6 0 0110B 0 0110B 7 0 0111B 0 0111B ...

53 µ PD17062 7.4 NOTES ON USING THE ALU 7.4.1 Notes on Using the Program Status Word for Operations After an arithmetic operation has been performed on the program status word, the operation result is held in the program status word. The CY and Z flags of the program status word are usually set or r...

54 µ PD17062 8. SYSTEM REGISTER (SYSREG) “System register” is the generic name for those registers directly related to CPU control. System registers are allocated at addresses 74H-7FH in data memory and can be referenced regardless of the bank specification. The system register types are as follows:...

55 µ PD17062 b 3 0 b 2 0 b 1 0 b 0 0 b 3 0 b 2 0 b 1 0 b 0 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 AR 15 (MSB) AR 0 (LSB) AR0 (77H) AR1 (76H) AR2 (75H) AR3 (74H) 8.1 ADDRESS REGISTER (AR) The address register specifies a program memory address. It is located at addresses 74H-77H. The instructions used to ...

56 µ PD17062 8.3 BANK REGISTER (BANK) The bank register specifies a data memory bank. The bank register contains BANK0 upon reset. The two high-order bits of address 79H are consistently set to 0. Data memory is classified into three banks by the bank register. When a data memory manipulation instru...

61 µ PD17062 Fig. 8-3 Indirect Transfer of General-Purpose Register with MPE = 0 and IXE = 0 Address generation of example 2 R M 0 0 0 0 3 3 5 4 8 (@ r) @ r, m MOV 05H 34H 0 1 2 3 4 5 6 7 8 9 A B C D E F 8 E 0 1 2 3 4 5 6 7 Column address Row address Example 1. ADD03H,11H Specifies the destination c...

63 µ PD17062 Fig. 8-4 Indirect Transfer of General-Purpose Register with MPE = 1 and IXE = 0 Address generation of example 1 R M 0 0 0 0 0 0 0 3 1 0 1 5 4 8 (@ r) @ r, m MOV 05H 34H 0 1 2 3 4 5 6 7 8 9 A B C D E F 8 E 0 1 2 3 4 5 6 7 MP = 00101B Column address Specifies the destination column addres...

65 µ PD17062 Fig. 8-5 Data Memory Address Modification with IXE = 1 0 1 2 3 4 5 6 R 0 1 2 3 4 M ADD r, m Column address Row address General-purposeregister Specified by IX

76 µ PD17062 9.3 CE (07H, b 0 ) CE is a flag for reading the CE pin level. The flag indicates 1 when a high level signal is input to the CE pin, or 0 when a low level signal is input. 9.4 SERIAL INTERFACE MODE REGISTER (08H) b 3 b 2 b 1 b 0 0 0 CE 07H 0 1 0 CE pin low level CE pin high level b 3 b 2...

77 µ PD17062 b 3 b 2 b 1 b 0 BTM0ZX BTM0CK2 BTM0CK0 09H BTM0CK1 0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 TIMER INT TIMER CARRY 5 ms 100 ms 20 ms 20 ms 5 ms 5/f TMR s 5 ms 6/f TMR s 100 ms 5 ms 100 ms 5 ms 5/f TMR s 5 ms 6/f TMR s 5 ms Time base setting Internal Internal Internal Internal ...

78 µ PD17062 9.7 INTNC (0FH, b 0 ) The INT NC flag is used for reading the INT NC pin state. The flag indicates 1 when a high level signal is input to the INT NC pin, and 0 when a low level signal is input to the INT NC pin. 9.8 HORIZONTAL SYNCHRONIZING SIGNAL COUNTER CONTROL (11H, 12H) b 3 b 2 b 1 ...

79 µ PD17062 9.9 PLL REFERENCE MODE SELECTION REGISTER (13H) 9.10 SETTING OF INT NC PIN ACCEPTANCE PULSE WIDTH (15H) b 3 b 2 b 1 b 0 PLLRFCK3 PLLRFCK2 PLLRFCK0 13H PLLRFCK1 0 0 1 0 0 0 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 0 1 0 1 0 1 1 1 1 1 0 6.25 kHz 12.5 kHz 25 kHz PLL disabled Not to be set Reference f...

80 µ PD17062 9.11 TIMER CARRY (17H) 9.12 SERIAL INTERFACE WAIT CONTROL (18H) 9.13 IEGNC (1FH) The IEGNC flag is used for selecting the interrupt detection edge of the INT NC pin and V SYNC pin. When the flag is set to 0, an interrupt occurs at a rising edge. When the flag is set to 1, an interrupt o...

83 µ PD17062 9.18 INTERRUPT PERMISSION FLAG (2FH) This flag is used to enable interrupt for each interrupt cause. When the flag is set to 1, interrupt is enabled. When the flag is set to 0, interrupt is disabled. 9.19 CROM BANK SELECTION (30H) b 3 b 2 b 1 b 0 IPSIO0 IPVSYN IPNC 2FH 0 1 IPBTM0 0 1 0 ...

86 µ PD17062 9.24 P0ABIOn (37H) P0ABIOn specifies the PORT0A I/O. When P0ABIOn is set to 0, PORT0A becomes an input port. When P0ABIOn is set to 1, PORT0A becomes an output port. 9.25 SETTING OF INTERRUPT REQUEST GENERATION TIMING IN SERIAL INTERFACE MODE (38H) b 3 b 2 b 1 b 0 P0ABIO3 P0ABIO2 P0ABIO...

87 µ PD17062 9.26 SHIFT CLOCK FREQUENCY SETTING (39H) 9.27 IRQNC (3FH) IRQNC is an interrupt request flag that indicates the interrupt request state. When an interrupt request is generated, the flag is set to 1. When the request is accepted (interrupt is made), the flag is reset to 0. The interrupt ...

88 µ PD17062 10. DATA BUFFER (DBF) The data buffer is used to transfer data to and from peripheral hardware and to reference tables. 10.1 DATA BUFFER STRUCTURE 10.1.1 Mapping of Data Buffer to Data Memory Fig. 10-1 shows how the data buffer is mapped to data memory. As shown in Fig. 10-1, the data b...

90 µ PD17062 10.2 FUNCTIONS OF DATA BUFFER The data buffer provides the following two functions: (1) Read constant data in program memory (to reference tables) (2) Transfer data to and from peripheral hardware Fig. 10-3 shows the relationship between the data buffer, peripheral hardware, and memory....

91 µ PD17062 10.3 DATA BUFFER AND TABLE REFERENCING 10.3.1 Table Referencing Tables are referenced by reading the constant data from program memory into the data buffer. This is done using the MOVT DBF, @AR instruction. Therefore, if display data or other constant data is written to program memory i...

94 µ PD17062 Table 10-1 Peripheral Hardware and Data Buffer Functions Data buffer and data transfer Function peripheral register Peripheral hardware Name Symbol Peri- PUT Data Valid Explanation pheral instruction/ buffer bits address GET I/O bits instruction Image display IDC start posi- IDCORG 01H ...

95 µ PD17062 10.4.2 Precautions When Transferring Data With Peripheral Registers Data is transferred between the data buffer and peripheral registers in 8-bit or 16-bit units. A PUT or GET instruction is executed for one instruction cycle (2 µ s) even if the data is 16 bits long. When 8-bit data tra...

96 µ PD17062 Example 2. GET instruction When the 8-bit data of a peripheral register is read, the value of the eight high-order bits (DBF3 and DBF2) of the data register does not change. Of the 8-bit data of the data register, each bit that is not a valid peripheral register bit becomes 0 or unpredi...

97 µ PD17062 10.5 Data Buffer and Peripheral Registers Sections 10.5.1 to 10.5.7 describe the data buffer and the peripheral registers. 10.5.1 IDC Start Position Setting Register Fig. 10-4 shows the functions of the IDC start position setting register. The IDC start position setting register sets th...

100 µ PD17062 10.5.4 HSYNC Counter Data Register Fig. 10.7 shows how the HSYNC counter data register functions . The HSYNC counter data register reads the horizontal synchronizing signal count. When the HSYNC counter data register reaches 3FH, it returns to 00H at the next input. Fig. 10-7 HSYNC Dat...

102 µ PD17062 10.5.6 Address Registers The address registers are mapped to addresses 74H to 77H in the system register (at data memory addresses 74H to 7FH). They are used for program memory address operations. See Chapter 8 . The address registers can be used to manipulate data directly with data m...

103 µ PD17062 10.5.7 PLL Data Register Fig. 10-10 shows how the PLL data register functions. The PLL data register sets the frequency division ratio of the PLL frequency synthesizer. For the pulse swallow method, all 16 bits are valid, the 12 high-order bits are set in the program counter, and the r...

104 µ PD17062 10.6 PRECAUTIONS WHEN USING DATA BUFFERS 10.6.1 Write Only, Read Only, and Unused Address Data Buffer Precautions When the 17K series assembler and emulator are used for data transfer with peripheral hardware via the data buffer, note the following regarding unused peripheral addresses...

105 µ PD17062 10.6.2 Peripheral Register Addresses and Reserved Words When a 17K series assembler is used, no error is generated when peripheral address “p” is specified directly (with a numerical value) in PUT p, DBF or GET DBF, p as shown in Example 1. However, to reduce program bugs, this method ...

106 µ PD17062 11. INTERRUPT An interrupt temporarily stops the program being executed in response to a request from the peripheral hardware (INT NC pin, timer, V SYNC pin or serial interface). The interrupt then branches the program flow to a predetermined address (vector address). 11.1 INTERRUPT BL...

107 µ PD17062 Fig. 11-1 Interrupt Block Configuration 3FH 2FH b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 I R Q S I O 0 I R Q VSY N I R Q B T M 0 I R QN C I PS I O 0 I RVSYN I PBT M 0 I P NC 01H b 3 b 2 b 1 b 0 0 SP2 SP1 SP0 BANK PSW b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 79H 7FH 0 0 C M P CY Z I XE System register Sy...

109 µ PD17062 11.2.4 Interrupt Permission Flags (IP ××× ) The interrupt permission flags set interrupt permissions for various types of peripheral hardware. If these flags are set to 1 and the corresponding interrupt request flags are also set, the corresponding interrupt requests are output. Becaus...

110 µ PD17062 11.2.6 Interrupt Enable Flip-Flop (INTE) The interrupt enable flip-flop sets the interrupt permissions of all four types of interrupts. If each interrupt request processing block outputs a 1 while this flip-flop is set to 1, a 1 is output from this flip-flop and an interrupt is accepte...

112 µ PD17062 Fig. 11-2 Interrupt Acceptance Flowchart START INT NC pin Timer V SYNC pin Serial interface IPNC=1? IPBTM0=1? IPVSYN=1? IPSIO0=1? No Yes No Yes No Yes No yes Yes No Yes No Yes No IRQNC= IPNC=1? IRQBTM0= IPBTM0=1? IRQVSYN= IPVSYN=1? IRQSIO0= IPSIO0=1 # $ No Yes Interruptrequest? No Yes ...

113 µ PD17062 11.3.2 Timing Chart at Interrupt Acceptance Fig. 11-3 shows the timing chart at interrupt acceptance. Fig. 11-3 (1) shows the timing chart of one interrupt. The timing chart when an interrupt request flag is set to 1 is shown in (a) of (1). The timing chart when an interrupt permission...

114 µ PD17062 Fig. 11-3 Interrupt Reception Timing Chart (1/2) (1) When one interrupt (e.g., rising edge at the INT NC pin) is used (a) When an interrupt mask time is not set by the interrupt permission flag # # When the MOVT instruction or a normal instruction that does not satisfy the skip conditi...

115 µ PD17062 Fig. 11-3 Interrupt Acceptance Timing Chart (2) When two or more interrupts (e.g., rising edge at the INT NC pin and falling edge at the V SYNC pin) are used (a) Hardware priorities (b) Software priorities Instruction EI MOV WR, #0101B POKE INTPM, WR INTE INT NC pin IRQVSYN flag IPNC f...

117 µ PD17062 11.6 INTERRUPT PROCESSING ROUTINE An interrupt is accepted in a program area that permits interrupts regardless of the program being executed. Therefore, to return control to the original program after interrupt processing, return the program to the state it is in when it is not proces...

118 µ PD17062 11.6.3 Notes on Interrupt Processing Routine Note the following regarding the interrupt processing routine: (1) Data saved by hardware All bank registers and index enable flags are reset to 0 after being saved in the interrupt stack. (2) Data saved by software Data saved by software is...

119 µ PD17062 Example Saving the status in an interrupt processing routine EI M046 M047 M048 M04D M04E M05F BTM0CK MEM MEM MEM MEM MEM MEM MEM 0.46H 0.47H 0.48H 0.4DH 0.4EH 0.5FH 0.89H # POKE $ PEEK % POKE & MOV ( ST ) ST M048, WR, M04E, RPL, M046, M047, WR RPL WR #0EH AR1 AR0 . . . * PEEK + ST ...

121 µ PD17062 11.7 EXTERNAL INTERRUPTS (INT NC PIN, V SYNC PIN) There are two external interrupt sources: INT NC and V SYNC . An interrupt request is issued when a rising or falling edge is input to the INT NC or V SYNC pin. 11.7.1 Configuration Fig. 11-5 shows the configurations of the INT NC and V...

123 µ PD17062 IEGNC or IEGVSYN flag change INT NC or V SYNC pin Whether interrupt IRQNC flag request is issued 1 → 0 Low Not issued No change (Fall) (Rise) High Issued Set 1 → 0 Low Issued Set (Rise) (Fall) High Not issued No change Table 11-3 Interrupt Request Issuance by IEGNC Flag Change 11.8 INT...

124 µ PD17062 11.9 MULTIPLE INTERRUPTS The multiple interrupt function is used to process interrupt C or D while another interrupt from source A or B is being processed as shown in Fig. 11-6. The interrupt depth at this time is called the interrupt level. Note the following regarding the multiple in...

125 µ PD17062 11.9.1 Interrupt Source Priorities When using the multiple interrupt function, the priorities of interrupt sources must be determined. For example, if the interrupt sources are A, B, C, and D, the following priorities can be specified: A = B = C = D or A < B < C < D. If A = B ...

127 µ PD17062 Fig. 11-7 Interrupt Stack Operation at Multiple Interrupts (a) Multiple level-2 interrupts (b) Multiple level-3 interrupts MAIN A MAIN B A MAIN RETI RETI A MAIN MAIN MAIN MAIN MAIN Interrupt B Interrupt stack Undefined Main routine Interrupt A Interrupt stack Undefined Undefined MAIN A...

128 µ PD17062 MAIN A MAIN B A C B A MAIN B A A A RETI RETI RET A A A A BANK0CLR1 IXE DI BANK0 CLR1 IXE EI Undefined Undefined Main routine Interrupt A Interrupt B Interrupt C Undefined Fig. 11-8 Example of Using Multiple Level-3 Interrupts To interrupt A, be sure to set a lower priority than interru...

129 µ PD17062 Fig. 11-9 Interrupt Stack Operation when 17K Series Emulator is Used If the RETI instruction is used on the emulator, the contents of the bank register and index enable flag of interrupt B are restored. MAIN MAIN A B A C B A MAIN B B B B RETI RETI RET A A A A Undefined Undefined Main r...

130 µ PD17062 11.9.3 Interrupt Level Restriction by Address Stack Register The return address at control return from interrupt processing is automatically saved in the address stack register. The address stack register can use the six levels from ASR0 to ASR5 as described in Chapter 4 . Because the ...

131 µ PD17062 11.9.4 Saving the Contents of System and Control Registers The contents of system and control registers must be saved before using the multiple interrupt function. The contents of these registers change during interrupt processing. An area must be obtained for these contents for each i...

134 µ PD17062 12.2 TIMER FUNCTIONS There are two timer functions, timer carry FF check and timer interrupt. The timer carry FF check function performs time management by checking, by program, the state of the timer carry FF, which is set at constant intervals. The timer interrupt function performs t...

136 µ PD17062 12.3 TIMER CARRY FLIP-FLOP (TIMER CARRY FF) The timer carry FF is set to 1 by the positive-going edge of the timer carry FF set pulse specified by the timer mode select register. The content of the timer carry FF corresponds to the lowest bit (BTM0CY flag) of the timer carry FF judge r...

137 µ PD17062 12.3.1 Example of Using the Timer Based on the BTM0CY Flag An example of a program follows. Example INITFLG NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, NOT BTM0CK0 ; Built-in macro ; Specifies that the timer carry FF be set at intervals of 100 ms. LOOP1: MOV M1, #0110B LOOP2: SKT1 BTM0CY ; B...

139 µ PD17062 (2) Timer error that occurs when the timer carry FF setting time interval is changed The timer carry FF setting time interval is specified by the BTM0CK2, BTM0CK1, and BTM0CK0 flags in the timer mode select register. As shown in Fig. 12-1 and 12-2, the timer interval set pulse can be s...

141 µ PD17062 12.4 CAUTIONS IN USING THE TIMER CARRY FF The timer carry FF is used not only as a timer function but also as a reset sync signal at a CE reset. A CE rest occurs when the timer carry FF set pulse rises after the CE pin goes from a low to a high. Note the following points: (1) The sum o...

152 µ PD17062 In reality, however, to avoid skipping the timer process in the above example, a delay is provided between the negative-going edge of the timer carry FF set pulse and the negative-going edge of the timer interrupt pulse, as shown in Fig. 12-10 (b). As shown at (2) in Fig. 12-10, restri...

153 µ PD17062 13. STANDBY The standby function is intended to reduce the current drain of the device at backup. 13.1 STANDBY BLOCK CONFIGURATION Fig. 13-1 shows the configuration of the standby block. As shown in Fig. 13-1, the standby block is further divided into halt control and clock stop contro...

155 µ PD17062 13.3 DEVICE OPERATION MODE SPECIFIED AT THE CE PIN The CE pin controls the following items according to the level and positive-going edge of its input signal. (1) Whether to enable or disable the clock stop instruction (2) Whether to reset the device Sections 13.3.1 and 13.3.2 explain ...

159 µ PD17062 (2) Cautions in using the P0D 0 /ADC 2 to P0D 3 /ADC 5 pins for an A/D converter P0D 3 /ADC 5 P0D 2 /ADC 4 P0D 1 /ADC 3 P0D 0 /ADC 2 A/D input A/D input Latch General-purpose port If one of the P0D 0 /ADC 2 to P0D 3 /ADC 5 pins is selected for an A/D converter (only one pin can be sele...

160 µ PD17062 (3) Alternative method to release the halt state P0D 3 /ADC 5 P0D 2 /ADC 4 P0D 1 /ADC 3 P0D 0 /ADC 2 Output port Latch Microprocessor or the like General-purpose output port The P0D 0 /ADC 2 to P0D 3 /ADC 5 pins can be used a general-purpose input port with a built-in pull-down resisto...

162 µ PD17062 13.4.5 Releasing the Halt State by an Interrupt The HALT 1000B instruction specifies an interrupt as halt release condition. If it is specified that the halt state is to be released according to an interrupt, the halt state is released immediately when an interrupt request is accepted....

164 µ PD17062 13.5 CLOCK STOP FUNCTION The clock stop function stops the operation of the 8 MHz crystal oscillator by executing the STOP s instruction. The clock stop function can reduce the current drain of the µ PD17062 by 10 µ A (maximum). The operand s of the STOP s instruction is 0000B. This in...

166 µ PD17062 13.5.3 Cautions in Using the Clock Stop Instruction The clock stop instruction (STOP s) is effective only when the CE pin is at a low level. To enable the clock stop state to be released, the program must therefore have a provision to handle when the CE pin happens to be at a high. Suc...

169 µ PD17062 13.6.2 Cautions in Processing of Each Pin During Halt or Clock Stop State The halt function is intended to reduce the required current drain, for example, by allowing only the clock to operate. Meanwhile, the clock stop function is intended to reduce the required current drain by suspe...

171 µ PD17062 14. RESET The reset function is used to initialize device operation. 14.1 RESET BLOCK CONFIGURATION Fig. 14-1 shows the configuration of the reset block. Device reset is divided into reset by turning on V DD (power-on reset or V DD reset), and reset by CE pin (CE reset). The power-on r...

172 µ PD17062 14.2 RESET FUNCTION Power-on reset is applied when V DD rises from a certain voltage, CE reset is applied when the CE pin rises from low level to high level. Power-on reset initializes the program counter, stack, system register and control registers, and executes the program from addr...

173 µ PD17062 14.3 CE RESET CE reset is executed by raising the CE pin from low level to high level. When the CE pin rises to high level, the RESET signal is output and the device is reset in synchronization with the rising edge of the pulse used for the next setting of the timer carry FF. When CE r...

175 µ PD17062 14.3.3 Cautions at CE Reset When CE reset is used, careful attention must be given to points (1) and (2) below regardless of the instruction being executed. (1) Time required for clock and other timer processing When writing a clock program by using timer carry FF and timer interrupts,...

178 µ PD17062 14.4.1 Power-on Reset at Normal Operation Fig. 14-5 (a) shows power-on reset at normal operation. As shown in Fig. 14-5 (a), when the V DD drops below 3.5 V, the power-on clear signal is output and operation of the device stops regardless of the input level of the CE pin. When V DD the...

179 µ PD17062 Fig. 14-5 Power-on Reset and V DD (a) During normal operation (including halt state) (b) At clock-stop (c) When V DD rises from 0 V 5 V 0 V “H” Normal operation Device operation stopped X OUT V DD CE Power-on clear signal Power-on clear releaseOscillation start Power-on resetProgram st...

180 µ PD17062 14.5 RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESET When supply voltage is first turned on, power-on reset and CE reset may be applied simultaneously. Sections 14.5.1 through 14.5.3 describe this reset operation. Section 14.5.4 describes the cautions when supply voltage rises. 14.5.1...

181 µ PD17062 Fig. 14-6 Relationship Between Power-on Reset and CE Reset (a) When V DD and CE pin raised simultaneously (b) When CE pin raised in halt state (c) When CE pin raised after power-on reset 5 V 0 V Opera- tion stopped V DD CE Power-on resetProgram start Power-on clear voltage 3.5 V Halt s...

182 µ PD17062 14.5.4 Cautions When Supply Voltage Raised When supply voltage is raised, careful attention must be given to points (1) and (2) below. (1) When V DD raised from power-on clear voltage When V DD is raised, it must be raised to 3.5 V or greater, once. This is shown in Fig. 14-7. As shown...

183 µ PD17062 (2) At return from clock-stop state When returning from the back-up state when clock-stop is used to back-up supply voltage at 2.2 V, V DD must be raised to 3.5 V or greater within 50 ms after the CE pin becomes high level. As shown in Fig. 14-8, return from the clock-stop state is per...

184 µ PD17062 14.6 POWER FAILURE DETECTION Power failure detection is used to judge whether the device is reset by turning on V DD or by the CE pin, as shown in Fig. 14-9. Since the contents of the data memory, output ports, etc. become “undefined” when V DD is turned on, they are initialized by pow...

185 µ PD17062 Fig. 14-10 BTM0CY Flag State Transition # $ V DD = L → 3.5 V CE = L CE = H ( & ) * + , - . 0 / 1 2 3 4 CE = H → L STOP 0 BTM0CY = 0 CE = L → H CE = L → H CE = H → L CE = L → H CE = L → H STOP 0 BTM0CY = 1 CE = low CE = optional CE = high V DD = low Operation stopped Clock oscillati...

186 µ PD17062 Fig. 14-11 BTM0CY Flag Operation (a) When BTM0CY flag not detected even once (neither SKT1 BTM0CY nor SKF1 BTM0CY executed) (b) When power failure detected with BTM0CY flag 5 V 0 V V DD CE Timer carry FF set pulse BTM0CY Fig. 14-12 operation Timer time switching STOP 0000B # $ ) ( + ) ...

187 µ PD17062 14.6.2 Cautions at Power Failure Detection with BTM0CY Flag When clock counting, etc. is performed with the BTM0CY flag, careful attention must be given to the following points. (1) Clock updating When writing a clock program by using the timer carry FF, the clock must be updated after...

189 µ PD17062 15. GENERAL-PURPOSE PORT A general-purpose port outputs a high level, low level, or floating signal to an external circuit and reads a high level or low level signal from an external circuit. 15.1 CONFIGURATION AND CLASSIFICATION OF GENERAL-PURPOSE PORT Fig. 15-1 shows a block diagram ...

190 µ PD17062 Table 15-1 Classification of General-Purpose Ports General-purpose ports Classification of general-purpose ports Target ports Data setting method I/O shared port Bit I/O Port0A Port register Port0B Port1B Group I/O Port1C Port register Input-only port Port0D Port register Output-only p...

191 µ PD17062 b 3 b 2 b 1 b 0 m n PPPP 3 2 1 0 Weight of port register bitPort register address (Examples: 70H = A, 71H = B, 72H = C, 73H = D)Port register bank"P" of port Port register Bank Address Bit 15.2 FUNCTIONS OF GENERAL-PURPOSE PORTS A general-purpose I/O port, set up either as a ge...

193 µ PD17062 Table 15-2 Relationship between Each Port (Pin) and Port Register Note Nothing is mapped to b 0 of 72H. When b 0 is read, 0 is always read. Port0A (P0A) Port0B (P0B) Port0C (P0C) Port0D (P0D) Port1A (P1A) Port1B (P1B) Port1C (P1C) P0A 3 P0A 2 P0A 1 P0A 0 P0B 3 P0B 2 P0B 1 P0B 0 P0C 3 P...

195 µ PD17062 15.3.3 Port0A Bit I/O Selection Register (P0ABIO) Port0B Bit I/O Selection Register (P0BBIO) Port1B Bit I/O Selection Register (P1BBIO) Port1C Group I/O Selection Register (P1CGPIO) The Port0A bit I/O selection register sets I/O for each pin of P0A. The Port0B bit I/O selection registe...

197 µ PD17062 15.3.6 Notes on Using I/O Ports (P0A 1 and P0A 0 ) As shown in the example below, when pins P0A 1 and P0A 0 pins are used as output pins, the contents of the output latch may be overwritten. Example: INITFLG NOT P0ABIO3, NOT P0ABIO2, P0ABIO1, P0ABIO0 ; Set the P0A 1 , P0A 0 pins as out...

201 µ PD17062 16. SERIAL INTERFACE The µ PD17062 has two sets of serial interface pins, channel 0 (CH0) and channel 1 (CH1), for exchanging data with an external unit. The CH0 pin, which consists of two wires, SDA and SCL, can be operated in any of three modes, clock synchronous two-wire serial inpu...

204 µ PD17062 16.1.1 SIO0CH The SIO0CH flag is used to select the channel of the serial interface. When the SIO0CH flag is set to 0, the serial interface hardware is connected to CH0. When the SIO0CH flag is set to 1, the serial interface hardware is connected to CH1. The external pin of the unselec...

205 µ PD17062 16.1.3 SIO0MS The SIO0MS flag specifies the serial interface clock to be used. When the SIO0MS flag is set to 0, the external clock is selected. When the SIO0MS flag is set to 1, the internal clock is selected. When the internal clock is selected, its frequency is set by the shift cloc...

207 µ PD17062 16.3 STATUS REGISTER The status register is a four-bit read-only register that retains the start and stop states in two-wire bus mode and the contents of the current clock counter. Fig. 16-2 Configuration of Status Register 16.3.1 SBBSY (Serial Bus Busy) Flag The SBBSY flag, mapped to ...

208 µ PD17062 16.3.4 SIO0SF8 (Serial I/O Shift 8 Clock) Flag The SIO0SF8 flag, mapped to b 3 of the status register, is set to 1 when the contents of the clock counter become 8. When the contents of the clock counter become 0 or 1, the SIO0SF8 flag is reset to 0. An operation to read the presettable...

209 µ PD17062 16.4 WAIT REGISTER The µ PD17062 can set a state in which the serial interface hardware does not operate, even if a shift clock is input. This state is called wait mode and is set by the wait register. The wait register consists of four bits; the SIO0WRQ0 flag, which specifies the timi...

210 µ PD17062 Table 16-8 Wait Timings (1) Slave operation wait in two-wire bus mode When the timing specified by SIO0WRQ1 and SIO0WRQ0 is set, the SCL pin is switched to output mode and a low level signal is output. If no-wait (SIO0WRQ1 = SIO0WRQ0 = 0) is specified, this operation is not performed. ...

212 µ PD17062 16.4.2 SIO0NWT (Serial I/O No-Wait) Flag Writing appropriate data into the SIO0NWT flag can both release wait and execute forced wait. (1) Writing 0 into SIO0NWT In this case, forced wait is executed. In other words, the clock being supplied to the clock counter and presettable shift r...

216 µ PD17062 Bit position b 3 b 2 b 1 b 0 Flag name SIO0CK3 SIO0CK2 SIO0CK1 SIO0CK0 (0) (0) SIO0CK1 SIO0CK0 Internal clock frequency 0 0 100 kHz 0 1 200 kHz 1 0 500 kHz 1 1 1 MHz 16.7 SHIFT CLOCK FREQUENCY REGISTER (SIO0CK) The shift clock frequency register is a four-bit register for setting the f...

217 µ PD17062 Peripheral equipment Peripheral address Corresponding pin PWM0 05H PWM 0 PWM1 06H PWM 1 PWM2 07H PWM 2 PWM3 08H PWM 3 17. D/A CONVERTER 17.1 PWM PINS The µ PD17062 has 4 output pins for 6-bit PWM, which enables varying the duty cycle of the 15.625 kHz pulse signal in 64 steps. With thi...

218 µ PD17062 Fig. 17-1 PWMR Structure and the Corresponding DBF Bits Fig. 17-2 Waveform Output from the PWM Pin b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 PWMR DBF1 (0EH) DBF0 (0FH) The PWM pin is used as a D/A converter. The PWM pin is used as a one-bit output port (through mo...

219 µ PD17062 18. PLL FREQUENCY SYNTHESIZER 18.1 PLL FREQUENCY SYNTHESIZER CONFIGURATION Fig. 18-1 is a block diagram of the PLL frequency synthesizer. As shown in Fig. 18-1, the PLL frequency synthesizer consists of a programmable divider (PD), phase comparator ( φ -DET), reference frequency genera...

220 µ PD17062 18.2 OVERVIEW OF EACH PLL FREQUENCY SYNTHESIZER BLOCK The PLL frequency synthesizer receives an input signal at the VCO pin, divides its frequency in the programmable divider, and outputs the difference in phase between the divider output and the reference frequency from the EO pin. Th...

224 µ PD17062 18.4.2 PLL Reference Mode Select Register Configuration and Functions Fig. 18-4 shows the configuration and functions of the PLL reference mode select register. When the PLL reference mode select register selects the PLL disable mode, the VCO pin is pulled down internally, and the EO p...

231 µ PD17062 18.6 PLL DISABLE MODE The PLL frequency synthesizer is disabled when the CE pin is at a low level. It is also disabled when the PLL reference mode select register (PLRFMODE, at address 13H) selects the PLL disable mode. Table 18-1 summarizes how each block operates during the PLL disab...

232 µ PD17062 PLLR 0000 0110 1100 1111 0 6 C F PLRFMODE 0010 6.25 kHz 18.7 SETTING DATA FOR THE PLL FREQUENCY SYNTHESIZER The following data is necessary to control the PLL frequency synthesizer. (1) Reference frequency : f r (2) Division value : N The following paragraphs explain how to set the PLL...

233 µ PD17062 19. A/D CONVERTER The µ PD17062 contains a 4-bit program-controlled A/D converter that operates with a successive compari- son method. 19.1 PRINCIPLE OF OPERATION The A/D converter in the µ PD17062 consists of a 4-bit resistor string-based D/A converter and comparator. The D/A converte...

234 µ PD17062 19.2 D/A CONVERTER CONFIGURATION The D/A converter used in the A/D converter of the µ PD17062 is a resistor string D/A converter consisting of 16 resistors connected in series between the V DD and GND pins in which a voltage at each resistor connection point is selected. The configurat...

236 µ PD17062 b 3 b 2 b 1 #0 (MSB) (LSB) (RF : 21H) ADCCMP ADCCH2 ADCCH1 ADCCH0 Selected pin 0 0 0 ADC 0 0 0 1 P1C 3 /ADC 1 0 1 0 P0D 0 /ADC 2 0 1 1 P0D 1 /ADC 3 1 0 0 P0D 2 /ADC 4 1 0 1 P0D 3 /ADC 5 1 1 0 No corresponding pin(do not set) 1 1 1 19.5 ADC PIN SELECT REGISTER (ADCCHn) The ADCCHn regist...

237 µ PD17062 19.6 EXAMPLE OF A/D CONVERSION PROGRAM The following example shows an A/D conversion program based on the successive comparison method. The result of conversion is held in the DBF0. Sample program DBF0B3 FLG 0.0FH.3 DBF0B2 FLG 0.0FH.2 DBF0B1 FLG 0.0FH.1 DBF0B0 FLG 0.0FH.0 START: BANK0 ...

240 µ PD17062 TV screen 19 characters 14 rows 20. IMAGE DISPLAY CONTROLLER The image display controller (IDC) function indicates a channel number, volume of sound, time, and other information on a TV screen. The pattern of a display is user-programmable, and the display pattern definition is stored ...

242 µ PD17062 (6) Up to 4 different character sizes, both vertical and horizontal, are available. The same vertical character size is specified for all characters in a row, while the horizontal character size is specified for individual characters (according to the control data Note 1 ). (7) The cha...

243 µ PD17062 20.2 DIRECT MEMORY ACCESS The direct memory access (DMA) function transfers memory contents directly to peripheral equipment, without using the CPU. In the µ PD17062, the DMA mode is used to run the IDC. The instruction cycle of the µ PD17062 is 2 µ s, but its apparent instruction cycl...

244 µ PD17062 Sample program Remark The “SET1” or “CLR1” is not included in the µ PD17062 instruction set. They are a built-in macro instruction of the 17K series assembler. They set or reset a one-bit flag. If they are written in a source program as shown at *1, they are expanded during assembly as...

245 µ PD17062 b 3 b 2 b 1 b 0 0 0 IDCEN 0 1 0 Turns off the display. Turns on the display. (RF 31H) ------ ------ 20.3 IDC ENABLE FLAG The IDCEN (IDC enable) flag is manipulated to start IDC operations (turn on the display). The flag is mapped at the lowest bit (#0) of the register file at 31H. Tabl...

247 µ PD17062 Fig. 20-2 VRAM Data Configuration 20.4.1 ID Field The ID field indicates the type of data in the data field. The data field can hold the following three types of data. (1) Character pattern select data (2) Carriage return data (3) Control data select data Table 20-3 ID Field 20.4.2 Cha...

249 µ PD17062 Sample program If the CROM data and VRAM data are specified as shown above, the display on the screen varies depending on the CROM bank. The CROM bank is specified by CROMBNK (b 0 at 30H). The following description applies to the above example. (1) CROMBNK = 0 Display “CH” appears on t...

250 µ PD17062 20.4.3 Carriage Return Data The term carriage return data refers to the data pointing to the address of the VRAM data that specifies the first character in a row on the screen. The carriage return data specifies the end of a display row. When carriage return data appears two times cons...

252 µ PD17062 20.4.4 Control Data Select Data The term control data refers to the data that specifies the character size, display position, and color of a character pattern on the screen. This data is held in CROM (at ××× FH). The control data select data is held in VRAM and selects control data in ...

254 µ PD17062 20.4.5 Cautions in Specifying VRAM Data (1) Reset the IDCEN flag to 0 before specifying VRAM data. (2) The VRAM data must begin at 00H in BANK1. (3) Do not set VRAM data at 7 × H in BANK1 or BANK2. (4) Always set control data at the beginning of a screen. To prevent a program error, co...

255 µ PD17062 20.5 CHARACTER ROM The CROM (character ROM) consists of the IDC pattern data and control data. The CROM data shares the program memory with programs. The CROM area has a capacity of 2 Ksteps (1920 × 16 bits). An area not used as CROM is used as an ordinary program area. The CROM area i...

256 µ PD17062 Fig. 20-6 Character Pattern Data Configuration (a) Data for a character with no rimming (b) Data for a character with rimming If 2 is to be displayed, the character pattern is set as shown in Fig. 20-7. 0 and 1 in the pattern data correspond to ■ ■ and ■ , respectively. In addition, th...

257 µ PD17062 Fig. 20-8 Example of the Pattern of a Character with Rimming × × × × 0 H × × × × 1 H × × × × 2 H × × × × 3 H × × × × 4 H × × × × 5 H × × × × 6 H × × × × 7 H × × × × 8 H × × × × 9 H × × × × A H × × × × B H × × × × C H × × × × D H × × × × E H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0...

258 µ PD17062 20.5.2 Control Data The control data specifies the display position, size, and color of a character pattern. It is stored at ××× FH in the CROM area. One control data item consists of 16 bits. The highest bit is always 0. Fig. 20-9 shows the configuration of the control data. Fig. 20-9...

260 µ PD17062 (4) Vertical position data (b 6 to b 3 of the control data) The vertical position data specifies which of the 12 rows (vertical positions) shown in Fig. 20-10 the display is to begin at. The vertical position data consists of four bits of the control data, with b 6 corresponding to the...

262 µ PD17062 20.5.3 Defining Display Patterns with an Assembler With the 17K series assembler, the DCP pseudo instruction can be used to define display patterns easily. How to use the DCP pseudo instruction is described below. (1) Instruction format Symbol field Mnemonic field Operand field Comment...

263 µ PD17062 20.6 BLANK, R, G, AND B PINS All these pins are CMOS push-pull output pins. They output an active-high signal. The BLANK pin outputs a signal to turn off a broadcasting picture. The R, G, and B pins output character pattern data. If rimming is not specified, the BLANK signal is the sam...

264 µ PD17062 20.7 SPECIFYING THE DISPLAY START POSITION IDC display start positions (upper left of the screen) can be specified by setting data in the IDC start position setting register. Up to 16 horizontal and vertical positions can be specified. In other words, the display position of the entire...

265 µ PD17062 20.7.1 Horizontal Start Position Setting Register If the horizontal start position setting register contains 0H, the horizontal start position is set 4.25 µ s after the trailing edge of the horizontal sync signal. Each time the horizontal start position setting register is incremented ...

266 µ PD17062 20.7.2 Vertical Start Position Setting Register If the vertical start position setting register contains 0H, the vertical start position is set 17 H (interlace) after the trailing edge of the vertical sync signal. Each time the vertical start position setting register is incremented by...

267 µ PD17062 The vertical start position of the display character is determined by the vertical start position register. At this point, the vertical start position (number of horizontal scan lines) depends on the state of the V SYNC and H SYNC signals supplied to the µ PD17062, as shown in Fig. 20-...

268 µ PD17062 20.8 SAMPLE PROGRAMS The following sample program generates a display shown below. The RAM names of VRAM are defined as follows (tentative): NEC CH 02 ....... 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C H 0 2 Display on the TV screen Column Column Row 0 Row 5 4 3 2 1 0 1 2 3 4 5 6 7 0 1 2 ...

274 µ PD17062 21. HORIZONTAL SYNC SIGNAL COUNTER 21.1 HORIZONTAL SYNC SIGNAL COUNTER CONFIGURATION The horizontal sync signal counter counts the frequency of a horizontal sync signal for TV or similar equipment. When a TV broadcasting signal is received, a prescribed horizontal sync signal is output...

275 µ PD17062 21.2 GATE CONTROL REGISTER (HSCGT) The gate control register is a 2-bit register consisting of the HSCGT1 and HSCGT0 flags used to control the gate. It is mapped in the register file at 11H. The gate control register can be read- and write-accessed through the window register (system r...

277 µ PD17062 22. INSTRUCTION SETS 22.1 OUTLINE OF INSTRUCTION SETS b 15 b 14 -b 11 0 1 BIN HEX 0 0 0 0 0 ADD r, m ADD m, #n4 0 0 0 1 1 SUB r, m SUB m, #n4 0 0 1 0 2 ADDC r, m ADDC m, #n4 0 0 1 1 3 SUBC r, m SUBC m, #n4 0 1 0 0 4 AND r, m AND m, #n4 0 1 0 1 5 XOR r, m XOR m, #n4 0 1 1 0 6 OR r, m OR...

278 µ PD17062 22.2 INSTRUCTIONS Legend AR : Address register ASR : Address stack register pointed to by the stack pointer addr : Program memory address (11 low-order bits) BANK : Bank register CMP : Compare flag CY : Carry flag DBF : Data buffer h : Halt release condition INTEF : Interrupt enable fl...

279 µ PD17062 22.3 LIST OF INSTRUCTION SETS Instruction set Add Subtract Logical operation Test Compare Rotation Transfer Mne- monic ADD ADDC INC SUB SUBC OR AND XOR SKT SKF SKE SKNE SKGE SKLT RORC LD ST MOV MOVT Operand r, m m, #n4 r, m m, #n4 AR IX r, m m, #n4 r, m m, #n4 r, m m, #n4 r, m m, #n4 r...

281 µ PD17062 22.4 BUILT-IN MACRO INSTRUCTIONS The following macro instructions are built in the 17K series assembler (AS17K). For details, refer to the assembler user’s guide. Legend flag n : FLG-type symbol < > : An operand enclosed in < > is optional. Mnemonic Operand Operation n Buil...

282 µ PD17062 23. RESERVED SYMBOLS FOR ASSEMBLER The reserved µ PD17062 symbols for the assembler are listed below. 23.1 SYSTEM REGISTER MEM MEM MEM MEM MEM MEM MEM MEM FLG MEM MEM MEM MEM MEM MEM FLG FLG FLG FLG FLG 0.74H 0.75H 0.76H 0.77H 0.78H 0.79H 0.7AH 0.7AH 0.7AH.3 0.7BH 0.7BH 0.7CH 0.7DH 0.7...

284 µ PD17062 Symbol Attribute Value Read/ Description write IDCDMAEN FLG 0.80H.1 R/W DMA enable flag SP MEM 0.81H R/W Stack pointer CE FLG 0.87H.0 R CE pin status flag SIO0CH FLG 0.88H.3 R/W SIO0 channel selection flag SB FLG 0.88H.2 R/W SIO0 mode selection flag SIO0MS FLG 0.88H.1 R/W SIO0 clock mo...

286 µ PD17062 23.5 PERIPHERAL HARDWARE REGISTER Symbol Attribute Value Read/ Description write IDCORG DAT 01H R/W IDC start position setting register ADCR DAT 02H R/W A/D-converter reference-voltage (V REF ) setting register SIO0SFR DAT 03H R/W SIO0 register HSC DAT 04H R Hsync counter data register...

288 µ PD17062 AC CHARACTERISTICS (T a = –40 to +85 ° C, V DD = 5 V ± 10 %, RH ≤ 70 %) Parameter Symbol Conditions Min. Typ. Max. Unit Operating frequency f in1 VCO Sine wave input V in = 0.7 V P-P 0.7 20 MHz f in2 TMIN 45 65 Hz f in3 HSCNT 10 20 kHz IDC jitter IDC G 4.0 8.0 ns IDC horizontal start p...

289 µ PD17062 25. PACKAGE DRAWINGS 48PIN PLASTIC SHRINK DIP (600 mil) I T E M M I L L I M E T E R S I N C H E S N O T E S 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. N 0 . 1 7 0 . 0 0 7 A 4 4 . 4 6 M A X . 1 . 7 5 1 M A X ...

290 µ PD17062 64 PIN PLASTIC QFP ( 14) I T E M M I L L I M E T E R S I N C H E S F G K N J 1 . 0 1 . 6 ± 0 . 2 0 . 1 0 0 . 8 ( T . P . ) 1 . 0 Q 0 . 0 3 9 0 . 0 3 9 0 . 0 6 3 ± 0 . 0 0 8 0 . 0 0 4 0 . 0 3 1 ( T . P . ) S64GC-80-3BE-1 A C N O T E Each lead centerline is located within 0.13 mm (0.005 ...

291 µ PD17062 26. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the µ PD17062. For details of the recommended soldering conditions, refer to our document SMD Surface Mount Technology Manual (IEI-1207). Please consult with our sales offices in case any other...

292 µ PD17062 Name Description APPENDIX DEVELOPMENT TOOLS The following support tools are available for developing programs for the µ PD17062. Hardware The IE-17K, IE-17K-ET, and EMU-17K are in-circuit emulators applicable to the 17K series. The IE-17K and IE-17K-ET are connected to the PC-9800 seri...

293 µ PD17062 17K series assembler (AS17K) Device file (AS17062) Support software (SIMPLEHOST) µ S5A10AS17K µ S5A13AS17K µ S7B10AS17K µ S7B13AS17K µ S5A10AS17062 µ S5A13AS17062 µ S7B10AS17062 µ S7B13AS17062 µ S5A10IE17K µ S5A13IE17K µ S7B10IE17K µ S7B13IE17K AS17K is an assembler applicable to the 1...

295 µ PD17062 Cautions on CMOS Devices # Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, u...

296 µ PD17062 SIMPLEHOST is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. Caution This product contains an I 2 C bus interface circuit. When using the I 2 C bus interface, notify its use to NEC when ord...