NEC 30500B - Manual

NEC 30500B

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Table of Contents:

  • Page 2 – Note; MAIN DIFFERENCES BETWEEN V; Notes 1. Under development
  • Page 3 – PIN CONFIGURATION; Index mark
  • Page 5 – Bottom View; Under development
  • Page 8 – PIN NAMES
  • Page 9 – INTERNAL BLOCK DIAGRAM
  • Page 10 – PIN FUNCTIONS
  • Page 11 – IO is only for V
  • Page 12 – ELECTRICAL SPECIFICATIONS; The upper limit of the input voltage (V
  • Page 13 – Clock parameter; 000 is guaranteed only when the PLL is operating
  • Page 16 – 000A is guaranteed only when the PLL is operating
  • Page 17 – Two kinds of power sources are provided with the V
  • Page 19 – 000B is guaranteed only when the PLL is operating
  • Page 21 – Test Condition; Test Load; Timing Chart; SysClock; Mode clock timing; ModeClock
  • Page 22 – Clock jitter; System interface edge timing
  • Page 25 – Warm reset timing; IO; Ok
  • Page 26 – PACKAGE DRAWING; Index Mark; NOTE; T S R Q P N M L K J H G F E D C B A
  • Page 27 – N O T E S; Controlling dimension millimeter.
  • Page 28 – RECOMMENDED SOLDERING CONDITIONS; (1) Soldering Conditions of Surface Mount Type
  • Page 29 – DIFFERENCES BETWEEN THE V; TM
  • Page 30 – NOTES FOR CMOS DEVICES; PRECAUTION AGAINST ESD FOR SEMICONDUCTORS; to be taken for PW boards with semiconductor devices on it.; HANDLING OF UNUSED INPUT PINS FOR CMOS; pin should be connected to V; or GND with a resistor, if it is considered to have a possibility of; STATUS BEFORE INITIALIZATION OF MOS DEVICES; having reset function.; Series are trademarks of NEC Corp.
  • Page 31 – Regional Information; • Device availability
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©

1997,1999

DATA SHEET

©

1997

MIPS Technologies Inc.

MOS INTEGRATED CIRCUIT

µ

PD30500, 30500A, 30500B

Document No. U12031EJ3V0DS00 (3rd edition)
Date Published August 1999 N CP(K)
Printed in Japan

DESCRIPTION

The

µ

PD30500 (V

R

5000),

µ

PD30500A

Note

(V

R

5000A), and

µ

PD30500B

Note

(V

R

5000B) are a high-performance,

64-bit RISC (Reduced Instruction Set Computer) type microprocessors employing the RISC architecture developed

by MIPS

TM

Technologies Inc.

The instructions of the V

R

5000, V

R

5000A, and V

R

5000B are compatible with those of the V

R

3000

TM

series and

V

R

4000

TM

series and higher, and completely compatible with those of the V

R

10000

TM

. Therefore, present applications

can be used as they are.

Note

Under development

Detailed functions are descrided in the following manual. Be sure to read the manual when

designing your system.

• V

R

5000 User’s Manual (U11761E)

FEATURES

•

Employs 64-bit MIPS-based RISC architecture

•

High-speed processing

•

2-way super scalar 5-stage pipeline

•

5.5 SPECint95, 5.5 SPECfp95, 278 MIPS (

µ

PD30500)

6.6 SPECint95, 6.6 SPECfp95, 353 MIPS (

µ

PD30500A)

8 SPECint95, 8 SPECfp95, 423 MIPS (

µ

PD30500B)

•

High-speed translation buffer mechanism (TLB) (48 entries)

•

Address space

Physical: 36 bits, Virtual: 40 bits

•

Floating-point unit (FPU)

•

Sum-of-products operation instruction supported

•

Primary cache memory (instruction/data: 32K bytes each)

•

Secondary cache controller

•

Maximum operating frequency Internal : 200MHz (

µ

PD30500), 250 MHz (

µ

PD30500A), 300 MHz (

µ

PD30500B)

External: 100 MHz

•

External/internal multiple selectable from two to eight

•

Instruction set compatible with V

R

3000 and V

R

4000 series and higher (conforms to MIPS I, II, III, and IV)

•

Supply voltage: 3.3 V

±

5% (

µ

PD30500)

Core: 2.5 V

±

5%, I/O: 3.3 V

±

5% (

µ

PD30500A)

Core: 1.8 V

±

0.1 V, I/O: 3.3 V

±

5% (

µ

PD30500B)

Unless otherwise specified, the V

R

5000 (

µ

PD30500) is treated as the representative model throughout this

document.

V

R

5000

TM

, V

R

5000A

TM

, V

R

5000B

TM

64-BIT MICROPROCESSOR

The mark shows major revised points.

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
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Summary

Page 2 - Note; MAIN DIFFERENCES BETWEEN V; Notes 1. Under development

µ PD30500, 30500A, 30500B 2 Data Sheet U12031EJ3V0DS00 APPLICATIONS • High-performance embedded systems • Multimedia systems • Entry-class computers • Image processing systems ORDERING INFORMATION Part number Package Maximum operating frequency (MHz) µ PD30500RJ-150 223-pin ceramic PGA (48 × 48 mm) ...

Page 3 - PIN CONFIGURATION; Index mark

µ PD30500, 30500A, 30500B 3 Data Sheet U12031EJ3V0DS00 PIN CONFIGURATION • 223-pin ceramic PGA (48 × 48 mm) µ PD30500RJ-150 µ PD30500RJ-180 µ PD30500RJ-200 181716151413121110987654321 A B C D E F G H J K L M N P R T U V V U T R P N M L K J H G F E D C B A Index mark Bottom View Top View

Page 5 - Bottom View; Under development

µ PD30500, 30500A, 30500B 5 Data Sheet U12031EJ3V0DS00 • 272-pin plastic BGA (29 × 29 mm) µ PD30500S2-150 µ PD30500S2-180 µ PD30500S2-200 µ PD30500AS2-200 Note µ PD30500AS2-250 Note µ PD30500BS2-250 Note µ PD30500BS2-300 Note Bottom View Top View 212019181716151413121110987654321 AA Y W V U T R P N ...

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