Lucent Technologies MN102H75K - Manual

Lucent Technologies MN102H75K

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Table of Contents:

  • Page 3 – and semiconductors described in this book; of patents or any other rights owned by a third party.
  • Page 4 – M N 1 0 2 H 7 5 K / F 7 5 K L S I U s e r M a n u a l; C o n t e n t s
  • Page 5 – P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y; Setting Up I
  • Page 8 – Setting Up the I; Appendix A
  • Page 10 – L i s t o f T a b l e s; M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l; L i s t o f Ta b l e s
  • Page 11 – Operating Modes for Devices on an I
  • Page 12 – L i s t o f F i g u r e s
  • Page 14 – Master Transmitter Timing in I
  • Page 16 – Example of I
  • Page 17 – U s i n g T h i s M a n u a l; U s i n g T h i s M a n u a l; REGISTER: Register Name; Key information; These notes summarize key points relating to an operation.
  • Page 18 – R e l a t e d D o c u m e n t s; MN102H Series LSI User Manual
  • Page 19 – M N 1 0 2 H S e r i e s O v e r v i e w; G e n e r a l D e s c r i p t i o n; M N 1 0 2 H S e r i e s O v e r v i e w; speed and functionality.; M N 1 0 2 H S e r i e s F e a t u r e s; High-speed signal processing
  • Page 20 – Single-byte basic instruction length; load/store operations occupy only one byte.; High-speed pipeline throughput; most frequently used basic instructions are single-byte.; New Panasonic code assignments
  • Page 21 – Fast interrupt response; The MN102H series combines hardware optimized for C language pro-
  • Page 22 – Outstanding power savings; array of embedded designs.; M N 1 0 2 H S e r i e s D e s c r i p t i o n; operation results; VX: Extension overflow
  • Page 23 – NX: Extension negative flag
  • Page 26 – CPU Core; Interrupt Controller; Figure 1-7 Interrupt Servicing Sequence
  • Page 27 – G e n e r a l S p e c i f i c a t i o n s; Table 1-1 General Specifications
  • Page 29 – B l o c k D i a g r a m; B l o ck D i a g r a m; Figure 1-8 Functional Block Diagram
  • Page 31 – P i n D e s c r i p t i o n s; M N 1 0 2 H 8 5 K P i n D e s c r i p t i o n; Figure 1-9 MN102H85K Pin Configuration in Single-Chip Mode; Top View
  • Page 32 – M N 1 0 2 H 7 5 K P i n D e s c r i p t i o n; Figure 1-10 MN102H75K Pin Configuration in Single-Chip Mode
  • Page 36 – B u s I n t e r f a c e; D e s c r i p t i o n; memory space for the MCU in this mode.; External Expansion Mode
  • Page 37 – B u s I n t e r f a c e C o n t r o l R e g i s t e r s; the external oscillator is 4 MHz, one wait is 83 ns.
  • Page 38 – I n t e r r u p t s; parable MCU in the previous generation of the 16-bit series.
  • Page 40 – Program
  • Page 41 – I n t e r r u p t S e t u p E x a m p l e s; S e t t i n g U p a n E x t e r n a l P i n I n t e r r u p t; external interrupt pin, and the interrupt priority level is 5.; CORE
  • Page 43 – S e t t i n g U p a Wa t ch d o g Ti m e r I n t e r r u p t; Enabling watchdog timer interrupts; Clearing the watchdog timer; Figure 2-6 Block Diagram of Watchdog Timer Interrupt
  • Page 44 – Figure 2-7 Timing for Watchdog Timer Interrupt Setup (Example)
  • Page 45 – I n t e r r u p t C o n t r o l R e g i s t e r s; ID : Interrupt detect flag; : Interrupt undetected; IE: Interrupt enable flag
  • Page 46 – IR: Interrupt request flag; : No interrupt requested; ID: Interrupt detect flag; Example 2-1 Setting the Interrupt Priority Level
  • Page 47 – Register
  • Page 49 – WDID : Watchdog interrupt detect flag
  • Page 50 – PIID : Undefined instruction interrupt detect flag; EIICR: Interrupt error Interrupt Control Register; IQ0IR: External interrupt 0 interrupt request flag
  • Page 51 – IQ0IE: External interrupt 0 interrupt enable flag; IQ1ICL: External Interrupt 1 Interrupt Control Register (Low); IQ1IR: External interrupt 1 interrupt request flag; IQ1IE: External interrupt 1 interrupt enable flag
  • Page 52 – IQ2IR: External interrupt 2 interrupt request flag; IQ2ICH: External Interrupt 2 Interrupt Control Register (High); IQ2IE: External interrupt 2 interrupt enable flag; IQ3ICL: External Interrupt 3 Interrupt Control Register (Low); IQ3IR: External interrupt 3 interrupt request flag
  • Page 53 – IQ3IE: External interrupt 3 interrupt enable flag; IQ4ICL: External Interrupt 4 Interrupt Control Register (Low); IQ4IR: External interrupt 4 interrupt request flag; IQ4IE: External interrupt 4 interrupt enable flag
  • Page 54 – IQ5IR: External interrupt 5 interrupt request flag; IQ5ICH: External Interrupt 5 Interrupt Control Register (High); IQ5IE: External interrupt 5 interrupt enable flag
  • Page 55 – TM4CBIE: Timer 4 compare/capture B interrupt enable flag; TM4CAID: Timer 4 compare/capture A interrupt detect flag; TM4CAICH enables timer 4 compare/capture interrupts. It is an 8-bit; TM4CAIE: Timer 4 compare/capture A interrupt enable flag
  • Page 56 – TM4UDIR : Timer 4 underflow interrupt request flag; TM4UDICH: Timer 4 Underflow Interrupt Control Register (High); TM4UDIE: Timer 4 underflow interrupt enable flag
  • Page 57 – TM5CBIR : Timer 5 compare/capture B interrupt request flag; TM5CBIE: Timer 5 compare/capture B interrupt enable flag
  • Page 58 – TM5CAIR : Timer 5 compare/capture A interrupt request flag; TM5CAICH enables timer 5 compare/capture interrupts. It is an 8-bit; TM5CAIE: Timer 5 compare/capture A interrupt enable flag; TM5UDID: Timer 5 underflow interrupt detect flag
  • Page 59 – TM5UDIE: Timer 5 underflow interrupt enable flag
  • Page 60 – TM2UDIR : Timer 2 underflow interrupt request flag; TM2UDICH: Timer 2 Underflow Interrupt Control Register (High); TM2UDIE: Timer 2 underflow interrupt enable flag
  • Page 61 – TM1UDIE: Timer 1 underflow interrupt enable flag; TM0UDIE: Timer 0 underflow interrupt enable flag
  • Page 62 – RMCIR : Remote signal receive interrupt request flag; RMCICH: Remote Signal Receive Interrupt Control Register (High); RMCIE: Remote signal receive interrupt enable flag
  • Page 63 – ADM3IE: Address match 3 interrupt enable flag; access register. Use the MOVB instruction to access it.; ADM2IR : Address match 2 interrupt request flag; ADM2IE: Address match 2 interrupt enable flag
  • Page 64 – ADM1IR : Address match 1 interrupt request flag
  • Page 65 – ADM0IE: Address match 0 interrupt enable flag; ANIE: A/D conversion end interrupt enable flag
  • Page 66 – SCT0IR : Serial 0 transmission end interrupt request flag; SCR0ICL: Serial 0 Reception End Interrupt Control Register (Low); SCT0IR : Serial 0 reception end interrupt request flag
  • Page 67 – SCR0IE: Serial 0 reception end interrupt enable flag
  • Page 68 – TM3UDIR : Timer 3 underflow interrupt request flag
  • Page 69 – TM3UDIE: Timer 3 underflow interrupt enable flag
  • Page 70 – SCT1IR : Serial 1 transmission end interrupt request flag
  • Page 71 – SCT1IE: Serial 1 transmission end interrupt enable flag; SCR1ICL: Serial 1 Reception End Interrupt Control Register (Low); SCT1IR : Serial 1 reception end interrupt request flag; SCT1ID: Serial 1 reception end interrupt detect flag; SCR1ICH: Serial 1 Reception End Interrupt Control Register (High); SCR1IE: Serial 1 reception end interrupt enable flag
  • Page 72 – C interrupt request flag
  • Page 73 – L o w - P o w e r M o d e s; L o w - Po w e r M o d e s; C P U M o d e s; A normal reset or an interrupt wakes the MCU from a standby mode.
  • Page 74 – E x i t i n g f r o m S L OW M o d e t o N O R M A L M o d e; routine immediately after power up.
  • Page 75 – N o t e s o n I nvo k i n g a n d E x i t i n g S TO P a n d H A LT M o d e s; MCU exits on reset, it always exits to SLOW mode.
  • Page 76 – T u r n i n g I n d i v i d u a l F u n c t i o n s O n a n d O f f; Tu r n i n g I n d i v i d u a l F u n c t i o n s O n a n d O f f
  • Page 77 – C P U C o n t r o l R e g i s t e r; This register controls the invoking of all of the CPU modes.; NWDEN: Watchdog timer reset; System clock monitor; STOP: STOP mode request; All unindicated bit settings are reserved.
  • Page 78 – - B i t T i m e r D e s c r i p t i o n; - B i t T i m e r D e s c r i p t i o n; interrupt is generated by a timer underflow.; Figure 4-1 Timer Configuration Examples; Cascading Connections
  • Page 79 – - B i t T i m e r F e a t u r e s; When B
  • Page 80 – - B i t T i m e r B l o c k D i a g r a m s; - B i t T i m e r B l o ck D i a g r a m s; Figure 4-3 Timer 0 Block Diagram
  • Page 82 – - B i t T i m e r T i m i n g
  • Page 83 – - B i t T i m e r S e t u p E x a m p l e s; S e t t i n g U p a n E ve n t C o u n t e r U s i n g Ti m e r 0; edge of the TM0IO signal.; signal resulting from the B; sampling of the TMnIO signal input.; Figure 4-9 Block Diagram of Event Counter Using Timer 0
  • Page 84 – underflow interrupt request is sent to the CPU.
  • Page 85 – S e t t i n g U p a n I n t e r v a l Ti m e r U s i n g Ti m e r s 1 a n d 2; In this example, timers 1 and 2 are cascaded to divide B; generate an underflow interrupt.; Timer 1
  • Page 87 – Set TM2LD to 0 and TM2EN to 1, then set TM1LD to 0 and TM1EN to 1.
  • Page 88 – - B i t T i m e r C o n t r o l R e g i s t e r s; TMnEN: TMnBC count enable
  • Page 89 – 6 - B i t T i m e r D e s c r i p t i o n; Figure 4-14 Block Diagram of 16-Bit Timers
  • Page 90 – 6 - B i t T i m e r F e a t u r e s; Table 4-3 16-Bit Timer Functions and Features
  • Page 91 – 6 - B i t T i m e r B l o c k D i a g r a m s; 6 - B i t T i m e r B l o ck D i a g r a m s; Figure 4-15 Timer 4 Block Diagram; TMnIOA
  • Page 92 – 6 - B i t T i m e r T i m i n g
  • Page 94 – Time
  • Page 95 – 6 - B i t T i m e r S e t u p E x a m p l e s; . 1 1 1 6 - B i t T i m e r S e t u p E x a m p l e s; . 1 1 . 1 S e t t i n g U p a n E ve n t C o u n t e r U s i n g Ti m e r 4; In this example, timer 4 counts the TM4IB input signal (B; and generates an interrupt on the second and fifth cycles.; Set the operating mode in the timer 4 mode register (TM4MD). Disable; Controller
  • Page 97 – . 1 1 . 2 S e t t i n g U p a S i n g l e - P h a s e P W M O u t p u t S i g n a l U s i n g; In this example, timer 4 is used to divide B; To set up the output port:
  • Page 98 – Set the divide-by ratio for timer 4. To divide B; prevents timing errors.
  • Page 102 – . 1 1 . 3 S e t t i n g U p a Two - P h a s e P W M O u t p u t S i g n a l U s i n g
  • Page 103 – as B
  • Page 107 – . 1 1 . 4 S e t t i n g U p a S i n g l e - P h a s e C a p t u r e I n p u t U s i n g Ti m e r 4; from the contents of TMnCB.; select looped counting from 0 to x’FFFF’. Select B; Interrupt B; Timer 4
  • Page 108 – To enable timer 4 capture B interrupts:; Timer 4 does not operate in STOP mode, when B; is off. If you use an external
  • Page 109 – . 1 1 . 5 S e t t i n g U p a Two - P h a s e C a p t u r e I n p u t U s i n g Ti m e r 4; unnecessary immediately after a reset, since TM0MD resets to 0.; Figure 4-37 Block Diagram of Two-Phase Capture Input Using Timer 4
  • Page 111 – does not operate in STOP mode, when B; is off. If you use an external clock, it; read during the interrupt service routine.
  • Page 112 – . 1 1 . 6 S e t t i n g U p a 4 x Two - P h a s e E n c o d e r I n p u t U s i n g Ti m e r 5; Timer 5
  • Page 113 – occurs at the beginning of the next cycle.
  • Page 114 – is off. If you use an external clock, it must be synchronized to; Table 4-4 Count Direction for 4x Two-Phase Encoder Timing Example
  • Page 115 – Setting Up a 1x Two-Phase Encoder Input U s i n g Ti m e r 5
  • Page 117 – Table 4-5 Count Direction for 1x Two-Phase Encoder Timing Example
  • Page 118 – . 1 1 . 8 S e t t i n g U p a O n e - S h o t P u l s e O u t p u t U s i n g Ti m e r 5
  • Page 119 – counting and interrupts. Select up counting. Select B; same as it does during two-phase PWM output.
  • Page 120 – is off. If you use an external clock, it must be synchronized to B
  • Page 121 – . 1 1 . 9 S e t t i n g U p a n E x t e r n a l C o u n t D i r e c t i o n C o n t r o l l e r; In this example, timer 5 counts B; /4 and the TM5IA pin controls the count
  • Page 123 – when the timer switches from down to up counting.
  • Page 124 – . 1 1 . 1 0 S e t t i n g U p E x t e r n a l R e s e t C o n t r o l U s i n g Ti m e r 5; Set the operating mode in the timer 5 mode register (TM5MD). Disable; Figure 4-52 Block Diagram of External Reset Control Using Timer 5
  • Page 125 – Figure 4-53 shows an example timing chart.
  • Page 126 – 6 - B i t T i m e r C o n t r o l R e g i s t e r s; . 1 2 1 6 - B i t T i m e r C o n t ro l R e g i s t e r s
  • Page 127 – TMnTGE: External trigger enable for start count
  • Page 128 – S e r i a l I n t e r f a c e s; C modes. The maximum baud rate in synchronous; F e a t u r e s
  • Page 129 – C o n n e c t i n g t h e S e r i a l I n t e r f a c e s; S y n ch r o n o u s S e r i a l M o d e C o n n e c t i o n s; chronous serial transfers.; UA RT M o d e C o n n e c t i o n s; The serial interfaces can connect to I; . Either connect a pullup; A. Simplex Connection; A. Simplex Connection; Figure 5-3 UART Mode Connections; Transmit; SBO; Slave
  • Page 130 – U A R T M o d e B a u d R a t e s; UA R T M o d e B a u d R a t e s; S e r i a l I n t e r f a c e T i m i n g; S y n ch r o n o u s S e r i a l M o d e Ti m i n g; Table 5-2 Example Baud Rate Settings for the UART Mode
  • Page 131 – UA RT M o d e Ti m i n g; Figure 5-6 Synchronous Serial Reception Timing
  • Page 132 – S e r i a l I n t e r f a c e S e t u p E x a m p l e s; S e t t i n g U p UA RT Tr a n s m i s s i o n U s i n g S e r i a l I n t e r f a c e 0; -bit character length
  • Page 136 – S e t t i n g U p t h e S e r i a l I n t e r f a c e C l o ck; UART interface by using timer 1 to divide B; Transfer clock = baud rate x 8; This means that the timer 1 underflow must be divided by 39.; Figure 5-11 Block Diagram of Serial Interface Clock
  • Page 137 – Figure 5-12 shows an example timing chart.; Figure 5-12 Serial Interface Clock Timing
  • Page 138 – S e t t i n g U p I; timer 0 underflow rate divided by 8 as the clock source.; output. The SBO0 pin begins data output to the I
  • Page 139 – Figure 5-13 shows an example timing chart.
  • Page 140 – To set up the I; To set up data reception:
  • Page 141 – S e r i a l I n t e r f a c e C o n t r o l R e g i s t e r s; S e r i a l I n t e r f a c e C o n t ro l R e g i s t e r s; Do not change this bit during transmission or reception.
  • Page 142 – SCnICM: Serial por t n I
  • Page 144 – A n a l o g - t o - D i g i t a l C o n v e r t e r; A n a l o g - t o - D i g i t a l C o nv e r t e r; is 24 MHz, you must set the reference clock to; Figure 6-1 ADC Architecture; Sample; Table 6-1 ADC Functions and Features
  • Page 145 – S e l e c t i n g t h e A D C C l o ck S o u r c e; Calculate the A/D conversion time as follows:; For example, if you set the clock source to B; Figure 6-2 ADC Block Diagram
  • Page 146 – A / D C o n v e r s i o n T i m i n g; S i n g l e C h a n n e l / S i n g l e C o nve r s i o n Ti m i n g; version, then clears to 0 when the conversion ends.; M u l t i p l e C h a n n e l / S i n g l e C o nve r s i o n Ti m i n g; Figure 6-4 Single Channel/Single Conversion Timing
  • Page 147 – S i n g l e C h a n n e l / C o n t i n u o u s C o nve r s i o n Ti m i n g; Figure 6-6 Single Channel/Continuous Conversion Timing
  • Page 148 – A D C S e t u p E x a m p l e s; To set up the input port:
  • Page 149 – A/D converter data registers
  • Page 150 – To set up the conversion cycle; Set the TM1LD bit of the TM1MD register to 1 and the TM1EN bit to 0.
  • Page 151 – A D C C o n t r o l R e g i s t e r s; A D C C o n t ro l R e g i s t e r s
  • Page 152 – ANTC: Conversion start at timer 1 underflow; Always set this bit to 0.; 1: Multiple channels, continuous conversion
  • Page 153 – C a u t i o n s a b o u t A n a l o g - t o - D i g i t a l C o n v e r t e r; C a u t i o n s a b o u t A n a l o g - t o - D i g i t a l C o nv e r t e r; accurancy of convension:; or
  • Page 154 – O n - S c r e e n D i s p l a y; This allows you to adjust the memory space to fit your application.; Table 7-1 OSD Functions and Features
  • Page 155 – Figu
  • Page 156 – P o w e r - S a v i n g C o n s i d e r a t i o n s i n t h e O S D B l o c k; This section explains how to use these bits.
  • Page 157 – O S D O p e r a t i o n; section 7 provides more detailed specifications.; O S D C l o ck; OSC clock source; E x t e r n a l I n p u t S y n c S i g n a l s; that you must these parameters separately.; M u l t i - L a y e r Fo r m a t; Text layer
  • Page 158 – O u t p u t P i n S e t u p
  • Page 159 – C o n d i t i o n s fo r V R A M W r i t e s; that order, at the end of the preceding line.
  • Page 160 – S t a n d a r d a n d E x t e n d e d D i s p l a y M o d e s; S t a n d a r d a n d E x t e n d e d D i s p l ay M o d e s; C u r s o r L a y e r D i s p l a y M o d e s; Figure 7-2 Cursor Tiles in Standard and Extended Modes
  • Page 161 – G r a p h i c s L a y e r D i s p l a y M o d e s
  • Page 162 – D i s p l a y S e t u p E x a m p l e s; D i s p l ay S e t u p E x a m p l e s; S e t t i n g U p t h e G r a p h i c s L a y e r; Register settings
  • Page 164 – S e t t i n g U p t h e Te x t L a y e r; This section shows how to set up the text display data in the VRAM.; A CC code must immediately follow a COL code.
  • Page 165 – Figure 7-5 Text Display Example; Display end
  • Page 166 – V R A M; V R A M O p e r a t i o n; Specifies the address of one of 1024 characters stored in the ROM.; CSHAD; Specifies character shadowing for a 3D effect.; FRAME; Table 7-7 VRAM Bit Allocation in Internal RAM
  • Page 168 – CSHT; CVP: Character Vertical Position Control Code; CLAST; Specifies the V size of the characters on the next line.; CINT; Specifies an OSD interrupt.; GCBF
  • Page 169 – GPRT; Specifies graphics color palette 1 or 2.; GSHT; GVP: Graphics Vertical Position Control Code; GLAST; Specifies the V size of the tiles on the next line.; GINT
  • Page 170 – V R A M O r g a n i z a t i o n; Graphics RAM Addresses; Text RAM Addresses
  • Page 172 – C a u t i o n s a b o u t t h e n u m b e r o f d i s p l a y c o d e s e t t o V R A M; the display data of the next line.
  • Page 173 – R O M; RO M O r g a n i z a t i o n; Figure 7-9 ROM Organization; Text ROM Addresses; Text character; Graphics ROM Addresses; Graphics
  • Page 174 – Graphics ROM Organization in Different Color Modes; zation for each color mode.
  • Page 175 – Graphic Tile Codes; colors
  • Page 179 – S e t t i n g U p t h e O S D; . 1 0 S e t t i n g U p t h e O S D; . 1 0 . 1 S e t t i n g U p t h e O S D D i s p l a y C o l o r s; This section describes how to set up the display colors for the OSD.; GPRT (GTC bit 9 in the RAM data) selects tile color palette 1 or 2.
  • Page 180 – FRAME (COL bit 9 in the RAM data) enables character outlining when; This function is unavailable in the closed-caption mode.; BBSHD (x’007FA4’) specifies the “black” color for box shadowing.; To set up functions applying to all layers:
  • Page 181 – : Output color 15 as specified
  • Page 184 – Int ernal DAC; YM; To pins
  • Page 185 – . 1 0 . 2 Te x t L a y e r F u n c t i o n s; Outlining
  • Page 187 – Italics
  • Page 190 – . 1 0 . 4 S e t t i n g U p t h e O S D D i s p l a y Po s i t i o n; To set up the horizontal position:; About the horizontal start position on the screen; of Horizontal Display Position
  • Page 192 – D M A a n d I n t e r r u p t T i m i n g; . 1 1 D M A a n d I n t e r r u p t T i m i n g; DMA; ) after the leading edge of the HSYNC pulse.
  • Page 194 – S e l e c t i n g t h e O S D D o t C l o c k; . 1 2 S e l e c t i n g t h e O S D D o t C l o c k; This section describes how to set up the OSD dot clock.
  • Page 195 – C o n t r o l l i n g t h e S h u t t e r i n g E f f e c t; . 1 3 C o n t r o l l i n g t h e S h u t t e r i n g E f f e c t; The MN102H75K/85K OSD achieves a shuttering effect using four pro-; . 1 3 . 1 C o n t r o l l i n g t h e S h u t t e r e d A r e a; Determining the vertical shutter positions (VST0 and VST1)
  • Page 197 – . 1 3 . 2 C o n t r o l l i n g S h u t t e r M ove m e n t; must reset the bits each time.
  • Page 198 – ABCDE
  • Page 199 – . 1 3 . 3 C o n t r o l l i n g S h u t t e r i n g E ff e c t s; You cannot shutter the cursor layer.; Function
  • Page 200 – CDE
  • Page 201 – . 1 3 . 4 C o n t r o l l i n g L i n e S h u t t e r i n g; To disable shuttering on the next line:; Figure 7-35 Line Shuttering Setup Example; ABCDEFG
  • Page 202 – F i e l d D e t e c t i o n C i r c u i t; . 1 4 F i e l d D e t e c t i o n C i rc u i t; Figure 7-36 Field Detection Circuit Block Diagram
  • Page 203 – . 1 4 . 3 C o n s i d e r a t i o n s fo r I n t e r l a c e d D i s p l a y s; following two bits to have the display start at field 2.
  • Page 204 – O S D R e g i s t e r s; . 1 5 O S D R e g i s t e r s; CROMEND: Text ROM End Address Register
  • Page 205 – SPRT0: Cursor 0 color palette select; SPRT1: Cursor 1 color palette select; Use the same ROM data as that used for the graphics.; SPRT2: Cursor 2 color palette select; Use the same ROM data as that used for the graphics.
  • Page 206 – : Graphics color palette 1
  • Page 207 – : Shutter control on; CISHT: Graphics initial shutter control
  • Page 210 – SPEXT: Cursor extended mode select; Specifies translucency for color 15 in all palettes.; COLB: Color background control
  • Page 213 – SHTC: Shutter Control Register
  • Page 217 – I R R e m o t e S i g n a l R e c e i v e r; block in the circuit and describes the operation of the receiver.; is formed by dividing PWM3 by the value
  • Page 219 – I R R e m o t e S i g n a l R e c e i v e r O p e r a t i o n; O p e r a t i n g M o d e s; interrupt status register, RMIS, monitors the operating mode.; N o i s e Fi l t e r; Figure 8-2 IR Remote Signal Noise Filtering
  • Page 220 – - B i t D a t a R e c e p t i o n; Figure 8-3 Reception of 8-Bit Data with No Leader
  • Page 221 – I d e n t i f y i n g t h e D a t a Fo r m a t
  • Page 222 – G e n e r a t i n g I n t e r r u p t s; . Bits 3 to 0 of the RMIR register control the interrupt; Figure 8-6 Pin Edge Detection; RMIN input; Edge detection output
  • Page 223 – C o n t r o l l i n g t h e S L OW Mo d e
  • Page 224 – I R R e m o t e S i g n a l R e c e i v e r C o n t r o l R e g i s t e r s; is f; divided by 2
  • Page 227 – SP and SPSLW: Switch clock frequencies; This 4-bit setting must be between 0 and 60 T; LONGDF: Long data format detection; Set to 1 when long data is detected.; SHORTDF: Short data format detection; Set to 1 when short data is detected.
  • Page 228 – C l o s e d - C a p t i o n D e c o d e r; Table 9-1 Pins Used for CCD0 and CCD1
  • Page 229 – F u n c t i o n a l D e s c r i p t i o n; A n a l o g - t o - D i g i t a l C o nve r t e r; Figure 9-2 Recommended ADC Configuration; VREFHS
  • Page 230 – C l a m p i n g C i r c u i t
  • Page 231 – See the page number indicated for register and bit descriptions.; S y n c S e p a r a t o r C i r c u i t; Register for selecting the low-pass filter
  • Page 234 – D a t a S l i c e r; Figure 9-8 VSYNC Masking
  • Page 235 – the page number indicated for register and bit descriptions.; C o n t r o l l e r a n d S a m p l i n g C i r c u i t; Registers for detecting CRI and generating sampling clock
  • Page 237 – C l o s e d - C a p t i o n D e c o d e r R e g i s t e r s
  • Page 238 – FCCNT: VBI Decoding Format Select Register; FCPSEL: Hard/soft sampling start position select; When this field is unused, tie it to b’00’.; SLPULSEL: Polarity select for the CRI cycle transition detection; : CRI capture interval only; NCRIGSEL: Sampling pulse generation interval
  • Page 240 – SBFLAG: Start bit detection flag; ACQ1: ACQ Capture Timing Control Register 1
  • Page 243 – MING: Output select for noise filter detecting minimum sync tip
  • Page 246 – SAFE: Clamping current source select; Figure 9-15 BSP and PSP Multiplexing
  • Page 247 – ODDEVEN: Field detection signal; HLOCKLV: Sync Separator Detection Control Register 1
  • Page 250 – P u l s e W i d t h M o d u l a t o r; 0 P u l s e W i d t h M o d u l a t o r; 0 . 1 D e s c r i p t i o n; with a minimum pulse width of 16/f; Output Wave
  • Page 251 – 0 . 2 B l o ck D i a g r a m; , and they set to 1 when PWM output is high.; Output pulse cycle = 2; Figure 10-2 PWM Block Diagram
  • Page 252 – 1 . 1 D e s c r i p t i o n
  • Page 253 – 1 . 2 I / O Po r t C i r c u i t D i a g r a m s
  • Page 259 – To use as SBT1,set P2MD8 and P2MD9 to 0.
  • Page 278 – 1 . 3 I / O Po r t C o n t ro l R e g i s t e r s; : Pullup resistor off
  • Page 279 – P0IN – P5IN: Ports 0–5 Input Registers; P0DIR – P5DIR: Ports 0–5 I/O Control Registers
  • Page 281 – P1MD: Port 1 Output Mode Register
  • Page 283 – P3MD: Port 3 Output Mode Register; This bit exists, but contains no function.
  • Page 285 – P5MD: Port 5 Output Mode Register
  • Page 286 – ODASCI1: Serial port 1 output switch
  • Page 288 – P7P8CNT: Por ts 7 and 8 forced pullup; Ports 7 and 8 are only available in the quad flat package.; C function enable; ply to the associated block, which reduces power dissipation.
  • Page 289 – R O M C o r r e c t i o n; 2 RO M C o r r e c t i o n; 2 . 1 D e s c r i p t i o n; designated addresses.; CPU; Start
  • Page 290 – 2 . 2 B l o ck D i a g r a m; Figure 12-3 ROM Correction Block Diagram
  • Page 291 – R O M C o r r e c t i o n C o n t r o l R e g i s t e r s; 2 . 4 R O M C o r r e c t i o n C o n t r o l R e g i s t e r s; ROMCEN15: Address 15 ROM correction enable
  • Page 294 – C B u s C o n t r o l l e r; 3 . 1 D e s c r i p t i o n; C bus controller, fully compliant with the
  • Page 295 – Figure 13-2 shows an example of an I
  • Page 296 – A. Master Transmitter; C Bus Interface Operation
  • Page 297 – 3 . 2 B l o ck D i a g r a m; The I; C sequence controller
  • Page 299 – S e t t i n g U p t h e I; 3 . 4 S e t t i n g U p t h e I; Circuit
  • Page 300 – S D A a n d S C L W a v e f o r m C h a r a c t e r i s t i c s; 3 . 5 S DA a n d S C L Wav e f o r m C h a r a c t e r i s t i c s
  • Page 301 – C I n t e r f a c e S e t u p E x a m p l e s; 3 . 6 . 1 S e t t i n g U p a Tr a n s i t i o n f r o m M a s t e r Tr a n s m i t t e r t o M a s -; To enable I
  • Page 302 – The circled areas are signals output from the MN102H75K/85K.
  • Page 303 – 3 . 6 . 2 S e t t i n g U p a Tr a n s i t i o n f r o m S l a ve R e c e i ve r t o S l a ve
  • Page 305 – C B u s I n t e r f a c e R e g i s t e r s; All registers in I; C Transmission Data Register; ferent start and stop conditions.; ACK: Acknowledge signal output control; C bus. It is shifted out MSB first to the interface.
  • Page 307 – C Clock Control Register; In this case, the following settings apply:; C Bus Reset Register; C bus. This function works in all I; C Bus Status Register; SCLS: SCL clock line status; This bit monitors the state of the I
  • Page 308 – H C o u n t e r; 4 H C o u n t e r; 4 . 1 D e s c r i p t i o n; Figure 14-1 H Counter Block Diagram; In this example, HI0 is active high and VSYNC is active low.; Figure 14-2 H Counter Operation Example
  • Page 309 – H C o u n t e r O p e r a t i o n; input a count source signal in less than 245 ns (t
  • Page 311 – H C o u n t e r C o n t r o l R e g i s t e r s; 4 . 4 H C o u n t e r C o n t r o l R e g i s t e r s; HCCNT0: H Counter Control Register 0; SEDG0: Polarity select for reset signal; SEDG1: Polarity select for reset signal; All other settings default to 1024 μs.
  • Page 313 – R e g i s t e r M a p; A p p e n d i x A R e g i s t e r M a p; MSBs
  • Page 317 – M N 1 0 2 H F 7 5 K F l a s h E E P R O M V e r s i o n; A p p e n d i x B M N 1 0 2 H F 7 5 K F l a s h E E P RO M Ve r s i o n; is overwritten in PROM writer mode.; Figure B-1 Memory Map for Onboard Serial Programming Mode
  • Page 318 – B e n e f i t s; to the microcontroller pin states.
  • Page 319 – U s i n g t h e P R O M W r i t e r M o d e
  • Page 320 – U s i n g t h e O n b o a r d S e r i a l P r o g r a m m i n g M o d e; Onboard serial writer; Television set
  • Page 321 – C on figu rin g th e S ys tem for O nb oa rd Se ria l P ro gra m m ing; source to the target board. The serial writer supplies; Model: AF200 flash microcontroller programmer; Target board
  • Page 322 – C i r c u i t R e q u i r e m e n t s fo r t h e Ta r g e t B o a r d; Install a switch on the target board to toggle between V; supplied by the; for normal operation.; Figure B-6 Target Board – Serial Writer Connection; During normal microcontroller operation, V; should always be equal to; supply only when programming
  • Page 324 – Do not write to this area.
  • Page 325 – interrupt service routine.; M i c r o c o n t r o l l e r C l o c k o n t h e Ta r g e t B o a r d
  • Page 326 – S e t t i n g U p t h e O n b o a r d S e r i a l P r o g r a m m i n g M o d e; To set up the serial writer interface:; SBT goes high on microcontroller power-up, for t
  • Page 327 – Reset start
  • Page 328 – B r a n ch i n g t o t h e U s e r P r o g r a m; B . 4 . 7 . 1 B r a n c h i n g t o t h e R e s e t S t a r t R o u t i n e
  • Page 329 – R e p r o g r a m m i n g F l o w; R e p ro g r a m m i n g F l o w; Times indicated are minimum time requirements.
  • Page 332 – Pin Descriptions
  • Page 337 – LSI User’s Manual
  • Page 338 – SALES OFFICES; NORTH AMERICA
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MICROCOMPUTER

MN102H

MN102H75K/F75K/85K/F85K

LSI User’s Manual

Pub.No.22385-011E

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Summary

Page 3 - and semiconductors described in this book; of patents or any other rights owned by a third party.

PanaXSeries is a trademark of Matsushita Electric Industrial Co., Ltd.The other corporation names, logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations. Request for your special attention and precautions in using the technical in...

Page 4 - M N 1 0 2 H 7 5 K / F 7 5 K L S I U s e r M a n u a l; C o n t e n t s

C o n t e n t s M N 1 0 2 H 7 5 K / F 7 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 3 Panasonic C o n t e n t s About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5 - P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y; Setting Up I

C o n t e n t s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K L S I U s e r M a n u a l 4 Panasonic 4.5.1 Setting Up an Event Counter Using Timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4...

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