Intel SDS2 - Manual

Intel SDS2

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Table of Contents:

  • Page 2 – Revision History
  • Page 3 – iii; Disclaimers; *Other brands and names may be claimed as the property of others.
  • Page 4 – Table of Contents
  • Page 8 – run
  • Page 10 – List of Figures
  • Page 11 – List of Tables
  • Page 15 – Figure 1. SDS2 Server Board Block Diagram
  • Page 17 – Dual Channel Wide Ultra160 SCSI controller: Adaptec* AIC-7899W
  • Page 18 – Processor and Chipset; The SDS2 Server Board supports two Intel; Table 1. SDS2 Intel® Pentium® III Processor Support Matrix
  • Page 20 – Processor Voltage Regulator Module (VRM); Memory Subsystem; Memory Configuration
  • Page 21 – DIMM Pair 1; Figure 2. SDS2 Memory Bank Layout
  • Page 22 – C Bus; An I; C Addresses for DIMM Slots; The HE-SL North Bridge is responsible for
  • Page 23 – CNB20HE-SL Champion North Bridge
  • Page 24 – CIOB20 Champion I/O Bridge; P64-C supports the following embedded devices and connectors:; CSB5 South Bridge; Please refer to Section 4.5 for information on CSB5.
  • Page 25 – D/3D Graphics Accelerator: ATI RAGE XL Video Controller
  • Page 26 – Intel® Server Board SDS2; All PCI masters must arbitrate for PCI access, using resources
  • Page 27 – All PCI
  • Page 28 – Zero Channel RAID (ZCR) Capable PCI Slot 6; Zero Channel Raid Cards (ZCR) cards are only supported on PCI slot 6.; Video Controller; Video Modes
  • Page 29 – The 82550 supports the following features:
  • Page 30 – NIC Connecto r and Status LEDs; PCI; PCI Bus Master IDE Interface
  • Page 31 – USB Interface; Many of these pins have; Table 10. CSB5 GPIO Usage Table
  • Page 32 – Chipset Support Components; GPIO; General Purpose Input and Output - GPIO
  • Page 33 – Serial Ports
  • Page 34 – BIOS Flash; Interrupt Routing; Legacy Interrupt Routing; Table 13. Interrupt Definitions
  • Page 35 – APIC Interrupt Routing
  • Page 37 – Serialized IRQ Interface
  • Page 39 – Server Management
  • Page 40 – Figure 6. SDS2 Sahalee BMC Block Diagram (View as Reference Only)
  • Page 41 – Sahalee Baseboard Management Controller
  • Page 43 – SDS2 Baseboard Management; Figure 7. SDS2 Locations of ADM1026 and Sahalee; Fault Resilient Booting
  • Page 44 – System Reset Control; Hard Reset; Intelligent Platform Management Buses; C Bus Specification
  • Page 45 – C busses. Four of these
  • Page 46 – Error Reporting; Error Sources and Types; PCI bus; PCI Bus Errors
  • Page 47 – Memory Bus Errors; ACPI requires an operating system that supports this feature.
  • Page 49 – Advanced
  • Page 50 – BIOS Error Handling; Logging Format Conventions
  • Page 52 – SMI Handler; Set NMI Source; PCI Bus Error
  • Page 53 – Intelligent; Table 24 Platform SEL Log Sensors for SDS2
  • Page 58 – Timestamp Clock; Get SEL Time
  • Page 59 – Error Messages and Error Codes; ASF Progress Codes; Table 25. Event Request Message Event Data Field Contents; POST Codes
  • Page 60 – One to four beeps are generated based on each group’s 2-bit pattern.; Table 27. Standard BIOS POST Codes
  • Page 64 – POST Error Codes and Messages; Table 29. POST Error Messages and Codes
  • Page 65 – Baseboard Management Controller (BMC) Beep Code Generation; Table 30. BMC Beep Code s
  • Page 66 – Setup utility operation.; Configuration Utilities Overview; The ROM-resident Setup utility configures only on-board devices.; Table 31. Setup Utility Screen
  • Page 67 – Entering Setup Utility
  • Page 69 – Menu Selection Bar; These and associated submenus are described below.; Table 32. Main Menu Selections
  • Page 72 – Advanced Menu Selections; Table 35. Advanced Menu Selections
  • Page 76 – Security Menu Selections; Table 44. Security Menu Selections
  • Page 77 – Server Menu Selections; Table 45. Server Menu Selections
  • Page 79 – Boot Menu Selections; Table 48. Boot Device Priority Selections
  • Page 80 – Exit Menu Selections; Table 51. Exit Menu Selections
  • Page 81 – CMOS Memory Definition; Flash Update Utility; Loading the System BIOS; On-board Video BIOS and SCSI BIOS
  • Page 82 – User Binary Area; release notes. Failure to do so will cause the process to fail.; Performing BIOS Recovery; Move the BIOS recovery jumper to the recovery position.
  • Page 83 – When the flash update completes:
  • Page 84 – Clock/Voltage Generation and Distribution; Clock
  • Page 86 – VCORE for the CPUs
  • Page 87 – Power Supply
  • Page 88 – Power Distribution Board Connector; without +12 V Power supplied to this connector.
  • Page 89 – Memory Module Connector; PC SDRAM Registered
  • Page 90 – System Management Headers; ICMB Connector; Intelligent Chassis Management Bus, Version 1.0; OEM IPMB Connector
  • Page 91 – Front Panel Header
  • Page 92 – PCI Slot Connector
  • Page 94 – VGA Connector
  • Page 95 – NIC Connectors
  • Page 96 – IDE Connector
  • Page 97 – Pin 9 GND; Floppy Connector
  • Page 98 – Serial Port Connector
  • Page 99 – Parallel Port
  • Page 100 – Miscellaneous Headers; Fan Headers; Table 75. Chassis Intrusion Header Pin-out; External SCSI Activity LED Input Signal Connector
  • Page 101 – Connector Manufacturers and Part Numbers; Table 77. Server Board Connector Manufacturer Part Numbers
  • Page 102 – System Configuration Jumpers; This section describes jumper options on the Server Board.
  • Page 103 – The following figure details the locations of these jumpers.
  • Page 104 – Figure 12. SDS2 Configuration Jumper Locations
  • Page 105 – The following tables describe each jumper options.; Table 78. System Configuration Jumper Options; Table 79. CPU Frequency Select Jumper Options
  • Page 106 – Update; Performing CMOS Clear; Clear CMOS as follows.; Performing BIOS Recovery Boot; Server Board obtained from Intel’s web sites.
  • Page 107 – Insert the BIOS Recovery floppy diskette into the disk drive.; Performing BMC Force Update; SDS2 Server Board obtained from Intel’s web sites.
  • Page 108 – Electrical and Thermal Specifications; Absolute Maximum Ratings; Table 81. Absolute Maximum Ratings; Power Consumption; Two processors, each with 30 W max
  • Page 109 – Power Supply Specification; Table 83: SDS2 Power Supply Specification; Power Timing; ) of each other and begin to turn off within 400 ms (T; Table 84: Voltage Timing Parameters
  • Page 111 – Estimateded Server Board MTBF
  • Page 112 – Mechanical Specifications; The following figure shows the Server Board mechanical drawing.; Figure 15. SDS2 Server Board Mechanical Drawing
  • Page 113 – Regulatory and Integration Information; Regulatory Compliance; Table 88. Safety Regulations; Table 89. EMC Regulations
  • Page 114 – Installation Instructions; this board assembly.; Ensure EMC; External I/O cable shielding and filtering.
  • Page 115 – Ensure Host Computer and Accessory Module Certifications; Europe; Prevent Power Supply Overload; Danger of explosion if battery is incorrectly replaced.
  • Page 116 – Use Only for Intended Applications; Sharp pins on connectors.; External ICMB Cable Information; IPMI Intelligent; Table 90. ICMB External Cable Connectors
  • Page 117 – Summary Errata Table; This erratum has been previously fixed.; Table 91. Errata Summary
  • Page 120 – Updating the FRU and Sensor Data Records
  • Page 121 – Boot-Time Diagnostic Screen option to; Intel® Server Board SDS2 C D-ROM issues; Editing a file with the DOS “Edit” command after booting to the SDS2
  • Page 122 – On the Utilities page, drop down the menu and choose the Platform
  • Page 123 – Extended RAM Step disable option in BIOS Setup has no effect; Setting the Intel® Server Board SDS2 BIOS Setup Advanced; High resolution video modes do not work correctly
  • Page 124 – Lower performance with CAS Latency 2 memory
  • Page 125 – Memory; Adaptec* 2100S RAID controller causes system lockup and
  • Page 126 – SDS2 0B71: System Temperature out of the range POST
  • Page 127 – SDS2 0B75: System Voltage out of the range POST message; System Monitoring Check; Miscellaneous numeric keys entered during POST enable PXE
  • Page 128 – SDS2 board level operating temperature and power supply
  • Page 129 – For the Intel SC5100 chassis:
  • Page 130 – Figure 1. Placing the Rubber Bumper in the Chassis; Keyboard and Mouse do not function under Microsoft*
  • Page 131 – Data miscompares when using Seagate* ATA III model; None; Potential Mylex AcceleRAID 352 Adaptor Card Mechanical
  • Page 132 – Bootable CD will not boot if inserted during OPTION ROM scan
  • Page 133 – OB P100 NICs do not show at POST but attempt PXE boot and
  • Page 134 – Can Not Change BIOS SETUP IDE Options Using Key
  • Page 135 – screen when greater than 4GB of system memory is installed
  • Page 136 – Peer-to-peer PCI transactions are not supported between the
  • Page 138 – Glossary
  • Page 140 – Documents; Reference Documents
  • Page 141 – Index; BIOS LCD
  • Page 142 – Get SDR Time
  • Page 143 – III; See
  • Page 144 – Sensor Event
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Intel® Server Board SDS2

Technical Product Specification

Order Number: A85874-002

Revision 1.2

December 2, 2002

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Summary

Page 2 - Revision History

Revision History Intel® Server Board SDS2 Revision 1.2 Order Number: A85874-002 ii Revision History Date Revision Number Modifications 9/20/2001 1.0 Initial release. 5/15/2002 1.1 Added Section 13: Errata. Corrected miscellaneous document errors. Added Table 6.2.5.4: Baseboard Management Controller ...

Page 3 - iii; Disclaimers; *Other brands and names may be claimed as the property of others.

Intel® Server Board SDS2 Disclaimers Revision 1.2 Order Number: A85874-002 iii Disclaimers Information in this document is provided in connection with Intel ® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except a...

Page 4 - Table of Contents

Table of Contents Intel® Server Board SDS2 Revision 1.2 Order Number: A85874-002 iv Table of Contents 1. Introduction .............................................................................................................................1 2. Architecture ..........................................

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