Intel MPCBL0001 - Manual

Intel MPCBL0001

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Table of Contents:

  • Page 3 – Contents
  • Page 8 – Tables
  • Page 11 – Figures
  • Page 12 – Revision History
  • Page 13 – Introduction; Document Organization
  • Page 14 – Glossary
  • Page 16 – Features Overview; Application; Functional Description
  • Page 19 – Chipset; Intel
  • Page 21 – Memory Ordering Rule for the MCH
  • Page 22 – Memory Ordering
  • Page 23 – Timer0 Capabilities
  • Page 26 – Flash ROM Backup Mechanism
  • Page 27 – Onboard Power Supplies; Power Feed Fuses
  • Page 28 – IPMB
  • Page 29 – Hardware Management Overview; Hardware Management Block Diagram
  • Page 36 – Temperature and Voltage Sensors; SEL Events Supported by the MPCBL0001 SBC (Sheet 4 of 4)
  • Page 41 – Processor Events; Critical Interrupts
  • Page 42 – PCI Mapping for Hardware Component Subsystem
  • Page 43 – System ACPI Power State; IPMB Link Sensor
  • Page 44 – Port 80h POST Codes; CPU Failure Behavior
  • Page 46 – IPMC Firmware Code; Link Descriptors for E-Keying
  • Page 47 – IPMC Firmware Upgrade Procedure; IPMC Firmware Upgrade Using KCS Interface; IPMC Firmware Code Process
  • Page 48 – IPMC Firmware Upgrade via the IPMB Interface (RMCP); Updating MPCBL0001 Firmware; OEM IPMI Commands; Upgrade via Remote Management Node
  • Page 49 – Reset BIOS Flash Type
  • Page 50 – Get HW Fibre Channel Port Selection; Get Fibre Channel Port Selection
  • Page 52 – Get Port80 Data; Controls Identifier Table; Get Control State
  • Page 54 – Ejector Mechanism
  • Page 55 – Interrupts and Error Reporting; Device Interrupts
  • Page 57 – Error Reporting
  • Page 58 – ACPI; System States and Power States; Reset Types; Power States and Targeted System Power
  • Page 59 – Reset Logic; Soft Reset Request
  • Page 60 – Warm Boot
  • Page 61 – Cold Boot; Power Good; Power Good Map
  • Page 64 – Watchdog Timers
  • Page 66 – Health LED
  • Page 67 – IDE Drive Activity LED
  • Page 68 – Network Link/Speed LEDs; Network Link LEDs
  • Page 69 – Fibre Channel Port State LEDs; Ethernet Controller Port State LED
  • Page 70 – FRU Payload Control; Cold Reset; Warm Reset; Graceful Reboot; CMM Commands for FRU Control Options
  • Page 71 – Diagnostic Interrupt; Flow Diagram for Graceful Reboot Command
  • Page 72 – Serial Port Buffering Overview; Diagnostic Interrupt Command Implementation
  • Page 73 – Using Serial Port Buffering; Configuring the Serial Port; Escape Sequences Not Buffered with Filter Enabled
  • Page 76 – Configuration of Buffering/Filtering
  • Page 77 – Examples
  • Page 80 – Connectors; MPCBL0001 SBC Connector Locations
  • Page 84 – Backplane Connectors; Power Distribution Connector (Zone 1) P10
  • Page 85 – Power Distribution Connector (Zone 1) P10 Pin Assignments
  • Page 86 – Alignment Blocks; Data Transport Connector (Zone 2) P23 Pin Assignments
  • Page 87 – Front Panel Connectors
  • Page 90 – Fibre Channel SFP Optical Transceiver Module
  • Page 91 – Fibre Channel SFP Pin Assignments
  • Page 95 – Addressing; Configuration Registers; Configuration Address Register MCH CONFIG_ADDRESS; Configuration Data Register MCH CONFIG_ADDRESS; Configuration Address Register Bit Assignments
  • Page 96 – I/O Address Assignments; Configuration Data Register Bit Assignments
  • Page 97 – Memory Map
  • Page 98 – IPMC Addresses; SMBus Addresses
  • Page 99 – Specifications; Mechanical Specifications; Board Outline
  • Page 102 – Backing Plate
  • Page 107 – Mean Time Between Failure (MTBF) Specifications; Environmental Specifications; Reliability Estimate Data
  • Page 108 – Environmental Assumptions; Power Consumption; Total Measured Power
  • Page 109 – Cooling Requirements; Board Layer Specifications
  • Page 110 – BIOS Features; BIOS Flash Memory Organization; Copying and Saving CMOS Settings
  • Page 111 – Redundant BIOS Functionality
  • Page 112 – Legacy USB Support
  • Page 113 – Language Support; Recovering BIOS Data; CD-ROM and Network Boot; Booting without Attached Devices
  • Page 114 – Fast Booting Systems; Quick Boot; BIOS Security Features
  • Page 115 – Remote Access Configuration; Supervisor and User Password Functions
  • Page 116 – BIOS Setup; Main Menu; BIOS Setup Program Menu Bar
  • Page 117 – Advanced Menu
  • Page 118 – CPU Configuration Submenu
  • Page 119 – IDE Configuration Submenu
  • Page 120 – Primary IDE Master/Slave Submenu
  • Page 122 – Floppy Configuration Submenu
  • Page 123 – SuperIO Configuration Submenu
  • Page 124 – ACPI Configuration Submenu
  • Page 125 – Advanced ACPI Configuration Submenu
  • Page 126 – System Management Configuration Submenu
  • Page 127 – Event Logging Configuration Submenu
  • Page 128 – Fibre Channel Routing (PICMG) Configuration Submenu
  • Page 129 – Remote Access Configuration Submenu; Remote Access Configuration Submenu (Sheet 1 of 2)
  • Page 130 – Remote Access Configuration Submenu (Sheet 2 of 2); USB Configuration Submenu
  • Page 132 – PCI Configuration; USB Mass Storage Device Configuration
  • Page 133 – Boot Settings Configuration Submenu; PCI Configuration Submenu; Boot Menu
  • Page 134 – Boot Device Priority Submenu
  • Page 135 – Hard Disk Drive Submenu; Hard Disk Drive Priority Submenu
  • Page 136 – Security Menu
  • Page 138 – Error Messages; BIOS Error Messages
  • Page 139 – Bootblock Initialization Code Checkpoints
  • Page 142 – ACPI Runtime Checkpoints; BIOS Beep Codes
  • Page 143 – Operating the Unit; BIOS Configuration; BIOS Image Updates; Copying BIOS.bin from the SBC
  • Page 144 – Saving BIOS.bin to the SBC
  • Page 145 – BIOS Utility Command Line Options
  • Page 147 – Jumpers; Jumper/Connector Locations
  • Page 149 – Digital Ground to Chassis Ground Connectivity; J40 Jumper Assignments
  • Page 151 – References; SOL Architecture
  • Page 152 – SOL Block Diagram
  • Page 153 – Architectural Components; Ethernet Controller; BIOS; Serial Console Redirection over Front Panel and LAN
  • Page 154 – Theory of Operation; Front Panel Serial Port
  • Page 155 – Utilities
  • Page 156 – Supported Usage Model; Configuring the Blade for SOL; Reference Script Running on Remote Node, Communicating over LAN
  • Page 157 – Installation and Configuration
  • Page 158 – HostIP; Password; BIOS and OS Configuration; Default Behavior
  • Page 159 – SOL User Information; IPMI V2.0 Set LAN Configuration Parameters Command Settings
  • Page 160 – SOL Parameters; SOL Configuration Reference Script Command-line Options
  • Page 161 – Operating Environment
  • Page 162 – Maintenance; Supervision; Hardware Monitoring Components
  • Page 163 – Thermals
  • Page 164 – Component Technology; Main Components
  • Page 165 – Warranty Information
  • Page 166 – For the Americas
  • Page 168 – Customer Support; Sales Assistance; MPCBL0001 Product Code Summary
  • Page 169 – Certifications
  • Page 170 – Agency Information—Class A; FCC Verification Notice; English
  • Page 171 – French; Taiwan Class A Warning Statement
  • Page 172 – Japan VCCI Class A
  • Page 173 – Agency Information—Class B
  • Page 174 – Japan VCCI Class B
  • Page 175 – Korean Class B
  • Page 176 – Safety Warnings; RACK MOUNT ENCLOSURE SAFETY:; Warning: Verify power cord and outlet compatibility:
  • Page 177 – Mesures de Sécurité
  • Page 178 – Avertissement : évitez les chocs électriques.; Attention : exigences environnementales du système :
  • Page 179 – Sicherheitshinweise; SICHERHEITSWARNUNG FÜR WECHSELSTROM UND/ODER GLEICHSTROM:
  • Page 181 – Norme di Sicurezza
  • Page 183 – Instrucciones de Seguridad; AVISO DE SEGURIDAD SOBRE LA ALIMENTACIÓN DE CA O CC; Advertencia: Compatibilidad del cable y la toma:
  • Page 185 – Chinese Safety Warning
  • Page 186 – Reference Documents
  • Page 192 – PICMG 3.0 IPMI Supported Commands
  • Page 194 – Material Declaration Data Sheets
  • Page 195 – Material Declaration Data Sheet
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Intel NetStructure

®

MPCBL0001

High Performance Single Board
Computer

Technical Product Specification

May 2006

Order Number: 273817-010

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Summary

Page 3 - Contents

Technical Product Specification 3 Order #273817 Intel NetStructure ® MPCBL0001 High Performance Single Board Computer Contents Contents 1 Introduction .................................................................................................................................... 131.1 Document O...

Page 8 - Tables

8 Technical Product Specification Order #273817 Intel NetStructure ® MPCBL0001 High Performance Single Board Computer Contents 17 Certifications ................................................................................................................................ 169 18 Agency Information—...

Page 11 - Figures

Technical Product Specification 11 Order #273817 Intel NetStructure ® MPCBL0001 High Performance Single Board Computer Contents Figures 1 Block Diagram ............................................................................................................................ 17 2 Memory Ordering .....

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