Intel LXD386 - Manual

Table of Contents:

• Page 3 – Contents; General Description
• Page 4 – Evaluation Board Schematics; Figures
• Page 5 – Evaluation Board for Quad T1/E1 Applications — LXD386; Developer Manual; Features
• Page 6 – LXD386 — Evaluation Board for Quad T1/E1 Applications
• Page 7 – Overview; The evaluation board kit contains the following components:; Equipment Requirements; Windows 9x is recommended.; Control Modes
• Page 8 – Factory Settings
• Page 9 – Hardware Mode Set-Up and Operation; Power Connections; To enable the Hardware mode of operation:; Loopback Mode Selection; Table 1; Clock Edge Selection
• Page 10 – Output Enable Selection; JA disabled = center
• Page 11 – Line Buildout Selection; . Jumper block JP5 is used to; Figure 2. Default Switch Settings; Table 2. JP5 Jumper Settings
• Page 12 – JTAG Boundary Scan Port; The eight pin connector JP2 shown in; Framer/ASIC Connection; Figure 5; Figure 3. Jumper Block JP5
• Page 13 – LED Indicators; input resistors. This protection is sufficient for G.703 Annex B; Figure 5. Jumper Block JP 31
• Page 14 – Software Mode Set-Up and Operation; i8051 Microcontroller Board; — HIGH for parallel mode (factory default); Test Equipment Connections; Connect power supply as described in
• Page 15 – Evaluation Board Software; Figure 6; Quitting the Program
• Page 16 – Configuration Screen; The configuration screen shown in; Communications Modes; “Evaluation Board Set-up” on page 14; Registers; “Registers” on page 16; Setting Individual Transceiver Operating Modes
• Page 17 – Apply to all Channels; Figure 7. Configuration Screen
• Page 18 – Registers Screen; Setting Registers; The Registers screen (see in; Status Indicators; Figure 8; Reset
• Page 20 – Figure 9. Evaluation Board Schematic — Data/Control