Intel 80C196NU - Manual

8XC196NP, 80C196NU USER ’S MANUAL iv CHAPTER 3 ADVANCED MATH FEATURES 3.1 ENHANCED MULTIPLICATION INSTRUCTIONS ........................................................ 3-1 3.2 OPERATING MODES.................................................................................................... 3-2 3.2....

vii CONTENTS 7.3.1.4 Open-drain Output Mode ................................................................................... 7-14 7.3.1.5 Input Mode ......................................................................................................... 7-16 7.3.2 Configuring EPORT Pins ...........

8XC196NP, 80C196NU USER ’S MANUAL viii 10.2 EPA AND TIMER/COUNTER SIGNALS AND REGISTERS ....................................... 10-2 10.3 TIMER/COUNTER FUNCTIONAL OVERVIEW........................................................... 10-5 10.3.1 Cascade Mode (Timer 2 Only) ................................

ix CONTENTS 12.3 IDLE MODE ................................................................................................................. 12-5 12.4 STANDBY MODE (80C196NU ONLY) ........................................................................ 12-6 12.4.1 Enabling and Disabling Standby Mode...

xi CONTENTS FIGURES Figure Page 2-1 8XC196NP and 80C196NU Block Diagram ................................................................. 2-2 2-2 Block Diagram of the Core ........................................................................................... 2-3 2-3 Clock Circuitry (8XC196NP) ....

8XC196NP, 80C196NU USER ’S MANUAL xii FIGURES Figure Page 8-5 Serial Port Frames in Mode 2 and 3 ............................................................................. 8-7 8-6 Serial Port Control (SP_CON) Register........................................................................ 8-9 8-7...

xiii CONTENTS FIGURES Figure Page 13-7 Chip Configuration 1 (CCR1) Register .....................................................................13-16 13-8 Multiplexing and Bus Width Options .........................................................................13-19 13-9 Bus Activity for Four Typ...

8XC196NP, 80C196NU USER ’S MANUAL xiv TABLES Table Page 1-1 Handbooks and Product Information ............................................................................ 1-6 1-2 Application Notes, Application Briefs, and Article Reprints .......................................... 1-6 1-3 MCS ® 96 M...

xv CONTENTS TABLES Table Page 7-9 EPORT Pins ............................................................................................................... 7-11 7-10 EPORT Control and Status Registers ........................................................................ 7-12 7-11 Logic Table for...

1-1 CHAPTER 1 GUIDE TO THIS MANUAL This manual describes the 8XC196NP and 80C196NU embedded microcontrollers. It is intendedfor use by both software and hardware designers familiar with the principles of microcontrollers.This chapter describes what you’ll find in this manual, lists other documents t...

1-2 8XC196NP, 80C196NU USER’S MANUAL Chapter 8 — Serial I/O (SIO) Port — describes the asynchronous/synchronous serial I/O (SIO)port and explains how to program it. Chapter 9 —Pulse-width Modulator — provides a functional overview of the pulse width mod-ulator (PWM) modules, describes how to program...

1-3 GUIDE TO THIS MANUAL 1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY The following notations and terminology are used throughout this manual. The Glossary definesother terms with special meanings. # The pound symbol (#) has either of two meanings, depending on thecontext. When used with a signal name...

1-4 8XC196NP, 80C196NU USER’S MANUAL italics Italics identify variables and introduce new terminology. The contextin which italics are used distinguishes between the two possiblemeanings. Variables in registers and signal names are commonly represented byx and y, where x represents the first variabl...

1-5 GUIDE TO THIS MANUAL t Lowercase “t” represents the internal operating period. See “InternalTiming” on page 2-7 for details. units of measure The following abbreviations are used to represent units of measure: A amps, amperes DCV direct current volts Kbytes kilobyteskHz kilohertz k Ω kilo-ohms m...

1-6 8XC196NP, 80C196NU USER’S MANUAL Table 1-1. Handbooks and Product Information Title and Description Order Number Intel Embedded Quick Reference Guide 272439 Solutions for Embedded Applications Guide 240691 Data on Demand fact sheet 240952 Data on Demand annual subscription (6 issues; Windows* ve...

1-8 8XC196NP, 80C196NU USER’S MANUAL Table 1-5. MCS ® 96 Microcontroller Quick References Title and Description Order Number 8XC196KR Quick Reference (includes the JQ, JR, KQ, KR) 272113 8XC196KT Quick Reference 272269 8XC196MC Quick Reference 272114 8XC196NP Quick Reference 272466 8XC196NT Quick Re...

1-9 GUIDE TO THIS MANUAL Page Intentionally Left Blank

1-11 GUIDE TO THIS MANUAL 1.4.4 World Wide Web We offer a variety of information through the World Wide Web (URL:http://www.intel.com/). Se-lect “Embedded Design Products” from the Intel home page. 1.5 TECHNICAL SUPPORT In the U.S. and Canada, technical support representatives are available to answe...

2-1 CHAPTER 2 ARCHITECTURAL OVERVIEW The 16-bit 8XC196NP and 80C196NU CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output (I/O) operations. They share a common architecture andinstruction set with other members of the MCS ® 96 microcontroller family. In additi...

2-3 ARCHITECTURAL OVERVIEW Figure 2-2. Block Diagram of the Core 2.3.1 CPU Control The CPU is controlled by the microcode engine, which instructs the RALU to perform operationsusing bytes, words, or double words from either the 256-byte lower register file or through a win-dow that directly accesses...

8XC196NP, 80C196NU USER’S MANUAL 2-4 2.3.3 Register Arithmetic-logic Unit (RALU) The RALU contains the microcode engine, the 16-bit arithmetic logic unit (ALU), the master pro-gram counter (PC), the processor status word (PSW), and several registers. The registers in theRALU are the instruction regi...

2-5 ARCHITECTURAL OVERVIEW 2.3.3.2 Instruction Format MCS 96 microcontrollers combine a large set of general-purpose registers with a three-operandinstruction format. This format allows a single instruction to specify two source registers and aseparate destination register. For example, the followin...

8XC196NP, 80C196NU USER’S MANUAL 2-6 The extended program counter (EPC) is an extension of the slave PC. The EPC generates the up-per eight address bits for extended code fetches and outputs them on the extended addressing port(EPORT). Because only four EPORT pins are implemented, only the lower fou...

2-7 ARCHITECTURAL OVERVIEW 2.4 INTERNAL TIMING The clock circuitry of the 8XC196NP (Figure 2-3) is identical to that of earlier MCS 96 micro-controllers. It receives an input clock signal on XTAL1 provided by an external crystal or clockand divides the frequency by two. The clock generators accept t...

2-9 ARCHITECTURAL OVERVIEW Figure 2-5. Internal Clock Phases The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basictime unit known as a state time or state. Table 2-2 lists state time durations at various frequencies. The following formulas calculate the frequency...

8XC196NP, 80C196NU USER’S MANUAL 2-10 Figure 2-6. Effect of Clock Mode on CLKOUT Frequency Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times F X TAL 1 (Frequency on XTAL1) PLLEN2:1 Multiplier f (Input Frequency to the Divide-by-two Circuit) t (Clock Period) State Ti...

2-11 ARCHITECTURAL OVERVIEW 2.5 INTERNAL PERIPHERALS The internal peripheral modules provide special functions for a variety of applications. This sec-tion provides a brief description of the peripherals; subsequent chapters describe them in detail. 2.5.1 I/O Ports The 8XC196NP and 80C196NU have fiv...

8XC196NP, 80C196NU USER’S MANUAL 2-12 Timer 1 and timer 2 are both 16-bit up/down timer/counters that can be clocked internally or ex-ternally. Each timer/counter is called a timer if it is clocked internally and a counter if it is clockedexternally. See Chapter 10, “Event Processor Array (EPA),” fo...

2-13 ARCHITECTURAL OVERVIEW 2.6.2 Testing the Printed Circuit Board The on-circuit emulation (ONCE) mode electrically isolates the 8XC196 device from the system.By invoking ONCE mode, you can test the printed circuit board while the device is soldered ontothe board. 2.7 DESIGN CONSIDERATIONS FOR 80C...

3-1 CHAPTER 3 ADVANCED MATH FEATURES The 80C196NU is the first member of the MCS ® 96 microcontroller family to incorporate en- hanced 16-bit multiplication instructions for performing multiply-accumulate operations and adedicated, 32-bit accumulator register for storing the results of these operati...

8XC196NP, 80C196NU USER’S MANUAL 3-2 3.2 OPERATING MODES The accumulator has two operating modes that allow you to control the results of operations onsigned numbers. These modes are called saturation mode and fractional mode. 3.2.1 Saturation Mode Saturation occurs when the result of two positive n...

3-3 ADVANCED MATH FEATURES 3.2.2 Fractional Mode A signed fractional contains an imaginary decimal point between the sign bit (the MSB) and theadjacent bit. These examples illustrate the representation of 32-bit signed fractional numbers: 0.111 1111 1111 1111 1111 1111 1111 1111 0.000 0000 0000 0000...

8XC196NP, 80C196NU USER’S MANUAL 3-4 3.3 ACCUMULATOR REGISTER (ACC_0 x ) The 32-bit accumulator register (Figure 3-1) resides at locations 0C–0FH. Read from or write tothe accumulator register as two words at locations 0CH and 0EH. ACC_0 x x = 0, 2 (80C196NU) Address: Reset State: 0EH, 0CH 00H The 3...

8XC196NP, 80C196NU USER’S MANUAL 3-6 Table 3-2. Effect of SME and FME Bit Combinations SME FME Description 0 0 Sets the OVF and STOVF flags if the sign bits of the accumulator and the addend (the number to be added to the contents of the accumulator) are equal, but the sign bit of the result is the ...

4-1 CHAPTER 4 PROGRAMMING CONSIDERATIONS This section provides an overview of the instruction set of the MCS ® 96 microcontrollers and of- fers guidelines for program development. For detailed information about specific instructions,see Appendix A. 4.1 OVERVIEW OF THE INSTRUCTION SET The instruction...

8XC196NP, 80C196NU USER’S MANUAL 4-2 Table 4-2 lists the equivalent operand-type names for both C programming and assembly lan-guage. 4.1.1 BIT Operands A BIT is a single-bit variable that can have the Boolean values, “true” and “false.” The architec-ture requires that BITs be addressed as component...

4-3 PROGRAMMING CONSIDERATIONS 4.1.4 WORD Operands A WORD is an unsigned, 16-bit variable that can take on values from 0 through 65,535 (2 16 –1). Arithmetic and relational operators can be applied to WORD operands, but the result must be in-terpreted in modulo 65536 arithmetic. Logical operations o...

8XC196NP, 80C196NU USER’S MANUAL 4-6 EST Extended store word. Stores the value of the source (leftmost) word operandinto the destination (rightmost) operand. This instruction allows you to movedata from the lower register file to anywhere in the address space. It operates inextended indirect and ext...

4-7 PROGRAMMING CONSIDERATIONS 4.2.1 Direct Addressing Direct addressing directly accesses a location in the 256-byte lower register file, without involv-ing the memory controller. Windowing allows you to remap other sections of memory into thelower register file for direct access (see Chapter 5, “M...

4-9 PROGRAMMING CONSIDERATIONS 4.2.3.4 Indirect Addressing with the Stack Pointer You can also use indirect addressing to access the top of the stack by using the stack pointer asthe WORD register in an indirect reference. The following instruction uses indirect addressingwith the stack pointer: PUS...

8XC196NP, 80C196NU USER’S MANUAL 4-10 ST AX,TABLE[BX] ; MEM_WORD(TABLE+BX) ← AX ADDB AL,BL,LOOKUP[CX] ; AL ← BL + MEM_BYTE(LOOKUP+CX) The instruction LD AX, TABLE[BX] loads AX with the contents of the memory location that re-sides at address TABLE+BX. That is, the instruction adds the contents of BX...

8XC196NP, 80C196NU USER’S MANUAL 4-12 4.5.1 Using Registers The 256-byte lower register file contains the CPU special-function registers and the stack pointer.The remainder of the lower register file and all of the upper register file is available for your use.Peripheral special-function registers (...

4-13 PROGRAMMING CONSIDERATIONS 4.5.4 Linking Subroutines Parameters are passed to subroutines via the stack. Parameters are pushed into the stack from therightmost parameter to the left. The 8-bit parameters are pushed into the stack with the high-orderbyte undefined. The 32-bit parameters are push...

8XC196NP, 80C196NU USER’S MANUAL 4-14 4.6 SOFTWARE PROTECTION FEATURES AND GUIDELINES The device has several features to assist in recovering from hardware and software errors. Theunimplemented opcode interrupt provides protection from executing unimplemented opcodes.The hardware reset instruction (...

5-1 CHAPTER 5 MEMORY PARTITIONS This chapter describes the organization of the address space, its major partitions, and the 1-Mbyteand 64-Kbyte operating modes. 1-Mbyte refers to the address space defined by the 20 externaladdress lines. In 1-Mbyte mode, code can execute from almost anywhere in the ...

5-3 MEMORY PARTITIONS Figure 5-2. Pages FFH and 00H 5.2 MEMORY PARTITIONS Table 5-1 is a memory map of the 8XC196NP and 80C196NU. The remainder of this section de-scribes the partitions. FFFFFFH FF3000H FF2FFFH FF2080H FF207FH FF2000H FF1FFFH FF0100H FF00FFH FF0000H 00FFFFH 003000H 002FFFH 002000H 0...

5-5 MEMORY PARTITIONS 5.2.1 External Mem ory Several partitions in pages 00H and FFH and all of pages 01H–0EH are assigned to externalmemory (see Table 5-1). Data can be stored in any part of this memory. Instructions can be storedin any part of this memory in 1-Mbyte mode, but can be stored only in...

8XC196NP, 80C196NU USER’S MANUAL 5-6 5.2.2.2 Special-purpose Memory Special-purpose memory resides in locations FF2000–FF207FH. It contains several reservedmemory locations, the chip configuration bytes (CCBs), and vectors for both peripheral transac-tion server (PTS) and standard interrupts. Note t...

5-9 MEMORY PARTITIONS NOTE Using any SFR as a base or index register for indirect or indexed operations can cause unpredictable results because external events can change the contents of SFRs. Also, because some SFRs are cleared when read, consider the implications of using an SFR as an operand in a...

5-13 MEMORY PARTITIONS 5.3 WINDOWING Windowing expands the amount of memory that is accessible with direct addressing. Direct ad-dressing can access the lower register file with short, fast-executing instructions. With window-ing, direct addressing can also access the upper register file and periphe...

8XC196NP, 80C196NU USER’S MANUAL 5-14 5.3.1 Selecting a Window The window selection register (Figure 5-5) has two functions. The HLDEN bit (WSR.7) enablesand disables the bus-hold protocol (see Chapter 13, “Interfacing with External Memory”); it isunrelated to windowing. The remaining bits select a ...

8XC196NP, 80C196NU USER’S MANUAL 5-16 5.3.2 Addressing a Location Through a Window After you have selected the desired window, you need to know the direct address of the me morylocation (the address in the lower register file). For SFRs, refer to the WSR tables in AppendixC. For register file locati...

8XC196NP, 80C196NU USER’S MANUAL 5-18 Appendix C includes a table of the windowable SFRs with the window selection register valuesand direct addresses for each window size. The following examples explain how to determine theWSR value and direct address for any windowable location. An additional exam...

5-21 MEMORY PARTITIONS This listing shows the disassembled code: 2080H ;C814 | PUSH WSR2082H ;B14814 | LDB WSR,#48H2085H ;44E4E2E0 | ADD E0H,E2H,E4H2089H ;B21814 | LDB WSR,[SP]208CH ;65020018 | ADD SP,#02H2090H ;F0 | RET2091H ;C814 | PUSH WSR2093H ;B14814 | LDB WSR,#48H2096H ;44EAE8E6 | ADD E6H,E8H,...

8XC196NP, 80C196NU USER’S MANUAL 5-22 5.4 REMAPPING INTERNAL ROM (83C196NP ONLY) The 83C196NP’s 4 Kbytes of ROM are located in FF2000–FF2FFFH. By using the REMAP bit(CCB1.2) and the EA# input, you can also access these locations in external memory (page 0FHor page 00H). The REMAP bit is loaded from ...

5-23 MEMORY PARTITIONS 5.5 FETCHING CODE AND DATA IN THE 1-MBYTE AND 64-KBYTE MODES This section describes how the device fetches instructions and accesses data in the 1-Mbyte and64-Kbyte modes. When the device leaves reset, the MODE64 bit (CCB1.1) selects the 1-Mbyteor 64-Kbyte mode. The mode canno...

8XC196NP, 80C196NU USER’S MANUAL 5-24 For nonextended instructions, the EP_REG register provides the page number. Data and constantsin this page are called near data and near constants. NOTE The 8XC196NP allows you to change the value of EP_REG to control which memory page a nonextended instruction ...

5-25 MEMORY PARTITIONS 5.5.3 Code Fetches in the 1-Mbyte Mode CCR1.1 (the MODE64 bit) controls whether the device operates in 1-Mbyte or 64-Kbyte mode.CCR1 is loaded with the contents of CCB1 at reset. When MODE64 is clear, the device operatesin 1-Mbyte mode. In this mode, code can execute from any ...

8XC196NP, 80C196NU USER’S MANUAL 5-26 Code fetches are from external memory or internal memory, depending on the device, the mem-ory location, and the value of the EA# input. 80C196NU: Code executes from page 0FH in external memory. (The 80C196NU has no EA# input.) 80C196NP: For devices without inte...

5-27 MEMORY PARTITIONS Data accesses to 002000–002FFFH depend on the REMAP bit and the EA# input: • If remapping is disabled (CCB1.2 = 0), accesses are external. • If remapping is enabled (CCB1.2 = 1), accesses depend on EA#: — If EA# is low, accesses are external (REMAP is ignored). — If EA# is hig...

5-29 MEMORY PARTITIONS 5.6.2 Example 2: A 64-Kbyte System with Additional Data Storage Figure 5-10 shows another system designed for operation in the 64-Kbyte mode. Code executesfrom page FFH only. This system is the same as the example in “Example 1: Using the 64-KbyteMode” on page 5-27, but with a...

5-31 MEMORY PARTITIONS 5.6.3 Example 3: Using 1-Mbyte Mode Figure 5-11 shows a system designed for operation in the 1-Mbyte mode. In this mode, code canexecute from any page in the 1-Mbyte memory space. The system uses both 8-bit and 16-bit busesand uses the write-strobe mode. (See Chapter 13, “Inte...

6-1 CHAPTER 6 STANDARD AND PTS INTERRUPTS This chapter describes the interrupt control circuitry, priority scheme, and timing for standard andperipheral transaction server (PTS) interrupts. It discusses the three special interrupts and the fourPTS modes, two of which are used with the EPA to produce...

8XC196NP, 80C196NU USER’S MANUAL 6-2 Figure 6-1. Flow Diagram for PTS and Standard Interrupts No No PTS Enabled? PTSSEL. x Bit = 1? Yes Yes No Interrupt Pending or PTSSRV Bit Set NMI Pending ? Interrupts Enabled ? Yes No Return INT_MASK. x = 1? No Return Yes Return Reset INT_PEND. x Bit Reset PTSSRV...

6-3 STANDARD AND PTS INTERRUPTS Figure 6-1 illustrates the interrupt processing flow. In this flow diagram, “INT_MASK” repre-sents both the INT_MASK and INT_MASK1 registers, and “INT_PEND” represents both theINT_PEND and INT_PEND1 registers. 6.2 INTERRUPT SIGNALS AND REGISTERS Table 6-1 describes th...

8XC196NP, 80C196NU USER’S MANUAL 6-4 6.3 INTERRUPT SOURCES AND PRIORITIES Table 6-3 lists the interrupts sources, their default priorities (30 is highest and 0 is lowest), andtheir vector addresses. The unimplemented opcode and software trap interrupts are not priori-tized; they go directly to the i...

6-5 STANDARD AND PTS INTERRUPTS 6.3.1.1 Unimplemented Opcode If the CPU attempts to execute an unimplemented opcode, an indirect vector through locationFF2012H occurs. This prevents random software execution during hardware and software fail-ures. The interrupt vector should contain the starting add...

8XC196NP, 80C196NU USER’S MANUAL 6-6 6.3.1.3 NMI The external NMI pin generates a nonmaskable interrupt for implementation of critical interruptroutines. NMI has the highest priority of all the prioritized interrupts. It is passed directly fromthe transition detector to the priority encoder, and it ...

6-7 STANDARD AND PTS INTERRUPTS rupt if PTSSEL.5 is set. The interrupt vectors through FF204AH, but the corresponding end-of-PTS interrupt vectors through FF200AH, the standard SIO transmit interrupt vector. When theend-of-PTS interrupt vectors to the interrupt service routine, hardware clears the P...

8XC196NP, 80C196NU USER’S MANUAL 6-8 6.4.2 Calculating Latency The maximum latency occurs when the interrupt request occurs too late for acknowledgment fol-lowing the current instruction. The following worst-case calculation assumes that the current in-struction is not a protected instruction. To ca...

8XC196NP, 80C196NU USER’S MANUAL 6-10 6.5 PROGRAMMING THE INTERRUPTS The PTS select register (PTSSEL) selects either PTS service or a standard software interrupt ser-vice routine for each of the maskable interrupt requests (see Figure 6-4). The interrupt mask reg-isters, INT_MASK and INT_MASK1, enab...

6-11 STANDARD AND PTS INTERRUPTS 6.5.1 Programming Considerations for Multiplexed Interrupts An overrun on the EPA capture compare channels can generate the multiplexed capture overruninterrupts (OVR0_1 and OVR2_3). Write to the EPA_MASK (Figure 10-11 on page 10-22) reg-ister to enable or disable th...

6-13 STANDARD AND PTS INTERRUPTS 6.5.2 Modifying Interrupt Priorities Your software can modify the default priorities of maskable interrupts by controlling the interruptmask registers (INT_MASK and INT_MASK1). For example, you can specify which interrupts,if any, can interrupt an interrupt service r...

6-15 STANDARD AND PTS INTERRUPTS 6. At the end of the service routine, the POPA instruction restores the original contents of thePSW, INT_MASK, INT_MASK1, and WSR registers; any changes made to theseregisters during the interrupt service routine are overwritten. Because interrupt callscannot occur i...

6-17 STANDARD AND PTS INTERRUPTS 6.6 INITIALIZING THE PTS CONTROL BLOCKS Each PTS interrupt requires a block of data, in register RAM, called the PTS control block(PTSCB). The PTSCB identifies which PTS microcode routine will be invoked and sets up thespecific parameters for the routine. You must se...

8XC196NP, 80C196NU USER’S MANUAL 6-18 The address of the first (lowest) PTSCB byte is stored in the PTS vector table in special-purposememory (see “Special-purpose Memory” on page 5-6). Figure 6-9 shows the PTSCB for eachPTS mode. Unused PTSCB bytes can be used as extra RAM. NOTE The PTSCB must be l...

6-19 STANDARD AND PTS INTERRUPTS 6.6.2 Selecting the PTS Mode The second byte of each PTSCB is always an 8-bit value called PTSCON. Bits 5–7 select the PTSmode (Figure 6-11). The function of bits 0–4 differ for each PTS mode. Refer to the sections thatdescribe each mode in detail to see the function...

8XC196NP, 80C196NU USER’S MANUAL 6-20 6.6.3 Single Transfer Mode In single transfer mode, an interrupt causes the PTS to transfer a single byte or word (selected bythe BW bit in PTSCON) from one memory location to another. This mode is typically used withserial I/O or synchronous serial I/O interrup...

6-21 STANDARD AND PTS INTERRUPTS PTS Single Transfer Mode Control Block In single transfer mode, the PTS control block contains a source and destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT). 7 0 Unused 0 0 0 0 0 0 0 0 7 0 Unused 0 0 0 0 0 0 0 0 15...

6-23 STANDARD AND PTS INTERRUPTS 6.6.4 Block Transfer Mode In block transfer mode, an interrupt causes the PTS to move a block of bytes or words from onememory location to another. See AP-445, 8XC196KR Peripherals: A User ’s Point of View, for ap-plication examples with code. Figure 6-13 shows the P...

8XC196NP, 80C196NU USER’S MANUAL 6-24 PTS Block Transfer Mode Control Block In block transfer mode, the PTS control block contains a block size (PTSBLOCK), a source and destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT). 7 0 Unused 0 0 0 0 0 0 0 0 7...

6-25 STANDARD AND PTS INTERRUPTS Register Location Function PTSCON PTSCB + 1 PTS Control Bits M2:0 PTS Mode These bits select the PTS mode: M2 M1 M0 0 0 0 block transfer mode BW Byte/Word Transfer 0 = word transfer1 = byte transfer SU Update PTSSRC 0 = reload original PTS source address after each b...

8XC196NP, 80C196NU USER’S MANUAL 6-26 6.6.5 PWM Modes The PWM toggle and PWM remap modes are designed for use with the event processor array(EPA) to generate pulse-width modulated (PWM) output signals. These modes can also be usedwith an interrupt signal from any other source. The PWM toggle mode us...

6-29 STANDARD AND PTS INTERRUPTS PTS PWM Toggle Mode Control Block In PWM toggle mode, the PTS uses a single EPA channel to generate a pulse-width modulated (PWM) output signal. The control block contains registers that contain the PWM on-time (PTSCONST1), the PWM off-time (PTSCONST2), the address p...

6-31 STANDARD AND PTS INTERRUPTS Figure 6-16. EPA and PTS Operations for the PWM Toggle Mode Example You can modify the duty cycle without interrupting the PWM operation. To change the duty cycleduring a PWM cycle, the PTS service routine should write new T1 and T2 – T1 values toCSTORE1 and CSTORE2 ...

8XC196NP, 80C196NU USER’S MANUAL 6-32 When the next timer match occurs, the PTS cycle (Figure 6-16) increments EPA0_TIME by T1(if TBIT is zero (output = 0)) or T2 – T1 (if TBIT is one (output = 1)). (Note that although thevalues of the EPA0 output and TBIT are the same in this example, these two val...

6-33 STANDARD AND PTS INTERRUPTS 4. Set up EPA0 and EPA1. — Load EPA0_CON with 68H (timer 1, compare mode, assert output pin, re-enable). — Load EPA1_CON with 158H (timer 1, compare mode, deassert output pin, re-enable, remap enabled). — Load EPA0_TIME with 0000H (selects time 0 as first event time ...

8XC196NP, 80C196NU USER’S MANUAL 6-34 PTS PWM Remap Mode Control Block In PWM remap mode, the PTS uses two EPA channels to generate a pulse-width modulated (PWM) output signal. The control block contains registers that contain the PWM on-time (PTSCONST1), the address pointer (PTSPTR1), and a control...

6-35 STANDARD AND PTS INTERRUPTS Figure 6-18 shows the EPA and PTS operations for this example. The first timer match occurs attime = 0 for EPA0, which asserts the output and generates an interrupt. PWM Remap Cycle 1. The PTS adds T2 to EPA0_TIME and toggles the TBIT. The output remains asserted unt...

8XC196NP, 80C196NU USER’S MANUAL 6-36 Figure 6-18. EPA and PTS Operations for the PWM Remap Mode Example You can change the duty cycle by changing the time that the output is high and keeping the periodconstant. After a timer match occurs for EPA1 (when the output falls), schedule the next EPA1match...

7-1 CHAPTER 7 I/O PORTS I/O ports provide a mechanism to transfer information between the device and the surroundingsystem circuitry. They can read system status, monitor system operation, output device status,configure system options, generate control signals, provide serial communication, and so o...

7-3 I/O PORTS 7.2.1 Bidirectional Port Operation Figure 7-1 shows the logic for driving the output transistors, Q1 and Q2. On ports 1, 2, and 3, Q1can source at least –3 mA at V CC – 0.7 volts. On port 4, which has a high-current sink capability for the PWMs, Q1 can source at least –3 mA at 0.45 vol...

7-4 8XC196NP, 80C196NU USER’S MANUAL In special-function mode (selected by setting Px_MODE.y), SFDIR and SFDATA are input to themultiplexers. These signals combine to drive the gates of Q1 and Q2 so that the output is high,low, or high impedance. Special-function output signals clear SFDIR; special-...

7-5 I/O PORTS Figure 7-1. Bidirectional Port Structure Vcc Q2 Q1 Px_REG Px_DIR Sample Latch PH1 Clock Internal Bus SFDATA SFDIR Px_MODE Px_PIN D Q 0 1 0 1 Vcc Vcc Q R S Any Write to Px_MODE WeakPullup MediumPullup RESET# RESET# Q3 Q4 Vss Read Port LE 300ns Delay I/O Pin A0238-04 150 Ω to 200 Ω R1

7-7 I/O PORTS 7.2.2 Bidirectional Port Pin Configurations Each bidirectional port pin can be individually configured to operate either as an I/O pin or as apin for a special-function signal. In the special-function configuration, the signal is controlled byan on-chip peripheral or an off-chip compon...

7-8 8XC196NP, 80C196NU USER’S MANUAL 7.2.3 Bidirectional Port Pin Configuration Example Assume that you wish to configure the pins of a bidirectional port as shown in Table 7-7. To do so, you could use the following example code segment. Table 7-8 shows the state of eachpin after reset and after exe...

7-9 I/O PORTS 7.2.4 Bidirectional Port Considerations This section outlines special considerations for using the pins of these ports. Port 1 After reset, your software must configure the device to match theexternal system. This is accomplished by writing appropriate config-uration data into P1_MODE....

7-11 I/O PORTS 7.2.5 Design Considerations for External Interrupt Inputs To configure a port pin that serves as an external interrupt input, you must set the correspondingbits in the configuration registers (Px_DIR, Px_MODE, and Px_REG). However, setting thePx_MODE bit causes the device to set the c...

7-12 8XC196NP, 80C196NU USER’S MANUAL 7.3.1 EPORT Operation As Figure 7-2 shows, each EPORT pin serves either as I/O or as an address line, as selected bythe I/O multiplexer. This multiplexer is controlled by the EP_MODE register. If EP_MODE.x isclear (I/O mode), the pin serves as I/O until EP_MODE....

7-13 I/O PORTS Figure 7-2. EPORT Block Diagram If EP_MODE.x is set (address mode), the address multiplexer determines the address source. Foran instruction fetch, the address multiplexer is set to the CODE input, which selects the extendedprogram counter (EPC) as the address source. For a data fetch...

7-14 8XC196NP, 80C196NU USER’S MANUAL The 8XC196NP allows you to change the value of EP_REG to control which memory page a non-extended instruction accesses. However, software tools require that EP_REG be equal to 00H.The 80C196NU forces all nonextended data accesses to page 00H. You cannot use EP_R...

7-17 I/O PORTS 7.3.2 Configuring EPORT Pins Each EPORT pin can be individually configured to operate either as an extended-address signalor as an I/O pin in one of these modes: • complementary output (output only) • high-impedance input or open-drain output (input, output, or bidirectional) 7.3.2.1 ...

7-18 8XC196NP, 80C196NU USER’S MANUAL 7.3.3 EPORT Considerations This section outlines considerations for using the EPORT pins. 7.3.3.1 EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold During reset, the EPORT pins are forced to their extended-address functions and are weaklypulled hig...

7-19 I/O PORTS 3. Any nonextended or direct instruction that accesses the register file or the windowableSFRs is always directed internally to these areas, regardless of the page from which codeis executing. This effectively maps the register file and windowable SFRs into every page.Extended instruc...

8-1 CHAPTER 8 SERIAL I/O (SIO) PORT A serial input/output (SIO) port provides a means for the system to communicate with externaldevices. This device has a serial I/O (SIO) port that shares pins with port 2. This chapter describesthe SIO port and explains how to configure it. Chapter 7, “I/O Ports,”...

8-2 8XC196NP, 80C196NU USER’S MANUAL An independent, 15-bit baud-rate generator controls the baud rate of the serial port. Either the in-ternal peripheral clock or T1CLK can provide the clock signal. The baud-rate register(SP_BAUD) selects the clock source and the baud rate. 8.2 SERIAL I/O PORT SIGN...

8-4 8XC196NP, 80C196NU USER’S MANUAL 8.3 SERIAL PORT MODES The serial port has both synchronous and asynchronous operating modes for transmission and re-ception. This section describes the operation of each mode. 8.3.1 Synchronous Mode (Mode 0) The most common use of mode 0, the synchronous mode, is...

8-6 8XC196NP, 80C196NU USER’S MANUAL When the serial port is configured for mode 1, 2, or 3, writing to SBUF_TX causes the serial portto start transmitting data. New data placed in SBUF_TX is transmitted only after the stop bit ofthe previous data has been sent. A falling edge on the RXD input cause...

8-8 8XC196NP, 80C196NU USER’S MANUAL 8.3.2.5 Multiprocessor Communications Modes 2 and 3 are provided for multiprocessor communications. In mode 2, the serial port setsthe RI interrupt pending bit only when the ninth data bit is set. In mode 3, the serial port sets theRI interrupt pending bit regard...

8-12 8XC196NP, 80C196NU USER’S MANUAL CAUTION For mode 0 receptions, the BAUD_VALUE must be 0002H or greater. Otherwise, the resulting data in the receive shift register will be incorrect. The reason for this restriction is that the receive shift register is clocked from an internal signal rather th...

9-1 CHAPTER 9 PULSE-WIDTH MODULATOR The pulse-width modulator (PWM) module has three output pins, each of which can output aPWM signal with a fixed frequency and a variable duty cycle. These outputs can be used to drivemotors that require an unfiltered PWM waveform for optimal efficiency, or they ca...

9-2 8XC196NP, 80C196NU USER’S MANUAL Figure 9-2. PWM Block Diagram (80C196NU Only) 9.2 PWM SIGNALS AND REGISTERS Table 9-1 describes the PWM’s signals and Table 9-2 briefly describes the control and status reg-isters. Table 9-1. PWM Signals Port Pin PWM Signal PWM Signal Type Description P4.0 PWM0 O...

9-3 PULSE-WIDTH MODULATOR 9.3 PWM OPERATION For the 8XC196NP, CON_REG0.0 (CLK0) controls the PWM output frequency by enabling ordisabling the divide-by-two clock prescaler. Enabling the prescaler causes the 8-bit counter to in-crement once every two state times; disabling it causes the counter to in...

9-5 PULSE-WIDTH MODULATOR Figure 9-3. PWM Output Waveforms 9.4 PROGRAMMING THE FREQUENCY AND PERIOD The PWM module provides two selectable, fixed PWM output frequencies for a specifiedinternal operating frequency (f). Table 9-3 shows the PWM output frequencies for commonoperating frequencies on the ...

9-7 PULSE-WIDTH MODULATOR 9.5 PROGRAMMING THE DUTY CYCLE The value written to the PWMx_CONTROL register controls the width of the high pulse, effec-tively controlling the duty cycle. The 8-bit value written to the control register is loaded into abuffer, and this value is used during the next period...

9-9 PULSE-WIDTH MODULATOR 9.5.1 Sample Calculations For example, assume that the operating frequency equals 25 MHz, the desired period of the PWMoutput waveform is either 20.48 µs (512 state times) if the divide-by-two prescaler is disabled or40.96 µs (1,024 state times) if the prescaler is enabled....

9-10 8XC196NP, 80C196NU USER’S MANUAL Figure 9-6. D/A Buffer Block Diagram Figure 9-7 shows a sample circuit used for low output currents (less than 100 µ A). Consider tem- perature and power-supply drift when selecting components for the external D/A circuitry. Withproper components, a highly accur...

10-1 CHAPTER 10 EVENT PROCESSOR ARRAY (EPA) Control applications often require high-speed event control. For example, the controller may needto periodically generate pulse-width modulated outputs or an interrupt. In another application, thecontroller may monitor an input signal to determine the stat...

8XC196NP, 80C196NU USER’S MANUAL 10-2 Figure 10-1. EPA Block Diagram 10.2 EPA AND TIMER/COUNTER SIGNALS AND REGISTERS Table 10-1 describes the EPA and timer/counter input and output signals. Each signal is multi-plexed with a port pin as shown in the first column. Table 10-2 briefly describes the re...

10-3 EVENT PROCESSOR ARRAY (EPA) Table 10-2. EPA Control and Status Registers Mnemonic Address Description EPA_MASK 1F9CH EPA Mask Four bits (OVR0, OVR1, OVR2, and OVR3) in this 8-bit register enable and disable (mask) the individual capture overrun interrupt sources associated with capture/compare ...

8XC196NP, 80C196NU USER’S MANUAL 10-8 Figure 10-4. Quadrature Mode Timing and Count 10.4 EPA CHANNEL FUNCTIONAL OVERVIEW The EPA has four programmable capture/compare channels that can perform the following tasks. • capture the current timer value when a specified transition occurs on the EPA pin • ...

10-11 EVENT PROCESSOR ARRAY (EPA) An input capture event does not set the interrupt pending bit until the captured time value actuallymoves from the capture buffer into the EPAx_TIME register. If the buffer contains data and thePTS is used to service the interrupts, then two PTS interrupts occur alm...

10-13 EVENT PROCESSOR ARRAY (EPA) The maximum output frequency depends upon the total interrupt latency and the interrupt-serviceexecution times used by your system. As additional EPA channels and the other functions of themicrocontroller are used, the maximum PWM frequency decreases because the tot...

8XC196NP, 80C196NU USER’S MANUAL 10-14 The maximum output frequency depends upon the total interrupt latency and interrupt-service ex-ecution time. As additional EPA channels and the other functions of the microcontroller are used,the maximum PWM frequency decreases because the total interrupt laten...

10-15 EVENT PROCESSOR ARRAY (EPA) 10.4.2.4 Generating the Highest-speed PWM Output You can generate a highest-speed, pulse-width modulated output with a pair of EPA channels anda dedicated timer/counter. The first channel toggles the output when the timer value matchesEPAx_TIME, and at some later ti...

8XC196NP, 80C196NU USER’S MANUAL 10-18 10.5.3 Programming the Capture/Compare Channels The EPAx_CON register controls the function of its assigned capture/compare channel. The reg-isters for EPA0 and EPA2 are identical. The registers for EPA1 and EPA3 have an additional bit,the remap bit (RM), which...

8XC196NP, 80C196NU USER’S MANUAL 10-24 10.8 PROGRAMMING EXAMPLES FOR EPA CHANNELS The three programming examples provided in this section demonstrate the use of the EPA channel for a compare event, for a capture event, and for generation of a PWM signal. The programs dem- onstrate the detection of e...

11-1 CHAPTER 11 MINIMUM HARDWARE CONSIDERATIONS The 8XC196NP and 80C196NU have several basic requirements for operation within a system.This chapter describes options for providing the basic requirements and discusses other hardwareconsiderations. 11.1 MINIMUM CONNECTIONS Table 11-1 lists the signal...

8XC196NP, 80C196NU USER’S MANUAL 11-2 11.1.1 Unused Inputs For predictable performance, it is important to tie unused inputs to V CC or V SS . Otherwise, they can float to a mid-voltage level and draw excessive current. Unused interrupt inputs may generatespurious interrupts if left unconnected. 11....

11-3 MINIMUM HARDWARE CONSIDERATIONS Figure 11-1. Minimum Hardware Connections ALE INST XTAL1 XTAL2 V CC (Note 2) 0.01 µF NMI READY V CC Bus Control (Note 4) 20 pF 20 pF (Note 1) 4.7 µF + .22 µF RESET# BHE# WR# RD# EA# V CC A2415-02 V SS RPD 8XC196 Device V CC Notes: 1. See the datasheet for the osc...

8XC196NP, 80C196NU USER’S MANUAL 11-4 11.2 APPLYING AND REMOVING POWER When power is first applied to the device, RESET# must remain continuously low for at least onestate time after the power supply is within tolerance and the oscillator/clock has stabilized; oth-erwise, operation might be unpredic...

11-5 MINIMUM HARDWARE CONSIDERATIONS Multilayer printed circuit boards with separate V CC and ground planes also help to minimize noise. For more information on noise protection, refer to AP-125, Designing Microcontroller Sys-tems for Noisy Environments and AP-711, EMI Design Techniques for Microcon...

8XC196NP, 80C196NU USER’S MANUAL 11-6 Figure 11-4 shows the connections between the external crystal and the device. When designingan external oscillator circuit, consider the effects of parasitic board capacitance, extended oper-ating temperatures, and crystal specifications. Consult the manufactur...

11-7 MINIMUM HARDWARE CONSIDERATIONS 11.5 USING AN EXTERNAL CLOCK SOURCE To use an external clock source, apply a clock signal to XTAL1 and let XTAL2 float (Figure11-5). To ensure proper operation, the external clock source must meet the minimum high andlow times (T XH XX and T XLX X ) and the maxim...

8XC196NP, 80C196NU USER’S MANUAL 11-8 11.6 RESETTING THE DEVICE Reset forces the device into a known state. As soon as RESET# is asserted, the I/O pins, the con-trol pins, and the registers are driven to their reset states. (Table B-5 on page B-13 lists the resetstates of the pins. See Table C-2 on ...

11-9 MINIMUM HARDWARE CONSIDERATIONS The following events will reset the device (see Figure 11-8): • an external device pulls the RESET# pin low • the CPU issues the reset (RST) instruction • the CPU issues an idle/powerdown (IDLPD) instruction with an illegal key operand The following paragraphs de...

8XC196NP, 80C196NU USER’S MANUAL 11-10 The simplest way to reset the device is to insert a capacitor between the RESET# pin and V SS , as shown in Figure 11-9. The device has an internal pull-up resistor (R RST ) shown in Figure 11-8. RESET# should remain asserted for at least one state time after V...

11-11 MINIMUM HARDWARE CONSIDERATIONS 11.6.2 Issuing the Reset (RST) Instruction The RST instruction (opcode FFH) resets the device by pulling RESET# low for 16 state times.It also clears the processor status word (PSW), sets the extended and master program counters(EPC/PC) to FF2080H, and resets th...

12-1 CHAPTER 12 SPECIAL OPERATING MODES The 8XC196NP and 80C196NU provide the following power saving modes: idle, standby(80C196NU only), and powerdown. They also provide an on-circuit emulation (ONCE) modethat electrically isolates the device from the other system components. This chapter describes...

12-2 8XC196NP, 80C196NU USER’S MANUAL — PLLEN2:1(80C196NU only) I Phase Lock Loop 1 and 2 Enable These input pins are used to enable the on-chip clock multiplier feature and select either the doubled or quadrupled clock speed. CAUTION: If PLLEN1 is held low while PLLEN2 is held high, the device will...

12-3 SPECIAL OPERATING MODES 12.2 REDUCING POWER CONSUMPTION Each power-saving mode conserves power by disabling portions of the internal clock circuitry(Figure 12-1 and Figure 12-2). The following paragraphs describe each mode in detail. INT_MASK1 0013H Interrupt Mask 1 Bits 5 and 6 of this registe...

12-6 8XC196NP, 80C196NU USER’S MANUAL The device enters idle mode after executing the IDLPD #1 instruction. Any enabled interruptsource, either internal or external, or a hardware reset can cause the device to exit idle mode.When an interrupt occurs, the CPU clocks restart and the CPU executes the c...

12-7 SPECIAL OPERATING MODES 12.4.3 Exiting Standby Mode The device will exit standby mode when a transition on an external interrupt pin (EXTINT3:0)or a hardware reset occurs. The interrupts need not be enabled for them to bring the device out ofstandby, but the pin must be configured as a special-...

12-8 8XC196NP, 80C196NU USER’S MANUAL After completing these tasks, execute the IDLPD #2 instruction to enter powerdown mode. NOTE To prevent an accidental return to full power, hold the external interrupt pins (EXTINTx) low while the device is in powerdown mode. 12.5.3 Exiting Powerdown Mode The de...

12-10 8XC196NP, 80C196NU USER’S MANUAL During normal operation (before entering powerdown mode), an internal pull-up holds theRPD pin at V CC . When an external interrupt signal is asserted, the internal oscillator circuitry is enabled and turns on a weak internal pull-down. The resistance of the in...

12-11 SPECIAL OPERATING MODES Figure 12-5. Typical Voltage on the RPD Pin While Exiting Powerdown When selecting the capacitor, determine the worst-case discharge time needed for the oscillatorto stabilize, then use this formula to calculate an appropriate value for C 1 . where: C 1 is the capacitor...

12-13 SPECIAL OPERATING MODES Table 12-3. 80C196NU Clock Modes PLLEN2 PLLEN1 Mode 0 0 Clock-multiplier circuitry disabled. 0 1 Reserved. CAUTION: This combination causes the device to enter an unsupported test mode. 1 0 Doubled; clock doubling circuitry enabled. Internal clock is twice the XTAL1 inp...

13-1 CHAPTER 13 INTERFACING WITH EXTERNAL MEMORY The device can interface with a variety of external memory devices. Six chip-selects can be indi-vidually programmed for bus width, the number of wait states, and a multiplexed or demulti-plexed address/data bus. Other features of the external memory ...

8XC196NP, 80C196NU USER’S MANUAL 13-2 13.2 EXTERNAL MEMORY INTERFACE SIGNALS Table 13-2 describes the external memory interface signals. For some signals, the pin has an al-ternate function (shown in the Multiplexed With column). In some cases the alternate function isa port signal (e.g., P2.7). Cha...

8XC196NP, 80C196NU USER’S MANUAL 13-8 ADDRMSK x x = 0–5 Address: Reset State: Table 13-5 The address mask (ADDRMSK x ) register, together with the address compare register, defines the address range that is assigned to the chip-select x output, CS x #. The address mask register determines the size o...

13-9 INTERFACING WITH EXTERNAL MEMORY Observe the following restrictions in choosing an address range for a chip-select output: • The addresses in the address range must be contiguous. • The size of the address range must be 2 n bytes, where n = 8, 9, ..., 20. This corresponds to block sizes of 256 ...

13-11 INTERFACING WITH EXTERNAL MEMORY 13.3.3 Chip-select Unit Initial Conditions A chip reset produces the following initial conditions for the chip-select unit: • ADDRMSKx = XFFFH. • ADDRCOM0 = 0F20H. This asserts CS0# for the 256-byte address range F2000–F20FFH. • ADDRCOM1–ADDRCOM5 = X000H. • For...

13-13 INTERFACING WITH EXTERNAL MEMORY Figure 13-5. Example System for Setting Up Chip-select Outputs The location and size of an address range are specified by the ADDRCOMx register and theADDRMSKx register (see Figure 13-2 and Figure 13-3). The 8-Kbyte SRAM is assigned to ad-dress range 7E000–7FFF...

8XC196NP, 80C196NU USER’S MANUAL 13-14 13.4 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES Two chip configuration registers (CCRs) have bits that set parameters for chip operation and ex-ternal bus cycles. The CCRs cannot be accessed by code. They are loaded from the chip config-uration b...

8XC196NP, 80C196NU USER’S MANUAL 13-18 After RESET# is deasserted, the following pins are initialized: • The P2.7/CLKOUT pin operates as CLKOUT (as during reset). Be sure that the CLKOUTsignal does not damage external hardware. • The P3.0/CS0# pin operates as CS0#, which is asserted for the CCB fetc...

13-19 INTERFACING WITH EXTERNAL MEMORY Figure 13-8. Multiplexing and Bus Width Options Bus Control Address Bits 16–19 Address Bits 0–15 16-bit Data A19:16 (EPORT) A15:0 AD15:0 8XC196 Device Bus Control Address Bits 16–19 Address Bits 0–15 A19:16 (EPORT) A15:0 AD7:0 8XC196 Device 8-bit Data Driven wi...

8XC196NP, 80C196NU USER’S MANUAL 13-20 A design can incorporate external devices that operate with different bus widths and multiplex-ing. The bus parameters used during a particular bus cycle are determined by the chip-select out-put that is assigned to the address being accessed. Figure 13-9 shows...

8XC196NP, 80C196NU USER’S MANUAL 13-22 Figure 13-10. 16-bit External Devices in Demult iplexed Mode 13.5.2 16-bit Bus Timings Figure 13-11 shows idealized 16-bit external-bus timings for the 8XC196NP. The signals are di-vided into two groups: signals for a demultiplexed bus (top) and signals for a m...

8XC196NP, 80C196NU USER’S MANUAL 13-26 13.5.4 Comparison of Multiplexed and Demultiplexed Buses This section compares the timings for multiplexed and demultiplexed buses. A 16-bit bus is usedfor the comparison. “8-bit Bus Timings” on page 13-24 compares the 8-bit and 16-bit buses. In a multiplexed s...

13-27 INTERFACING WITH EXTERNAL MEMORY When selecting infinite wait states, be sure to add external hardware to count wait states and re-lease READY within a specified period of time. Otherwise, a defective external device could tieup the address/data bus indefinitely. NOTE Ready control is valid on...

8XC196NP, 80C196NU USER’S MANUAL 13-28 Figure 13-13. READY Timing Diagram — Multiplexed Mode T0013-02 T WLWH + 2t T QVWH + 2t T CLYX (max) T AVYV T LHLH + 2t T RLRH + 2t T AVDV + 2t T RLD V + 2t Address Out Data In Address Out Data Out CLKOUT READY ALE RD# AD15:0 WR# AD15:0 BHE#, INST A19:16 CS x # ...

13-33 INTERFACING WITH EXTERNAL MEMORY 13.7.4 Regaining Bus Control While HOLD# is asserted, the 8XC196Nx continues executing code until it needs to access theexternal bus. If executing from internal memory, it continues until it needs to perform an externalmemory cycle. If executing from external m...

8XC196NP, 80C196NU USER’S MANUAL 13-34 Figure 13-17. Write-control Signal Waveforms Table 13-14 compares the values of the write-control signals for write operations in the sta ndardmode and the write strobe mode. The table lists values of WR# and BHE# and values of WRL#and WRH# for 8-bit and 16-bit...

8XC196NP, 80C196NU USER’S MANUAL 13-36 Figure 13-19 illustrates the use of the write strobe mode in a mixed 8-bit and 16-bit system withtwo flash memories and one SRAM. The WRL# signal, which is generated for all 8-bit writes(Table 13-14), is used to write bytes to the SRAM. Note that the RD# signal...

13-43 INTERFACING WITH EXTERNAL MEMORY The 8XC196N x Meets These Specifications f Operating frequency Frequency of the signal input on the XTAL1 pin times the clock multiplier ( x ). For the 8XC196NP, x is always 1; for the 80C196NU, x is 1, 2, or 4, depending on the clock mode. The internal bus spe...

8XC196NP, 80C196NU USER’S MANUAL A-2 Table A-1. Opcode Map (Left Half) Opcode x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 0 x SKIP CLR NOT NEG XCH di DEC EXT INC 1 x CLRB NOTB NEGB XCHB di DECB EXTB INCB 2 x SJMP 3 x JBC bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 4 x AND 3op ADD 3op di im in ix di im in ix...

A-3 INSTRUCTION SET REFERENCE Table A-1. Opcode Map (Right Half) Opcode x 8 x 9 x A x B x C x D x E x F 0 x SHR SHL SHRA XCH ix SHRL SHLL SHRAL NORML 1 x SHRB SHLB SHRAB XCHB ix EST in EST ix ESTB in ESTB ix 2 x SCALL 3 x JBS bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 4 x SUB 3op MULU 3op (Note...

A-5 INSTRUCTION SET REFERENCE Table A-3 shows the effect of the PSW flags or a specified condition on conditional jump instruc-tions. Table A-4 defines the symbols used in Table A-6 to show the effect of each instruction onthe PSW flags. . Table A-3. Effect of PSW Flags or Specified Conditions on Co...

A-47 INSTRUCTION SET REFERENCE Table A-7. Instruction Opcodes Hex Code Instruction Mnemonic 00 SKIP 01 CLR 02 NOT 03 NEG 04 XCH Direct 05 DEC 06 EXT 07 INC 08 SHR 09 SHL 0A SHRA 0B XCH Indexed 0C SHRL 0D SHLL 0E SHRAL 0F NORML 10 Reserved 11 CLRB 12 NOTB 13 NEGB 14 XCHB Direct 15 DECB 16 EXTB 17 INC...

B-1 APPENDIX B SIGNAL DESCRIPTIONS This appendix provides reference information for the pin functions of the 8XC196NP and80C196NU. B.1 FUNCTIONAL GROUPINGS OF SIGNALS Table B-1 lists the signals for the 8XC196NP and 80C196NU, grouped by function. A diagramof each package that is currently available ...

8XC196NP, 80C196NU USER’S MANUAL B-2 Figure B-1. 8XC196NP 100-lead SQFP Package RD#BHE# / WRH#ALEINSTREADYRPDONCEV SS V CC V SS A8A9A10A11A12A13A14A15NCV SS XTAL1XTAL2V SS NCP2.7 / CLKOUT AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 V CC AD8 V SS AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 / EPORT.0 A17 / EPORT.1 V CC...

B-3 SIGNAL DESCRIPTIONS Figure B-2. 8XC196NP 100-lead QFP Package V SS A18 / EPORT.2A19 / EPORT.3WR# / WRL#RD#BHE# / WRH#ALEINSTREADYRPDONCEV SS V CC V SS A8A9A10A11A12A13A14A15V SS XTAL1XTAL2V SS P2.7 / CLKOUTNCP2.6 / HLDA#P2.5 / HOLD# AD1 AD2 AD3 AD4 AD5 AD6 AD7 V CC AD8 V SS AD9 AD10 AD11 AD12 AD...

8XC196NP, 80C196NU USER’S MANUAL B-6 B.2 SIGNAL DESCRIPTIONS Table B-2 defines the columns used in Table B-3, which describes the signals. Table B-2. Description of Columns of Table B-3 Column Heading Description Name Lists the signals, arranged alphabetically. Many pins have two functions, so there...

B-13 SIGNAL DESCRIPTIONS B.3 DEFAULT CONDITIONS Table B-5 lists the default functions of the I/O and control pins of the 8XC196NP and 80C196NUwith their values during various operating conditions. Table B-4 defines the symbols used to rep-resent the pin status. Refer to the DC Characteristics table ...

C-1 APPENDIX C REGISTERS This appendix provides reference information about the device registers. Table C-1 lists the mod-ules and major components of the device with their related configuration and status registers. Ta-ble C-2 lists the registers, arranged alphabetically by mnemonic, along with the...

C-3 REGISTERS EPA2_CON EPA Capture/Comp 2 Control 1F88H 0000 0000 EPA3_CON EPA Capture/Comp 3 Control 1F8CH 0000 0000 0000 0000 EPA0_TIME EPA Capture/Comp 0 Time 1F82H 0000 0000 0000 0000 EPA1_TIME EPA Capture/Comp 1 Time 1F86H 0000 0000 0000 0000 EPA2_TIME EPA Capture/Comp 2 Time 1F8AH 0000 0000 00...

8XC196NP, 80C196NU USER’S MANUAL C-8 ADDRCOMx ADDRCOM x x = 0–5 Address: Reset State: Table C-5 The address compare (ADDRCOM x ) register specifies the base (lowest) address of the address range. The base address of a 2 n -byte address range must be on a 2 n -byte boundary. 15 8 — — — — BASE19 BASE1...

C-9 REGISTERS ADDRMSKx ADDRMSK x x = 0–5 Address: Reset State: Table C-6 The address mask (ADDRMSK x ) register, together with the address compare register, defines the address range that is assigned to the chip-select x output, CS x #. The address mask register determines the size of the address ra...

8XC196NP, 80C196NU USER’S MANUAL C-10 BUSCONx BUSCON x x = 0–5 Address: Reset State: Table C-7 For the address range assigned to chip-select x , the bus control (BUSCON x ) register specifies the number of wait states, the bus width, and the address/data multiplexing for all external bus cycles that...

8XC196NP, 80C196NU USER’S MANUAL C-24 EPAx_TIME EPA x _TIME x = 0–3 Address: Reset State: Table C-9 The EPA time (EPA x _TIME) registers are the event-time registers for the EPA channels. In capture mode, the value of the reference timer is captured in EPA x _TIME when an input transition occurs. Ea...

8XC196NP, 80C196NU USER’S MANUAL C-30 Px_DIR P x _DIR x = 1–4 Address: Reset State: Table C-10 Each pin of port x can operate in any of the standard I/O modes of operation: complementary output, open-drain output, or high-impedance input. The port x I/O direction (P x _DIR) register determines the I...

8XC196NP, 80C196NU USER’S MANUAL C-32 Px_PIN P x _PIN x = 1–4 Address: Reset State: Table C-13 Each bit of the port x pin input (P x _PIN) register reflects the current state of the corresponding pin, regardless of the pin configuration. 7 0 x = 1–3 PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 7 0 x = 4 ...

8XC196NP, 80C196NU USER’S MANUAL C-34 PSW PSW no direct access The processor status word (PSW) actually consists of two bytes. The high byte is the status word, which is described here; the low byte is the INT_MASK register. The status word contains one bit (PSW.1) that globally enables or disables ...

C-35 REGISTERS PSW 4 VT Overflow-trap Flag This flag is set when the overflow flag is set, but it is cleared only by the CLRVT, JVT, and JNVT instructions. This allows testing for a possible overflow at the end of a sequence of related arithmetic operations, which is generally more efficient than te...

8XC196NP, 80C196NU USER’S MANUAL C-36 PTSSEL PTSSEL Address: Reset State: 0004H0000H The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit selects a sta...

C-37 REGISTERS PTSSRV PTSSRV Address: Reset State: 0006H0000H The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corre-sponding PTSSEL bit and sets the PTSSRV bit, wh...

8XC196NP, 80C196NU USER’S MANUAL C-38 PWMx_CONTROL PWM x _CONTROL x = 0–2 Address: Reset State: Table C-15 The PWM control (PWM x _CONTROL) register determines the duty cycle of the PWM x channel. A zero loaded into this register causes the PWM to output a low continuously (0% duty cycle). An FFH in...

C-41 REGISTERS SP SP Address: Reset State: 18H XXXXH The system’s stack pointer (SP) can point anywhere in an internal or external memory page; it must be word aligned and must always be initialized before use. The stack pointer is decremented before a PUSH and incremented after a POP, so the stack ...

8XC196NP, 80C196NU USER’S MANUAL C-46 T1CONTROL T1CONTROL Address: Reset State: 1F90H 00H The timer 1 control (T1CONTROL) register determines the clock source, counting direction, and count rate for timer 1. 7 0 CE UD M2 M1 M0 P2 P1 P0 Bit Number Bit Mnemonic Function 7 CE Counter Enable This bit en...

C-47 REGISTERS T2CONTROL T2CONTROL Address: Reset State: 1F94H 00H The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count rate for timer 2. 7 0 CE UD M2 M1 M0 P2 P1 P0 Bit Number Bit Mnemonic Function 7 CE Counter Enable This bit enables or disables the t...

8XC196NP, 80C196NU USER’S MANUAL C-48 TIMERx TIMER x x = 1–2 Address: Reset State: Table C-17 Th is register contains the value of timer x . This register can be written, allowing timer x to be initialized to a value other than zero. 15 8 Timer Value (high byte) 7 0 Timer Value (low byte) Bit Number...

C-49 REGISTERS WSR WSR Address: Reset State: 0014H 00H The window selection register (WSR) has two functions. One bit enables and disables the bus-hold protocol. The remaining bits select windows. Windows map sections of RAM into the top of the lower register file, in 32-, 64-, or 128-byte increment...

8XC196NP, 80C196NU USER’S MANUAL C-52 WSR1 WSR1(80C196NU) Address: Reset State: 0015H 00H Window selection 1 (WSR1) register selects a 32- or 64-byte segment of the upper register file or peripheral SFRs to be windowed into the middle of the lower register file, below any window selected by the WSR....

Glossary-1 GLOSSARY This glossary defines acronyms, abbreviations, and terms that have special meaning in this man-ual. (Chapter 1 discusses notational conventions and general terminology.) 1-Mbyte mode The addressing mode that allows code to resideanywhere in the 1-Mbyte addressing space. 64-Kbyte ...

Glossary-3 GLOSSARY far data Data that can be accessed only with extended instruc-tions. See also near data. FET Field-effect transistor. f Lowercase “f” represents the frequency of the internalclock. For the 8XC196NP, f is always equal to F XTAL 1 (the input frequency on XTAL1). For the 80C196NU,wh...

Glossary-5 GLOSSARY nonvolatile memory Read-only memory that retains its contents whenpower is removed. Many MCS ® 96 microcontrollers are available with either masked ROM, EPROM, orOTPROM. Consult the Automotive Products orEmbedded Microcontrollers databook to determinewhich type of memory is avail...

Glossary-6 8XC196NP, 80C196NU USER’S MANUAL PSW Processor status word. The high byte of the PSW isthe status byte, which contains one bit that globallyenables or disables servicing of all maskableinterrupts, one bit that enables or disables the PTS,and six Boolean flags that reflect the state of the...

Glossary-7 GLOSSARY reserved memory A memory location that is reserved for factory use orfor future expansion. Do not use a reserved memorylocation except to initialize it with FFH. sampled inputs All input pins, with the exception of RESET#, aresampled inputs. The input pin is sampled one statetime...

Glossary-8 8XC196NP, 80C196NU USER’S MANUAL special-purpose memory A partition of memory used for storing the interruptvectors, PTS vectors, chip configuration bytes, andseveral reserved locations. standard interrupt Any maskable interrupt that is assigned to theinterrupt controller for processing b...

Index-1 #, defined, 1-3, A-11-Mbyte mode, 5-1 fetching code, 5-23, 5-25fetching data, 5-26incrementing SP, 5-11memory configuration example, 5-31 64-Kbyte mode, 5-1, 5-5 fetching code, 5-23, 5-25fetching data, 5-26incrementing SP, 5-11memory configuration example, 5-27, 5-29 A A15:0, B-6A19:0, 5-1, ...

Index-3 INDEX CMP instruction, A-3, A-11, A-49, A-53, A-60CMPB instruction, A-3, A-12, A-50, A-53, A-60CMPL instruction, A-2, A-12, A-51, A-53, A-60Code execution, 2-4, 2-5Code fetches, 5-25CompuServe forums, 1-10Conditional jump instructions, A-5CON_REG0, C-50, C-53Constants, near, 5-24CPU, 2-3CS5:...

Index-5 INDEX device considerations, 11-1–11-11device reset, 11-8, 11-9, 11-10, 11-11interrupt processor, 2-6, 6-1minimum configuration, 11-1NMI considerations, 6-6noise protection, 11-4reset instruction, 4-14SIO port considerations, 8-6 HLDA#, 13-4, 13-30, B-8HLDEN bit, 5-14, 13-32Hold latency, See...

Index-7 INDEX map, A-2reserved, A-3, A-52 Operand types, See data typesOperands, addressing, 4-12Operating modes, 2-12 See also 1-Mbyte mode, 64-Kbyte mode OR instruction, A-2, A-33, A-49, A-54, A-61ORB instruction, A-2, A-33, A-49, A-54, A-61Oscillator and powerdown mode, 12-7external crystal, 11-6...

Index-9 INDEX See also windows Register RAM and idle mode, 12-5and powerdown mode, 12-7 Registers ACC_0x, 3-4ACC_STAT, 3-5allocating, 4-12EPA_MASK, 10-3EPA_PEND, 10-3EP_DIR, 7-12, 7-14, 7-16, 7-17EP_MODE, 7-12, 7-14, 7-16, 7-17, 7-18EP_PIN, 7-12, 7-14, 7-16, 7-17EP_REG, 7-12, 7-16, 7-17, 7-18 consid...

Index-11 INDEX T1DIR, 10-2, B-11T2CLK, 10-2, B-11T2CONTROL, C-51, C-54T2DIR, 10-2, B-11Technical support, 1-11Terminology, 1-3TIJMP instruction, A-2, A-44, A-51, A-57, A-64Timer/counters, 2-11, 10-5, 10-6 and PWM, 10-12, 10-13, 10-14, 10-15cascading, 10-6configuring pins, 10-2count rate, 10-6resolut...