Intel 41210 - Manual

vi Intel® 41210 Serial to Parallel PCI Bridge Design Guide Contents This page intentionally left blank .

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 7 About This Document 1 This document provides layout information and guidelines for designing platform or add-in board applications with the Intel ® 41210 Serial to Parallel PCI Bridge (also called the 41210 Bridge). It is recommended that thi...

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 9 Introduction 2 The Intel ® 41210 Serial to Parallel PCI Bridge integrates two PCI Express-to-PCI bridges. Each bridge follows the PCI-to-PCI Bridge programming model. The PCI Express port is compliant to the PCI Express Specification , Revisi...

10 Intel® 41210 Serial to Parallel PCI Bridge Design Guide Introduction • Tunable inbound read prefetch algorithm for PCI MRM/MRL commands • Local initialization via SMBus • Secondary side initialization via Type 0 configuration cycles. 2.3 Power Management • Support for PCI Express Active State Pow...

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 11 Introduction 2.4.2 Microcontroller Connections to the 41210 Bridge The following diagram shows the SMB interface from the 41210 Bridge to the microcontroller. Figure 1. 41210 Bridge Microcontroller Block Diagram B2707-01 Configuration Regist...

12 Intel® 41210 Serial to Parallel PCI Bridge Design Guide Introduction 2.5 JTAG • Compliant with IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1a 2.6 Related Documents • Intel® 41210 Serial to Parallel PCI Bridge Design Specification (EDS) , Revision 1.0. • PCI Express Specific...

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 15 Package Information 3 3.1 Package Specification The 41210 Bridge is in a 567-ball FCBGA package, 31mm X 31mm in size, with a 1.27mm ball pitch. Figure 5. Top View - 41210 Bridge 567-Ball FCBGA Package Dimensions Pkg_567-Ball_Top 0.550 in. Ha...

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Intel® 41210 Serial to Parallel PCI Bridge Design Guide 19 Power Plane Layout 4 This chapter provides details on the decoupling and voltage planes needed to bias the 41210 Bridge package. 4.1 41210 Bridge Decoupling Guidelines Table 2 lists the decoupling guidelines for the 41210 Bridge. Figure 8 an...

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 21 Power Plane Layout Table 2. 41210 Bridge Decoupling Guidelines 4.2 Split Voltage Planes There are two 1.5V voltage planes that supply power to the 41210 Bridge: • VCC15:1.5V ±5% (1.5V core voltage) • VCCPE:1.5V ±3% (1.5V PCI Express voltage)...

22 Intel® 41210 Serial to Parallel PCI Bridge Design Guide Power Plane Layout Note: Linear voltage regulators are recommended when using 1.5 Volt power supplies. Figure 10. 41210 Bridge Single-Layer Split Voltage Plane B2715-01 re Core PCI Express

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 23 41210 Bridge Reset and Power Timing Considerations 5 This chapter describes the 41210 Bridge reset timing considerations. 5.1 A_RST#,B_RST# and PERST# Timing Requirements The PCI-X Specification requires that there is a 100ms delay from vali...

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 25 General Routing Guidelines 6 This chapter provides some basic routing guidelines for layout and design of a printed circuit board using the 41210 Bridge. The high-speed clocking required when designing with the 41210 Bridge requires special ...

26 Intel® 41210 Serial to Parallel PCI Bridge Design Guide General Routing Guidelines • Avoid slots in the ground plane. Slots increases mutual inductance thus increasing crosstalk. • Make sure that ground plane surrounding connector pin fields are not completely cleared out. When this area is compl...

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 27 General Routing Guidelines 6.4 Power Distribution and Decoupling Have ample decoupling to ground, for the power planes, to minimize the effects of the switching currents. Three types of decoupling are: the bulk, the high-frequency ceramic, a...

28 Intel® 41210 Serial to Parallel PCI Bridge Design Guide General Routing Guidelines Note: Using stripline transmission lines may give better results than microstrip. This is due to the difficulty of precisely controlling the dielectric constant of the solder mask, and the difficulty in limiting th...

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 29 Board Layout Guidelines 7 This chapter provides details on adapter card stackup suggestions. It is highly recommended that signal integrity simulations be run to verify each 41210 Bridge PCB layout especially if it deviates from the recommen...

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 31 PCI-X Layout Guidelines 8 This chapter describes several factors to be considered with a 41210 Bridge PCI/PCI-X design. These include the PCI IDSEL, PCI RCOMP, PCI Interrupts and PCI arbitration. 8.1 Interrupts PCI Express provides interrupt...

32 Intel® 41210 Serial to Parallel PCI Bridge Design Guide PCI-X Layout Guidelines Note: PCI Express Assert_INTx/Deassert_INTx messages are not inhibited by the BME bit. 8.1.1 Interrupt Routing for Devices Behind a Bridge Given the legacy interrupt sharing scheme shown in Table 4 , to get the best l...

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 33 PCI-X Layout Guidelines • Priority group for a master (i.e., whether a master is in low priority group or high priority group). • Bus parking on last PCI agent or the bridge. By default the arbiter parks the bus on the bridge and drives the ...

34 Intel® 41210 Serial to Parallel PCI Bridge Design Guide PCI-X Layout Guidelines Table 7. PCI/PCI-X Frequency/Mode Straps Note: All signals sampled on the rising edge of PERST# . 8.3.1 PCI Pullup Resistors Not Required PCI control signals on the 41210 Bridge do NOT require pullup resistors on the ...

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 35 PCI-X Layout Guidelines B_CBE#[7:4], B_DEVSEL#, B_FRAME#, B_INTA#, B_INTB#, B_INTC#, B_INTD#, B_IRDY#, B_PERR#, B_PAR, B_GNT#[5:0], B_REQ#[5:0], B_LOCK#, B_PAR64, B_REQ64#, B_SERR#, B_STOP#, and B_TRDY#. 8.4 PCI Clock Layout Guidelines The P...

38 Intel® 41210 Serial to Parallel PCI Bridge Design Guide PCI-X Layout Guidelines 8.5 PCI-X Topology Layout Guidelines The PCI-X Addendum to the PCI Local Bus Specification , Revision 1.0b compliant, recommends the following guidelines for the number of loads for your PCI-X designs. Any deviation f...

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 39 PCI-X Layout Guidelines 8.6.1 Embedded PCI-X 133 MHz This section lists the routing recommendations for PCI-X 133 MHz without a slot. Figure 18 shows the block diagram of this topology and Table 10 describes the routing recommendations. Figu...

40 Intel® 41210 Serial to Parallel PCI Bridge Design Guide PCI-X Layout Guidelines 8.6.2 Embedded PCI-X 100 MHz This section lists the embedded routing recommendations for PCI-X 100 MHz. Figure 19 shows the block diagram of this topology and Table 11 describes the routing recommendations. Figure 19....

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 41 PCI-X Layout Guidelines 8.6.3 PCI-X 66 MHz Embedded Topology Figure 20 and Table 12 provide routing details for a topology with an embedded PCI-X 66 MHz application. Figure 20. PCI-X 66 MHz Embedded Routing Topology Table 12. PCI-X 66 MHz Em...

42 Intel® 41210 Serial to Parallel PCI Bridge Design Guide PCI-X Layout Guidelines 8.6.4 PCI 66 MHz Embedded Topology Figure 21 and Table 13 provide routing details for a topology with an embedded PCI 66 MHz design. P Figure 21. PCI 66 MHz Embedded Topology Table 13. PCI 66 MHz Embedded Table Parame...

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 43 PCI-X Layout Guidelines 8.6.5 PCI 33 MHz Embedded Mode Topology Figure 22 and Table 14 provide routing details for a topology with an embedded PCI 33 MHz design. Figure 22. PCI 33 MHz Embedded Mode Routing Topology Table 14. PCI 33 MHz Embed...

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 45 PCI Express Layout 9 This section provides an overview of the PCI-Express stackup recommended based on Intel presimulation results. For additional information, refer to the Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual or the...

46 Intel® 41210 Serial to Parallel PCI Bridge Design Guide PCI Express Layout 9.2 PCI-Express Layout Guidelines The layout guidelines for PCI-Express were developed for an adapter card topologies. The models and assumptions used in development of these guidelines were as follows: • Add-In Card Stack...

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 49 Circuit Implementations 10 This chapter describes 41210 Bridge circuit implementations. 10.1 41210 Bridge Analog Voltage Filters The Intel® 41210 Serial to Parallel PCI Bridge requires several external analog voltage filter circuits to be pl...

50 Intel® 41210 Serial to Parallel PCI Bridge Design Guide Circuit Implementations 10.1.1 PCI Analog Voltage Filters The following filter circuit is recommended for the PCI interface. Three separate, identical versions of this circuit should be placed on the system board, one for each VCCAPCI[2:0] p...

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 51 Circuit Implementations Figure 24. PCI Express Analog Voltage Filter Circuit Note: . • Place C as close as possible to package pin. • R must be placed between VCC15 and L. • Route VCCAPE and VSSAPE as differential traces. • VCCAPE and VSSAPE...

54 Intel® 41210 Serial to Parallel PCI Bridge Design Guide Circuit Implementations 10.2.1 SM Bus The SMBus interface does not have configuration registers. The SMBus address is set by the states of pins SMBUS[5] and SMBUS [3:1] when PERST# is asserted as described in Table 17 . Refer to Section 2.4 ...

56 Intel® 41210 Serial to Parallel PCI Bridge Design Guide 41210 Bridge Customer Reference Boards 11.2 Material The following materials are used with the 41210 Bridge CRB: • FR-4, 0.062 in. +/- .007, 1.0 oz Copper Power/GND. • Full length PCI Raw Card (3.3V Universal) 6.2” high x 7.00” long max with...

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 57 41210 Bridge Customer Reference Boards 11.4 Board Outline Figure 27 provides the mechanical outline of the 41210 Bridge CRB. Figure 27. Mechanical Outline of the 41210 Bridge B2728 -01 U1 Intel fi 41210 Bridge

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 59 Design Guide Checklist 12 This checklist highlights design considerations that should be reviewed prior to manufacturing an adapter card that implements the 41210 Bridge product. The items contained within this checklist attempt to address i...