Page 3 - Contents
315889-002 3 Contents 1 Applications ............................................................................................................... 9 1.1 Introduction and Terminology ............................................................................... 9 2 Output Voltage Requirements .......
Page 4 - Manufacturing Considerations; Figures; Impedance Z
4 315889-002 8.10 Safety - PROPOSED ...........................................................................................46 9 Manufacturing Considerations ..................................................................................47 9.1 Lead Free (Pb Free) .................................
Page 6 - Revision History
6 315889-002 Revision History Rev # Description Rev. Date 001 • Initial Release November 2006 002 • General- Update Harpertown and Wolfdale-DP to public names• Table 2-3 correction - Loadline ID codes for 5400/5200 series processors April 2008
Page 9 - Applications; Introduction and Terminology; VRM; VRM/EVRD 11.0 Supported Platforms and Processors
315889-002 9 Applications 1 Applications 1.1 Introduction and Terminology This document defines the DC-to-DC converters to meet the processor power requirements of the following platforms: The requirements in this document will focus primarily on the Enterprise processors based on Dual-Core Intel ® ...
Page 10 - • Tighter DC load line tolerance from ±20 mV to ±15 mV
Applications 10 315889-002 • New power-on sequence• Extended VR 10.x VID table with a 7th bit for 6.25 mV resolution and 0.83125 V to 1.6 V range, only 12.5 mV resolution will be used in Dual-Core Intel Xeon Processor-Based Platform and Intel E8500 platforms. • Support for a separate additional VR 1...
Page 11 - Output Voltage Requirements; Voltage and Current - REQUIRED; Processor VID signal implementation
315889-002 11 Output Voltage Requirements 2 Output Voltage Requirements 2.1 Voltage and Current - REQUIRED There will be independent selectable voltage identification (VID) codes for the core voltage regulator. The VID code is provided by the processor to the VRM/EVRDs, which will determine a refere...
Page 12 - Sustained Curr
Output Voltage Requirements 12 315889-002 The continuous load current ( I CCTDC ) can also be referred to as the Thermal Design Current (TDC). It is the sustained DC equivalent current that the processor is capable of drawing indefinitely and defines the current that is used for the voltage regulato...
Page 13 - Load Line Definitions - REQUIRED; Icc Guidelines
315889-002 13 Output Voltage Requirements Notes: 1. These values are either pre-silicon or the latest known values and are subject to change. See the respective Processor’s Electrical, Mechanical, and Thermal Specifications (EMTS) for the latest IccTDC and IccMAX specifications. 2. FMB = Planned Fle...
Page 14 - LGA771-V2 Voltage Test Tool
Output Voltage Requirements 14 315889-002 The upper and lower load lines represent the allowable range of voltages that must be presented to the processor. The voltage must always stay within these boundaries for proper operation of the processor. Operating above the V CCMAX load line limit will res...
Page 15 - Voltage Tolerance - REQUIRED; The voltage ranges shown in
315889-002 15 Output Voltage Requirements Notes: 1. The Vcc values are the expected voltage measured at the processor die. 2. The Dual-Core Intel® Xeon® 7100 series / Dual-Core Intel® Xeon® processor 7000 sequence entry is required for backward compatibility for VR ‘modules’ only using the EVRD/VRM ...
Page 16 - Processor V; Overshoot - REQUIRED; and; in; bandwidth. The power delivery frequency response is largely; Figure 2-2. Processor Vcc Overshoot Example Waveform; Vo; : Overshoot time above VID; : Overshoot voltage above VID
Output Voltage Requirements 16 315889-002 2.4 Processor V CC Overshoot - REQUIRED The VRM/EVRD 11.0 is permitted short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high-to-low current load condition ( Figure 2-2 ). This overshoot cannot exceed VID + VOS_MAX....
Page 17 - Guide; Hz; VR BW; LL Max
315889-002 17 Output Voltage Requirements dependent upon the selection of the bulk capacitors, ceramic capacitors, power plane routing and the tuning of the PWM controller’s feedback network. This analysis can be done with LGA771-V2 VTT tool impedance testing or through power delivery simulation if ...
Page 18 - Processor Power Sequencing - REQUIRED; Measurement Parameter Limits
Output Voltage Requirements 18 315889-002 3. See Section 2.5 and Table 2-4 , Impedance Measurement parameters and definitions Notes: 1. Z LL is the target impedance for each processor and Z(f) value coincides with it’s Load Line slope. 2. Z LLMAX is the max allowed Z LL tolerance, which still fits w...
Page 19 - VTT; VID bits; Startup Sequence Timing Parameters (Sheet 1 of 2)
315889-002 19 Output Voltage Requirements Notes: 1. VTT_PWRGD can be designed to be driving directly the OUTEN input. 2. Tb and Td voltage slopes are determined by soft start logic of the PWM controller. 3. Vboot is a default power-on Vcc (Core) value. Upon detection of a valid Vtt supply, the PWM c...
Page 20 - REQUIRED; The worst case settling time,; Startup Sequence Timing Parameters (Sheet 2 of 2)
Output Voltage Requirements 20 315889-002 Note: 1. Minimum delays must be selected in a manner which will guarantee compliance to voltage tolerance specifications. 2.8 Dynamic Voltage Identification (D-VID) - REQUIRED VRM/EVRD 11.0 supports dynamic VID across the entire VID table. The VRM/EVRD must ...
Page 21 - Figure 2-6. Dynamic VID Transition States Illustration
315889-002 21 Output Voltage Requirements Figure 2-6 is an example of dynamic VID. The diagram assumes steady state, constant current during the dynamic VID transition for ease of illustration; actual processor behavior allows for any dIcc/dt during the transitions, depending on the code it is execu...
Page 22 - Output Filter Capacitance - REQUIRED; and with the baseboard and processor; Recommended Decoupling and Other Specifications for Supported
Output Voltage Requirements 22 315889-002 2.9 Overshoot at Turn-On or Turn-Off - REQUIRED The core VRM/EVRD output voltage should remain within the load-line regulation band for the VID setting, while the VRM/EVRD is turning on or turning off, with no over or undershoot out of regulation. No negativ...
Page 23 - ). At least nine of the 10 μF capacitors should be placed in the; Delivery Impedance Model Path with 1206 Size Caps
315889-002 23 Output Voltage Requirements The platform processor decoupling design incorporates fifteen 560 µF Aluminum-polymer bulk capacitors and forty four 10 µF 1206 package ceramic high-frequency capacitors per processor for a 6 layer board, thirteen 560 µF Aluminum-polymer bulk capacitors and ...
Page 24 - requirements than described in this document.; Decoupling Capacitor Recommendations
Output Voltage Requirements 24 315889-002 Note: The amount of bulk decoupling needed is dependent on the voltage regulator design. Some multiphase buck regulators may have a higher switching frequency that would require a different output decoupling solution to meet the processor load line requireme...
Page 25 - Power Delivery Impedance Model Path - Example; Motherboard
315889-002 25 Output Voltage Requirements Notes: 1. Dual-Core Intel Xeon 5000 Series processors with Intel 5400 Chipsets platform has 8-layer stackup. Refer to the latest Dual-Core Intel Xeon 5000 Series processors with Intel 5400 Chipsets Platform Design Guide for baseboard stack-up details. 2. 9 o...
Page 27 - Control Signals; EXPECTED; EXPECTED
315889-002 27 Control Signals 3 Control Signals 3.1 Output Enable (OUTEN) - REQUIRED The VRM/EVRD must accept an input signal to enable its output voltage. When disabled, the regulator’s output should go to a high impedance state and should not sink or source current. When OUTEN is pulled low during...
Page 28 - Extended VR 10 Voltage Identification (VID) Table
Control Signals 28 315889-002 Note: An OFF VID code is equivalent to de-asserting the output enable input ( Section 3.1 ). Table 3-3. Extended VR 10 Voltage Identification (VID) Table VID4 VID3 VID2 VID1 VID0 VID5 VID6 Voltage VID4 VID3 VID2 VID1 VID0 VID5 VID6 Voltage 400 mV 200 mV 100 mV 50 mV 25 ...
Page 29 - . As a practical guideline to
315889-002 29 Control Signals Note: Only VID [6.0] are used for VRM/EVRD 11.0 platforms. The eighth VID bit is provisional for future Itanium-based platforms. 3.3 Differential Remote Sense (VO_SEN+/-) - REQUIRED The PWM controller shall include differential sense inputs to compensate for an output v...
Page 30 - the processor pin field.
Control Signals 30 315889-002 Notes: For each processor, refer to the appropriate platform design guide (PDG) for the recommended VR’s remote sense routing. The sense lines should be routed based on the following guidelines: • Route differentially with a maximum of 5 mils separation.• Traces should ...
Page 31 - VID Bit Mapping
315889-002 31 Control Signals 3.4 Load Line Select (LL0, LL1, VID_Select) - REQUIRED The VID_Select, LL1 and LL0 control signal form a 3-bit load line selection and will used to configure the VRM/EVRD to supply the proper load line for the processors. These signals are programmed by the CPU package ...
Page 33 - Input Voltage and Current; Input Voltages - EXPECTED; be coordinated between the baseboard and VRM designers.
315889-002 33 Input Voltage and Current 4 Input Voltage and Current 4.1 Input Voltages - EXPECTED The power source for the VRM/EVRD is 12 V +5% / –8%. This voltage is supplied by a separate power supply. For input voltages outside the normal operating range, the VRM/EVRD should either operate proper...
Page 35 - Processor Voltage Output; These are features built into the VRM/EVRD to
315889-002 35 Processor Voltage Output Protection 5 Processor Voltage Output Protection These are features built into the VRM/EVRD to prevent fire, smoke or damage to itself, the processor, or other system components. 5.1 Over-Voltage Protection (OVP) - EXPECTED The OVP circuit monitors the processo...
Page 37 - Output Indicators; shows the; VR_Ready Specifications
315889-002 37 Output Indicators 6 Output Indicators 6.1 Voltage Regulator Ready (VR_Ready) - REQUIRED The VRM/EVRD VR_Ready signal is an output signal that indicates the start-up sequence is complete and the output voltage has moved to the programmed VID value. This signal will be used for start-up ...
Page 38 - PROPOSED
Output Indicators 38 315889-002 to the FORCEPR# pin or through system management logic. Assertion of this signal will lower processor power consumption and reduce current draw through the voltage regulator, resulting in lower component temperatures. Sustained assertion of the FORCEPR# pin will cause...
Page 41 - VRM – Mechanical Guidelines; VRM Connector - EXPECTED; . The VRM reference in; Connector Keying; Referencing; Pin Descriptions and Assignments; VRM 11.0 Connector Part Number and Vendor Name
315889-002 41 VRM – Mechanical Guidelines 7 VRM – Mechanical Guidelines 7.1 VRM Connector - EXPECTED The part number and vendor name for VRM 11.0 connectors that can be found in Table 7-1 . The VRM reference in Section 7.2 , Section 7.3 and Section 7.4 , is based on the Tyco*/Elcon* interface with t...
Page 42 - VRM 11.0 Connector Pin Descriptions
VRM – Mechanical Guidelines 42 315889-002 Note: VID7 bit is not routed from the PWM control IC to the VRM connector; VID7is to be held Low on the VRM board. Table 7-2. VRM 11.0 Connector Pin Descriptions Name Type Description Load_Current Output Analog signal representing the output load current OUT...
Page 43 - Mechanical Dimensions - PROPOSED; Gold Finger Specification
315889-002 43 VRM – Mechanical Guidelines 7.4 Mechanical Dimensions - PROPOSED The mechanical dimensions for the VRM 11.0 module and connector are shown in Figure 7-1 . 7.4.1 Gold Finger Specification The VRM board must contain gold lands (fingers) for interfacing with the VRM connector that is 1.50...
Page 44 - Component; View A; PCB Footprint; View B
VRM – Mechanical Guidelines 44 315889-002 § Figure 7-1. VRM 11.0 Module and Connector 96.52mm (3.80") MAX 65.34mm (2.57") MAX 93.34mm (3.675") MAX 13.50mm (0.531") 66.34mm (2.612") MAX 59.3mm (2.33") Ref. Component Keepout View A View A 15.50mm (0.610") 2X R2.00mm (R0.08&...
Page 45 - Environmental Conditions; Operating Temperature - PROPOSED; ) over an ambient temperature range of 0oC to +45oC with a; VRM Board Temperature - REQUIRED; 5% relative – operating
315889-002 45 Environmental Conditions 8 Environmental Conditions The VRM/EVRD design, including materials, should meet the environmental requirements specified below. 8.1 Operating Temperature - PROPOSED The VRM/EVRD shall meet all electrical requirements when operated at the Thermal Design Current...
Page 46 - Electrostatic Discharge - PROPOSED; three times in each of the orthogonal axes.; Electromagnetic Compatibility - PROPOSED
Environmental Conditions 46 315889-002 8.5 Altitude - PROPOSED 3.05 km [10 k feet] – operating 15.24 km [50 k feet] – non-operating 8.6 Electrostatic Discharge - PROPOSED Testing shall be in accordance with IEC 61000-4-2. Operating – 15 kV initialization level. The direct ESD event shall cause no ou...
Page 49 - Impedance Design; Introduction - PROPOSED; Microprocessor Voltage Regulator Validation Setup
315889-002 49 Z(f) Constant Output Impedance Design A Z(f) Constant Output Impedance Design A.1 Introduction - PROPOSED The VRM/EVRD performance specification is based on the concept of output impedance, commonly known as the load line. The impedance is determined by the Pulse Width Modulator (PWM) ...
Page 50 - Load Line
Z(f) Constant Output Impedance Design 50 315889-002 The impedance plot Z(f) shown in Figure A-2 can be divided up into three major areas of interest. • Low frequency, Zero Hz (DC) to the VR loop bandwidth. This is set by AVP and loop compensation of the VR controller or PWM control IC. • Middle freq...
Page 51 - . The transient load line is
315889-002 51 Z(f) Constant Output Impedance Design capacitors in parallel. The effect of the mid frequency resonant point must be investigated and validated with Vdroop testing to ensure any current load transient pattern, does not violate the V min load line. By defining the output impedance load ...
Page 52 - . The first harmonic values from the Fast Fourier; FFT
Z(f) Constant Output Impedance Design 52 315889-002 frequency applied by the application. Hence a better method is needed to extract the impedance profile with the VR operating. The following sections introduce the theory behind using a VTT tool to create an impedance profile for the VR system. A.2 ...
Page 53 - Results; shows the test platform with 10 560; of Voltage, Current and Impedance
315889-002 53 Z(f) Constant Output Impedance Design A.3 VTT Z(f) Measurement Method An electronic load that has the capability to change the repetition rate up to 3 MHz of the load step is needed. The Intel LGA771/775V2 VTT by Cascade Systems Design, will meet this requirement. By monitoring the VTT...
Page 54 - Figure A-5. Photo of Motherboard Analyzed Showing High Frequency
Z(f) Constant Output Impedance Design 54 315889-002 current was 40 A. The waveforms show the effect of capacitor depopulation on the impedance profile above 1 MHz as pairs of high frequency MLCC capacitors are removed (banks 1-9) per the bank designations depicted in Figure A-7 . Simulation comparis...
Page 56 - Output Decoupling Design Procedure; be approximately 1⁄2 the load line target impedance. For a 1.25 m; im
Z(f) Constant Output Impedance Design 56 315889-002 A.5 Output Decoupling Design Procedure 1. Select type and number of bulk capacitors. Normally the equivalent ESR needs to be approximately ½ the load line target impedance. For a 1.25 m Ω load line, the equivalent ESR should be less than 0.625 m Ω ...
