Intel 21555 - Manual - manualsarea.com

Page 3 - Contents

21555 Non-Transparent PCI-to-PCI Bridge User Manual 3 Contents Contents 1 Preface .......................................................................................................................................... 11 1.1 Cautions and Notes ........................................................

Page 6 - Figures

6 21555 Non-Transparent PCI-to-PCI Bridge User Manual Contents 16.7 Interrupt Registers ............................................................................................................ 170 16.8 Scratchpad Registers ............................................................................

Page 11 - Preface

21555 Non-Transparent PCI-to-PCI Bridge User Manual 11 Preface 1 A brief description of the contents of this manual follows. Chapter 1, “Preface” Provides information about the contents and organization of this book. Chapter 2, “Introduction” Provides an overview of the 21555 functionality and archi...

Page 12 - Cautions and Notes

12 21555 Non-Transparent PCI-to-PCI Bridge User Manual Preface 1.1 Cautions and Notes Caution: Cautions provide information to prevent damage to equipment or loss of data. Note: Notes emphasize particularly important information. 1.2 Data Units This manual uses the following data-unit terminology. 1...

Page 13 - Signal Nomenclature; Table 1. Signal Type Abbreviations

21555 Non-Transparent PCI-to-PCI Bridge User Manual 13 Preface 1.4 Signal Nomenclature 21555 device signal names are printed in lowercase type. Prefixes and suffixes are tagged with a leading or trailing letter and are delimited with an “_” underscore: • The prefix “p_” denotes a primary bus signal....

Page 14 - Register Abbreviations; Table 2. Register Abbreviations

14 21555 Non-Transparent PCI-to-PCI Bridge User Manual Preface 1.5 Register Abbreviations When a register is associated with the primary interface, its name is preceded with Primary. When a register is associated with the secondary interface, its name is preceded with Secondary. When a register is s...

Page 15 - Introduction; Comparing a 21555 to a Transparent PPB

21555 Non-Transparent PCI-to-PCI Bridge User Manual 15 Introduction 2 The Intel ® 21555 is a PCI peripheral device that performs PCI bridging functions for embedded and intelligent I/O applications. The 21555 has a 64-bit primary interface, a 64-bit secondary interface, and 66-MHz capability. In thi...

Page 16 - Figure 1. 21555 Intelligent Controller Application

16 21555 Non-Transparent PCI-to-PCI Bridge User Manual Introduction A primary goal of the PPB architecture is that PPB are transparent to devices and device drivers. For example, no changes are needed to a device driver when a PCI peripheral is located behind a PPB. Once configured during system ini...

Page 17 - Table 3. 21555 and PPB Feature Comparison

21555 Non-Transparent PCI-to-PCI Bridge User Manual 17 Introduction Table 3 shows compares a 21555 and to a transparent PPB. Table 3. 21555 and PPB Feature Comparison Feature Non-Transparent PPB or 21555 Transparent PPB Transaction forwarding • Adheres to PPB ordering rules. • Uses posted writes and...

Page 18 - Architectural Overview; Data Buffers

18 21555 Non-Transparent PCI-to-PCI Bridge User Manual Introduction 2.2 Architectural Overview This section describes the buffers, registers, and control logic of the 21555: 2.2.1 Data Buffers Data buffers include the buffers along with the associated data path control logic. Delayed transaction buf...

Page 20 - Special Applications; Primary Bus VGA Support; Secondary Bus VGA Support; Programming Notes; Addressing; Table 4. Decoded and Not Decoded Addresses

20 21555 Non-Transparent PCI-to-PCI Bridge User Manual Introduction 2.3 Special Applications 2.3.1 Primary Bus VGA Support The 21555 provides hardware support that allows configuration of itself as a Video Graphics Adapter (VGA) device. The primary class code should be preloaded through the serial R...

Page 21 - Transaction Forwarding

21555 Non-Transparent PCI-to-PCI Bridge User Manual 21 Introduction • Setting a translated base address for a downstream range to fall within an address range defined for upstream forwarding. This would cause the 21555 to respond as a target on the secondary bus to a downstream transaction that it h...

Page 23 - Signal Descriptions; Table 5. Signal Pin Functional Groups

21555 Non-Transparent PCI-to-PCI Bridge User Manual 23 Signal Descriptions 3 This chapter presents the theory of operation information about the PCI signal interface. See Chapter 16 for specific information about PCI registers. Table 5 describes the PCI signal groups, function, and provides a page r...

Page 24 - Primary PCI Bus Interface Signals

24 21555 Non-Transparent PCI-to-PCI Bridge User Manual Signal Descriptions 3.1 Primary PCI Bus Interface Signals Table 6 describes the primary PCI bus interface signals. The letters in the “Type” column are described in Table 1 . Table 6. Primary PCI Bus Interface Signals (Sheet 1 of 2) Signal Name ...

Page 26 - Primary PCI Bus Interface 64; Table 7. Primary PCI Bus Interface 64

26 21555 Non-Transparent PCI-to-PCI Bridge User Manual Signal Descriptions 3.2 Primary PCI Bus Interface 64 - Bit Extension Signals Table 7 describes the primary PCI bus interface 64-bit extension signals. The letters in the “Type” column are described in Table 1 . Table 7. Primary PCI Bus Interface...

Page 28 - Secondary PCI Bus Interface Signals

28 21555 Non-Transparent PCI-to-PCI Bridge User Manual Signal Descriptions 3.3 Secondary PCI Bus Interface Signals Table 8 describes the secondary PCI bus interface signals. The letters in the “Type” column are described in Table 1 . Table 8. Secondary PCI Bus Interface Signals (Sheet 1 of 2) Signal...

Page 30 - Secondary PCI Bus Interface 64; Table 9. Secondary PCI Bus Interface 64

30 21555 Non-Transparent PCI-to-PCI Bridge User Manual Signal Descriptions 3.4 Secondary PCI Bus Interface 64 - Bit Extension Signals Table 9 describes the secondary PCI bus interface 64-bit extension signals. The letters in the “Type” column are described in Table 1 . Table 9. Secondary PCI Bus Int...

Page 31 - Miscellaneous Signals; Table 10. Miscellaneous Signals

21555 Non-Transparent PCI-to-PCI Bridge User Manual 31 Signal Descriptions 3.5 Miscellaneous Signals Table 10 describes the miscellaneous signals. The letters in the “Type” column are described in Table 1 . s_par64 TS Secondary PCI interface upper 32 bits parity. The 21555 does not bus park this pin...

Page 33 - Address Decoding

21555 Non-Transparent PCI-to-PCI Bridge User Manual 33 Address Decoding 4 This chapter presents the theory of operation information about address mapping and decoding. See Chapter 16 for specific information about addressing registers. The following areas are covered: • Section 4.1, “CSR Address Dec...

Page 34 - CSR Address Decoding

34 21555 Non-Transparent PCI-to-PCI Bridge User Manual Address Decoding 4.1 CSR Address Decoding The 21555 implements a set of CSRs that are mapped in memory or in I/O space. The registers are mapped independently on the primary and secondary interfaces. The following BARs are used for CSR mapping: ...

Page 35 - Using the BAR Setup Registers; Figure 3. BAR Setup Register Example

21555 Non-Transparent PCI-to-PCI Bridge User Manual 35 Address Decoding 4.3.1 Using the BAR Setup Registers All downstream and upstream BARs have programmable sizes, and can be disabled so that they request no space. The Primary CSR and Downstream Memory 0 BAR cannot be totally disabled, as the 2155...

Page 36 - Direct Address Translation; Figure 4. Address Format

36 21555 Non-Transparent PCI-to-PCI Bridge User Manual Address Decoding 4.3.2 Direct Address Translation With the exception of secondary bus transactions falling into the Upstream Memory 2 address range (see Section 4.3.3 ) and all dual address transactions ( Section 4.3.5 ), the 21555 uses direct a...

Page 37 - Lookup Table Based Address Translation; Figure 5. Direct Offset Address Translation

21555 Non-Transparent PCI-to-PCI Bridge User Manual 37 Address Decoding This new base address, also called the translated base address, references a new location in the secondary bus address map. The offset is not affected. The process is similar for transactions forwarded from the secondary bus to ...

Page 38 - Table 11. Upstream Memory 2 Window Size

38 21555 Non-Transparent PCI-to-PCI Bridge User Manual Address Decoding The Upstream Memory 2 address range consists of a fixed number (64) of pages. The page size is programmable in the Chip Control 1 configuration register. Therefore, the size of the Upstream Memory 2 BAR is dependent on the page ...

Page 39 - Figure 7. Address Translation Using A Lookup Table

21555 Non-Transparent PCI-to-PCI Bridge User Manual 39 Address Decoding Figure 7 shows how a translated address is built using the lookup table, assuming a page size of 4 KB. Figure 8 shows an example of how different address regions might be forwarded upstream using the lookup table address transla...

Page 40 - Lookup Table Entry Format; Figure 8. Upstream Lookup Table Address Translation

40 21555 Non-Transparent PCI-to-PCI Bridge User Manual Address Decoding Note: The indirect access mechanism must be used only by one interface at a time. When access to the lookup table by multiple masters is possible, it is strongly recommended that the Generic Own bits or some other semaphore mech...

Page 41 - Forwarding of 64; Figure 9. Lookup Table Entry Format

21555 Non-Transparent PCI-to-PCI Bridge User Manual 41 Address Decoding Note: The lookup table is not cleared by reset. The lookup table must be initialized by the local processor before the Upstream Memory 2 Address range is used. 4.3.5 Forwarding of 64 - Bit Address Memory Transactions The 21555 c...

Page 42 - I/O Transaction Address Decoding; Indirect I/O Transaction Generation; Address Transaction Forwarding

42 21555 Non-Transparent PCI-to-PCI Bridge User Manual Address Decoding the Downstream memory 3 address range must be set to a non-zero value when the upper 32 bits are enabled (a base address of 0 is not allowed). . 4.4 I/O Transaction Address Decoding The 21555 provides a mechanism where one BAR o...

Page 44 - Subtractive Decoding of I/O Transactions; Configuration Accesses; Type 0 Accesses to 21555 Configuration Space

44 21555 Non-Transparent PCI-to-PCI Bridge User Manual Address Decoding 4.4.2 Subtractive Decoding of I/O Transactions The 21555 can be enabled to subtractively decode I/O transactions and forward these transactions to the opposite bus. No address translation is performed on subtractively decoded I/...

Page 45 - Initiation of Configuration Transactions by 21555

21555 Non-Transparent PCI-to-PCI Bridge User Manual 45 Address Decoding Accesses to the 21555 configuration space are not ordered with respect to transactions in the 21555 queues. That is, the 21555 responds immediately to configuration transactions regardless of what transactions exist in the upstr...

Page 47 - Table 12. Bar Summary

21555 Non-Transparent PCI-to-PCI Bridge User Manual 47 Address Decoding 4.6 21555 Bar Summary Table 12 shows a summary of the 21555 BARs. Table 12. Bar Summary Bar Size Address Translation Primary CSR and Downstream Memory 0 4 KB to 2 GB Low 4 KB: None Above 4KB boundary: Direct Offset Primary CSR I...

Page 49 - PCI Bus Transactions; Transactions Overview; Responds to transactions by asserting DEVSEL# with medium timing.

21555 Non-Transparent PCI-to-PCI Bridge User Manual 49 PCI Bus Transactions 5 This chapter presents the theory of operation information about PCI transactions. See Chapter 16 for specific information about PCI registers. The following sections are discussed: • Section 5.2, “Posted Write Transactions...

Page 50 - Posted Write Transactions

50 21555 Non-Transparent PCI-to-PCI Bridge User Manual PCI Bus Transactions 5.2 Posted Write Transactions This section discusses the following Posted Write Transactions: • Section 5.2.1, “Memory Write Transactions” on page 51 . • Section 5.2.2, “Memory Write and Invalidate Transactions” on page 51 ....

Page 51 - Memory Write Transactions; Memory Write and Invalidate Transactions

21555 Non-Transparent PCI-to-PCI Bridge User Manual 51 PCI Bus Transactions 5.2.1 Memory Write Transactions As a target, the 21555 disconnects memory write transactions at the following address boundaries: • An aligned 4KB address boundary. • An aligned page address boundary for upstream transaction...

Page 52 - bit Extension Posted Write Transaction; Memory Write and Invalidate

52 21555 Non-Transparent PCI-to-PCI Bridge User Manual PCI Bus Transactions When any of these conditions is not met, the 21555 uses the memory write command. When a subsequent cache line in the transaction does not have all bytes enabled, the 21555 terminates the MWI transaction and delivers the rem...

Page 53 - Memory Write Disconnect Mode

21555 Non-Transparent PCI-to-PCI Bridge User Manual 53 PCI Bus Transactions 5.2.4.3 Write-Through When the 21555 is able to obtain access to the target bus and start transferring write data to the target before the transaction has been terminated on the initiator bus, it automatically enters flow-th...

Page 54 - Delayed Write Transactions; conditionally asserts SERR# on the initiator bus. See

54 21555 Non-Transparent PCI-to-PCI Bridge User Manual PCI Bus Transactions 5.3 Delayed Write Transactions The 21555 uses delayed transactions when forwarding I/O writes from one PCI interface to the other. Delayed transactions are also used for CSR or configuration register writes that cause the 21...

Page 55 - Delayed Read Transactions; Table 13. Delayed Write Transaction Target Termination Returns

21555 Non-Transparent PCI-to-PCI Bridge User Manual 55 PCI Bus Transactions When the initiator repeats the transaction using the same address, bus command, write data, and byte enables, then the 21555 returns the appropriate target termination when ordering rules allow. Otherwise, the 21555 continue...

Page 56 - Nonprefetchable Reads; Table 14. Delayed Read Transaction Target Termination Returns

56 21555 Non-Transparent PCI-to-PCI Bridge User Manual PCI Bus Transactions The 21555 requests the target bus and initiates the delayed read transaction as soon as the 21555 ordering rules allow. See Section 5.7 . When the transaction is a nonprefetchable read as described in Section 5.4.1 , the 215...

Page 57 - Prefetchable Reads; Prefetchable Read Transactions Using the 64

21555 Non-Transparent PCI-to-PCI Bridge User Manual 57 PCI Bus Transactions 5.4.2 Prefetchable Reads The following transactions are considered by the 21555 to be prefetchable read transactions: • Transactions using the memory read line command. • Transactions using the memory read multiple command. ...

Page 58 - Prefetching; Table 15. Prefetch Boundaries

58 21555 Non-Transparent PCI-to-PCI Bridge User Manual PCI Bus Transactions When using the Quadword boundary, REQ64# asserts every time the transaction is Quadword-aligned (AD[3:0] = x000b). In some cases, the address is only 2 Dwords away from a cache line boundary, or a 4KB boundary. This means th...

Page 59 - Read Queue Full Threshold Tuning; Bit Transactions Initiated by the 21555

21555 Non-Transparent PCI-to-PCI Bridge User Manual 59 PCI Bus Transactions 5.4.4.3 Read Queue Full Threshold Tuning The 21555 implements read queue management control bits for each read data queue in the Chip Control 1 configuration register. These bits specify at what read-queue threshold the 2155...

Page 60 - Target Terminations; Target Terminations Returned by the 21555

60 21555 Non-Transparent PCI-to-PCI Bridge User Manual PCI Bus Transactions 5.6 Target Terminations This section describes the following target retries, target disconnects, and target aborts received and returned by the 21555. • Section 5.6.1, “Target Terminations Returned by the 21555” on page 60 ....

Page 61 - Transaction Termination Errors on the Target Bus; Ordering Rules

21555 Non-Transparent PCI-to-PCI Bridge User Manual 61 PCI Bus Transactions 5.6.2 Transaction Termination Errors on the Target Bus When the 21555 detects a target abort on the target bus, the 21555 sets the Received Target Abort in the Primary and Secondary Status register. See Table 62, “Primary an...

Page 65 - Initialization Requirements

21555 Non-Transparent PCI-to-PCI Bridge User Manual 65 Initialization Requirements 6 This chapter presents the theory of operation information about the 21555 initialization requirements. See Chapter 16 for specific information about the initialization registers. 6.1 Power Management, Hot-Swap, and ...

Page 66 - Reset Behavior

66 21555 Non-Transparent PCI-to-PCI Bridge User Manual Initialization Requirements 6.2 Reset Behavior The 21555 implements a primary reset input, p_rst_l, a secondary reset input s_rst_in_l, and a secondary reset output, s_rst_l. The 21555 also implements a Chip Reset bit and a Secondary Reset bit i...

Page 67 - Table 18. Reset Mechanisms

21555 Non-Transparent PCI-to-PCI Bridge User Manual 67 Initialization Requirements The secondary reset output, s_rst_l, is asserted and remains asserted when any of the following are true: • The 21555 primary reset input, p_rst_l, is asserted. • The 21555 secondary reset input, s_rst_in_l, is assert...

Page 68 - Central Function During Reset

68 21555 Non-Transparent PCI-to-PCI Bridge User Manual Initialization Requirements 6.2.1 Central Function During Reset The 21555 is selected to be the secondary bus central function when it detects pr_ad[6] low when s_rst_l is asserted. When the 21555 detects this condition, it immediately drives s_...

Page 69 - Local Processor Initialization; Without Serial Preload

21555 Non-Transparent PCI-to-PCI Bridge User Manual 69 Initialization Requirements 6.3.1 With SROM, Local, and Host Processors The following is the 21555 initialization procedure using all configuration mechanisms: 1. Serial Preload Upon deassertion of p_rst_l or completion of chip reset, the 21555 ...

Page 70 - Without Local Processor; Without Host Processor; Power Management Support

70 21555 Non-Transparent PCI-to-PCI Bridge User Manual Initialization Requirements The remainder of the 21555 configuration proceeds as described in Section 6.3.1 . 6.3.3 Without Local Processor Initialization of the 21555 is possible without a local processor, or without local processor interventio...

Page 71 - Transitions Between Power Management States; The 21555 asserts p_pme_l when all of the following are true:

21555 Non-Transparent PCI-to-PCI Bridge User Manual 71 Initialization Requirements 6.4.1 Transitions Between Power Management States The 21555 is put into a different power state by writing the Power State bits in the Power Management Control and Status configuration register. Table 19 shows the act...

Page 72 - Power Management Data Register; CompactPCI Hot; Overview of CompactPCI Controller Hardware Interface

72 21555 Non-Transparent PCI-to-PCI Bridge User Manual Initialization Requirements 6.4.3 Power Management Data Register The PCI Power Management specification defines an optional data register that can be used for static or dynamic data reporting. A Data Select field in the Power Management Control ...

Page 73 - Insertion and Removal Process; Figure 11. CompactPCI Hot

21555 Non-Transparent PCI-to-PCI Bridge User Manual 73 Initialization Requirements A CompactPCI hot-swap card also implements an indicator LED. When the LED is on, this indicates that the board can be removed from the slot. Software may choose to flash the LED to indicate an intermediate state as we...

Page 75 - Swap Insertion and Removal

21555 Non-Transparent PCI-to-PCI Bridge User Manual 75 Initialization Requirements When the INS_STAT bit is cleared, the card is ready for normal operation. When l_stat continues to be sampled low, that indicates that the ejector handle is closed (and the micro-switch is open), meaning the card rema...

Page 77 - Clocking; Primary and Secondary PCI Bus Clock Signals; Table 20. Primary and Secondary PCI Bus Clock Signals (Sheet 1 of 2)

21555 Non-Transparent PCI-to-PCI Bridge User Manual 77 Clocking 7 The 21555 supports two clock inputs, p_clk and s_clk. The signal p_clk corresponds to the primary interface and s_clk corresponds to the secondary interface. Both clocks must adhere to the PCI Local Bus specification. The 21555 may op...

Page 78 - Figure 13. Synchronous Secondary Clock Generation

78 21555 Non-Transparent PCI-to-PCI Bridge User Manual Clocking 7.2 21555 Secondary Clock Outputs When the secondary clock is not supplied independently, the secondary clock output implemented on the 21555 can be used in either synchronous or asynchronous mode. The 21555 secondary clock output, s_cl...

Page 79 - 6 MHz Support

21555 Non-Transparent PCI-to-PCI Bridge User Manual 79 Clocking 7.3 66 MHz Support The 21555 supports 66 MHz operation. It has two pins, p_m66ena and s_m66ena, that indicate whether the primary and secondary bus are operating at 66 MHz, respectively. Signal p_m66ena is an input-only pin. • When samp...

Page 81 - Parallel ROM Interface

21555 Non-Transparent PCI-to-PCI Bridge User Manual 81 Parallel ROM Interface 8 This chapter presents the theory of operation information about the 21555 Parallel ROM (PROM) interface. See Chapter 16 for specific information about the PROM registers. The 21555 supports the attachment of a standard P...

Page 84 - Parallel and Serial ROM Connection; Figure 14. Parallel and Serial ROM Connections

84 21555 Non-Transparent PCI-to-PCI Bridge User Manual Parallel ROM Interface 8.2 Parallel and Serial ROM Connection Figure 14 shows how a parallel and serial ROM can be connected to the 21555. This figure illustrates the connection of a 16MB ROM. When a smaller ROM is used, the address registers co...

Page 85 - Figure 15. PROM Read Timing

21555 Non-Transparent PCI-to-PCI Bridge User Manual 85 Parallel ROM Interface When a byte read of the PROM is performed, the 21555 follows this sequence on the ROM interface, also shown in Figure 15 . 1. The 21555 drives address bits [23:16] on the pr_ad[7:0] pins and asserts pr_ale_l to enable the ...

Page 86 - PROM Write by CSR Access; pr_cs_l according to the access time in the ROM Setup register.

86 21555 Non-Transparent PCI-to-PCI Bridge User Manual Parallel ROM Interface 8.4 PROM Write by CSR Access Byte writes of the PROM can be performed by CSR access of the Table 112, “ROM Control Register” on page 178 , Table 111, “ROM Address Register” on page 178 , and Table 110, “ROM Data Register” ...

Page 87 - PROM Dword Read; Figure 16. PROM Write Timing

21555 Non-Transparent PCI-to-PCI Bridge User Manual 87 Parallel ROM Interface . 8.5 PROM Dword Read A Dword read is performed on the PROM interface when a read is initiated on the primary bus whose address falls into the address range defined by the Table 107, “Primary Expansion ROM BAR” on page 175...

Page 88 - Access Time and Strobe Control; Figure 17. Read and Write Strobe Timing

88 21555 Non-Transparent PCI-to-PCI Bridge User Manual Parallel ROM Interface 8.6 Access Time and Strobe Control The 21555 controls both the access time and the read and write strobe timing through the ROM Setup CSR. The access time is specified as a multiple of the p_clk signal and must be set to 8...

Page 89 - Attaching Additional Devices to the ROM Interface

21555 Non-Transparent PCI-to-PCI Bridge User Manual 89 Parallel ROM Interface 8.7 Attaching Additional Devices to the ROM Interface The 21555 allows additional devices to be attached to the ROM interface. Two ROM interface signals are slightly redefined to support multiple devices by setting the Mul...

Page 90 - Figure 18. Attaching Multiple Devices on the ROM Interface

90 21555 Non-Transparent PCI-to-PCI Bridge User Manual Parallel ROM Interface . Figure 18. Attaching Multiple Devices on the ROM Interface A7473-01 OtherDeviceSelects Other Device Read StrobeOther Device Write StrobeOther Device DataOther Device Ready Line 21555 pr_ad[7:0] pr_wr_l pr_rd_l pr_cs_l(pr...

Page 91 - Serial ROM Interface; SROM Interface Signals; SROMSROM Preload Operation; Table 22. SROM Interface Signals

21555 Non-Transparent PCI-to-PCI Bridge User Manual 91 Serial ROM Interface 9 This chapter presents the theory of operation information about the 21555 Serial ROM (SROM) interface. See Chapter 16 for specific information about the SROM registers. The serial ROM interface is used to preload data into...

Page 92 - SROM Configuration Data Preload Format; SROM Operation by CSR Access

92 21555 Non-Transparent PCI-to-PCI Bridge User Manual Serial ROM Interface 9.3 SROM Configuration Data Preload Format Some fields of the 21555 configuration registers may be preloaded using the SROM interface. The first two bits read from the SROM after the completion of chip reset indicate whether...

Page 94 - Figure 19. SROM Write All Timing Diagram

94 21555 Non-Transparent PCI-to-PCI Bridge User Manual Serial ROM Interface Note: When a SROM access using the CSR mechanism is attempted when the SROM is not implemented, the ROM interface may hang. This prevents access to any PROMs that may be present. A chip reset may be needed to put the ROM int...

Page 95 - Figure 22. SROM Erase Timing Diagram

21555 Non-Transparent PCI-to-PCI Bridge User Manual 95 Serial ROM Interface Figure 22. SROM Erase Timing Diagram Figure 23. SROM Erase All Operation Figure 24. SROM Check Status Timing Diagram A7479-01 A8 A0 1 1 1 pr_ad[1] (sr_di) sr_cs pr_ad[0] (sr_ck) A7480-01 1 1 0 0 0 pr_ad[1] (sr_di) sr_cs pr_a...

Page 97 - Arbitration; Primary PCI Bus Arbitration Signals; Secondary PCI Bus Arbitration Signals; Table 23. Primary PCI Bus Arbitration Signals; Table 24. Secondary PCI Bus Arbitration Signals

21555 Non-Transparent PCI-to-PCI Bridge User Manual 97 Arbitration 10 This chapter describes the arbitration signals. It also describes how the 21555 implements primary and secondary PCI bus arbitration. See Chapter 16 for specific information about the Arbiter registers. 10.1 Primary PCI Bus Arbitr...

Page 98 - Primary PCI Bus Arbitration; Secondary Bus Arbitration Using the Internal Arbiter

98 21555 Non-Transparent PCI-to-PCI Bridge User Manual Arbitration 10.3 Primary PCI Bus Arbitration The 21555 implements primary PCI bus request and grant pins, p_req_l and p_gnt_l, that interface to an external primary bus arbiter. These pins are used when the 21555 wants to initiate a transaction ...

Page 99 - Figure 25. Secondary Arbiter Example

21555 Non-Transparent PCI-to-PCI Bridge User Manual 99 Arbitration . Each bus master, including the 21555, may be configured to be in either the low priority group or the high priority group by setting the corresponding priority bit in the Arbiter Control register in device-specific configuration sp...

Page 100 - Secondary Bus Arbitration Using an External Arbiter; Table 25. Arbiter Control Register

100 21555 Non-Transparent PCI-to-PCI Bridge User Manual Arbitration The 21555’s internal arbiter may be programmed to park the secondary PCI bus either at the last master to use the bus, or always on the 21555. In the former case, an initiator's secondary bus grant remains asserted unless and until ...

Page 101 - Interrupt and Scratchpad Registers; Primary and Secondary PCI Bus Interrupt Signals; describes the primary and secondary PCI bus interrupt signals.; Interrupt Support; Table 26. Primary and Secondary PCI Bus Interrupt Signals

21555 Non-Transparent PCI-to-PCI Bridge User Manual 101 Interrupt and Scratchpad Registers 11 This chapter presents the theory of operation information about the 21555 interrupt handling and about the 32-bit scratchpad registers. See Chapter 16 for specific information about these registers. 11.1 Pr...

Page 103 - Doorbell Interrupts; Scratchpad Registers

21555 Non-Transparent PCI-to-PCI Bridge User Manual 103 Interrupt and Scratchpad Registers 11.3 Doorbell Interrupts A 16-bit software controlled interrupt request register and an associated 16-bit mask register is implemented for each interface (primary and secondary). Each register is byte addressa...

Page 105 - Error Handling; Error Signals; Primary PCI Bus Error Signals; Table 27. Primary PCI Bus Error Signals

21555 Non-Transparent PCI-to-PCI Bridge User Manual 105 Error Handling 12 This chapter presents the theory of operation information about the 21555 Error handling capability. See Chapter 16 for specific information about the Error registers. 12.1 Error Signals This section describes both the primary...

Page 106 - Secondary PCI Bus Error Signals; Table 28. Secondary PCI Bus Arbitration Signals

106 21555 Non-Transparent PCI-to-PCI Bridge User Manual Error Handling 12.1.2 Secondary PCI Bus Error Signals Table 28 describes the secondary PCI bus error signals . Table 28. Secondary PCI Bus Arbitration Signals Signal Name Type Description s_perr_l STS Secondary PCI interface PERR#. Signal s_per...

Page 107 - Parity Errors

21555 Non-Transparent PCI-to-PCI Bridge User Manual 107 Error Handling 12.2 Parity Errors The 21555 checks, forwards, and generates parity on both the primary and secondary buses. When forwarding transactions, the 21555 forwards the data parity condition as queued, whether it is bad parity or good p...

Page 111 - JTAG Test Port; JTAG Signals; Table 30. JTAG Signals

21555 Non-Transparent PCI-to-PCI Bridge User Manual 111 JTAG Test Port 13 This chapter presents the theory of operation information about the 21555 JTAG interface. See Chapter 16 for specific information about the JTAG registers. The 21555’s implementation of the JTAG test port is according to IEEE ...

Page 112 - Test Access Port Controller; Initialization; Asynchronously with the assertion of trst_l .

112 21555 Non-Transparent PCI-to-PCI Bridge User Manual JTAG Test Port 13.2 Test Access Port Controller The test access port controller is a finite-state machine that interprets IEEE 1149.1 protocols received through the tms signal. The state transitions in the controller are caused by the tms signa...

Page 113 - I2O Support; Inbound Message Passing

21555 Non-Transparent PCI-to-PCI Bridge User Manual 113 I2O Support 14 This chapter presents the theory of operation information about the 21555 I20 support. See Chapter 16 for specific information about I20 registers. The 21555 implements an I2O messaging unit to allow passing of I2O messages betwe...

Page 115 - Outbound Message Passing

21555 Non-Transparent PCI-to-PCI Bridge User Manual 115 I2O Support processor removes the message from the Inbound Post_List, it must write bit 31 of the Inbound Post_List counter with a 0, which causes the 21555 to decrement the Inbound Post_List counter by 1. When the counter decrements to zero, t...

Page 116 - Notes

116 21555 Non-Transparent PCI-to-PCI Bridge User Manual I2O Support and asserts p_inta_l to indicate to the host processor that one or more MFAs exist in the Outbound Post_List . Signal p_inta_l remains asserted until either the Outbound Post_List Counter is zero and the outbound prefetch buffer emp...

Page 119 - VPD Support; Reading VPD Information

21555 Non-Transparent PCI-to-PCI Bridge User Manual 119 VPD Support 15 This chapter presents the theory of operation information about the 21555 Vital Product Data (VPD) support. See Chapter 16 for specific information about the VPD registers. The 21555 provides VPD support through its serial ROM in...

Page 120 - Writing VPD Information

120 21555 Non-Transparent PCI-to-PCI Bridge User Manual VPD Support 15.2 Writing VPD Information A write can occur only to the last 2 Kb (256 bytes) of VPD Space. Valid VPD byte addresses for write operations are 17F:080h. To write VPD information from the serial ROM, the following steps must be tak...

Page 121 - List of Registers; Register Summary; — Y: accessible from both primary and secondary interface.

21555 Non-Transparent PCI-to-PCI Bridge User Manual 121 List of Registers List of Registers 16 This chapter contains reference information about all of the 21555 registers. Table 31 is a cross reference between the sections in this chapter to there accompanying theory of operation chapters. 16.1 Reg...

Page 122 - Configuration Registers; Table 32. Configuration Space Address Register (Sheet 1 of 5)

122 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers • “Via Setup” refers to the base address setup register corresponding to that BAR 16.2 Configuration Registers Table 32 lists the configuration space address registers. Table 32. Configuration Space Address Register (Sheet 1 o...

Page 123 - Table 32. Configuration Space Address Register (Sheet 2 of 5)

21555 Non-Transparent PCI-to-PCI Bridge User Manual 123 List of Registers 2F:2E6F:6E Subsystem ID Register, page 154 0000 Y Secondary Y 33:30 (P)73:70 (S) Primary Expansion ROM BAR, page 175 00000000 Via Setup Via Setup Y 3474 Enhanced Capabilities Pointer Register, page 154 DC — N Y 37:35 (P)77:75 ...

Page 124 - Table 32. Configuration Space Address Register (Sheet 3 of 5)

124 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers 7D (P)3D (S) Primary and Secondary Interrupt Pin Registers, page 155 00 — N Y 7E (P)3E (S) Primary and Secondary Minimum Grant Registers, page 155 00 Y N Y 7F (P)3F (S) Primary and Secondary Maximum Latency Registers, page 155...

Page 125 - Table 32. Configuration Space Address Register (Sheet 4 of 5)

21555 Non-Transparent PCI-to-PCI Bridge User Manual 125 List of Registers C7:C4 Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Setup Registers, page 138 00000000 Y Secondary Y CB:C8 Downstream Memory 0, 2, 3, and Upstream Memory 1 Setup Registers, page 139 00000000 Y Secondary Y CD:CC Chip ...

Page 126 - Control and Status Registers; Table 32. Configuration Space Address Register (Sheet 5 of 5)

126 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers 16.3 Control and Status Registers The control and status registers are memory mapped in the Primary CSR and Memory 0 Base Address window and the Secondary CSR Base Address window. These registers are I/O mapped in the Primary ...

Page 130 - Primary and Secondary Address; Table 34. Primary CSR and Downstream Memory 0 Bar

130 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers 16.4 Address Decoding 16.4.1 Primary and Secondary Address This section covers pages 16-130 through 16-140 and includes tables Table 34 through Table 60 . See Chapter 4 for theory of operation information. 0FF:0D0 Reserved 000...

Page 131 - Table 35. Secondary CSR Memory BARs

21555 Non-Transparent PCI-to-PCI Bridge User Manual 131 List of Registers 3 Prefetchable R Indicates whether the region is prefetchable. Accesses to the 21555 registers are disconnected after the first data phase. • When 0, nonprefetchable memory is requested. • When 1, prefetchable memory is reques...

Page 132 - Table 36. Primary and Secondary CSR I/O Bars

132 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers 3 Prefetchable R Indicates if this space is prefetchable. • When a 0, do not use prefetching when reading the 21555 registers. 11:4 — R Returns zero. 31:12 Base Address R/W Indicate to configuration software the size of the re...

Page 133 - Table 37. Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR

21555 Non-Transparent PCI-to-PCI Bridge User Manual 133 List of Registers Table 37. Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR Bit Name R/W Description 0 Space Indicator R • When a 0, this BAR is disabled or memory space is requested memory space. • When a one (1), I/O space is requ...

Page 134 - Table 38. Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR

134 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers Table 38. Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR Bit Name R/W Description 0 Space Indicator R Reads only as 0 to indicate that memory space is requested. 2:1 Type R Indicates size and location of this address...

Page 135 - Table 39. Upper 32 Bits Downstream Memory 3 Bar

21555 Non-Transparent PCI-to-PCI Bridge User Manual 135 List of Registers Table 39. Upper 32 Bits Downstream Memory 3 Bar • Primary byte offset: 27:24h • Secondary byte offset: 67:64h Bit Name R/W Description 31:0 Base Address R/W This register defines the upper 32 bits of a memory range for downstr...

Page 140 - Configuration Transaction Generation Registers; Table 45. Upper 32 Bits Downstream Memory 3 Setup Register

140 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers 16.4.2 Configuration Transaction Generation Registers All of these registers are mapped into the 21555 configuration space and described in Section 16.4.2 . Note that the 21555 initiates a transaction only when the Configurati...

Page 142 - Table 48. Configuration Own Bits Register

142 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers Table 47. Downstream Configuration Data and Upstream Configuration Data Registers These registers are also mapped in memory and I/O space. This register is treated as a reserved register for all memory accesses. Bit Name R/W D...

Page 144 - Table 50. Downstream I/O Address and Upstream I/O Address Registers

144 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers 9 Upstream Configuration Control R/W Enables the 21555 to perform upstream indirect configuration transactions. • When 0, the 21555 will not initiate a configuration transaction on the primary interface when the Upstream Confi...

Page 145 - Table 51. Downstream I/O Data and Upstream I/O Data Registers

21555 Non-Transparent PCI-to-PCI Bridge User Manual 145 List of Registers Table 51. Downstream I/O Data and Upstream I/O Data Registers The Downstream I/O Data register is used for I/O transactions to be initiated on the secondary bus, and the Upstream I/O Data register is used for I/O transactions ...

Page 146 - Table 54. Lookup Table Offset Register

146 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers Table 53. I/O CSR • Byte Offset: 027:026h Bit Name R/W Description 0 Downstream I/O Own Bit Status R This bit reflects the status of the Secondary Own bit used for generating I/O transaction on the secondary bus. • When 0, the...

Page 147 - PCI Registers; Table 55. Lookup Table Data Register; Table 56. Upstream Memory 2 Lookup Table

21555 Non-Transparent PCI-to-PCI Bridge User Manual 147 List of Registers 16.5 PCI Registers This section covers pages 16-147 through 16-165 and Table 57 through Table 80 . See Chapter 3 or Chapter 5 for theory of operation information. 16.5.1 Configuration Registers The registers described in this ...

Page 148 - Table 57. Primary Interface Configuration Space Address Map

148 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers Table 57. Primary Interface Configuration Space Address Map Byte 3 Byte 2 Byte 1 Byte 0 Primary Offset Secondary Offset Device ID 1 Vendor ID 1 00h 40h Primary Status Primary Command 04h 44h Primary Class Code 2 Revision ID 1 ...

Page 149 - Primary and Secondary Command Registers; Table 61. Primary and Secondary Command Registers (Sheet 1 of 2)

21555 Non-Transparent PCI-to-PCI Bridge User Manual 149 List of Registers 16.5.2 Primary and Secondary Command Registers The register types in this section have separate registers for the primary and secondary interfaces. However, the register description is given once, and applies to both the prima...

Page 150 - Table 62. Primary and Secondary Status Registers

150 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers 7 Wait Cycle Control R Reads as zero to indicate the 21555 does not perform address or data stepping. 8 SERR# Enable R/W Controls the enable for SERR# on the corresponding interface. • When 0, SERR# cannot be driven by the 215...

Page 152 - Table 64. Primary and Secondary Class Code Registers

152 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers Table 64. Primary and Secondary Class Code Registers These registers may be preloaded through the serial ROM. The Primary Class Code register may also be programmed by the local processor before host configuration . Bit Name R...

Page 153 - Table 67. Header Type Register

21555 Non-Transparent PCI-to-PCI Bridge User Manual 153 List of Registers Table 66. Primary Latency and Secondary Master Latency Timer Registers Bit Name R/W Description 7:0 Master Latency Timer R/W Master latency timer for the corresponding interface. Indicates the number of PCI clock cycles from t...

Page 154 - Table 69. Subsystem Vendor ID Register

154 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers Pr Table 69. Subsystem Vendor ID Register • Primary byte offset: 2D:2Ch and 6D:6Ch • Secondary byte offset: 6D:6Ch and 2D:2Ch Bit Name R/W Description 15:0 Subsystem Vendor ID R/(WS) Identifies the vendor of the add - in card ...

Page 155 - Table 73. Primary and Secondary Interrupt Pin Registers

21555 Non-Transparent PCI-to-PCI Bridge User Manual 155 List of Registers Table 73. Primary and Secondary Interrupt Pin Registers Bit Name R/W Description 7:0 Interrupt Pin R This register indicates which PCI interrupt pin the 21555 uses on the corresponding bus. This is a read - only register and a...

Page 156 - Device; Specific Control and Status Address Map

156 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers 16.5.3 Device - Specific Control and Status Registers This section contains information about the device-specific control and status registers. Table 76. Device - Specific Control and Status Address Map Byte 3 Byte 2 Byte 1 By...

Page 162 - Table 79. Chip Status Register

162 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers 12 I20_ENA R/W Enables the I20 message unit. • When 0, the I20 message unit is disabled. Memory accesses to the Inbound and Outbound FIFO registers at CSR offsets 40h and 44h result in TRDY# and discarded data on writes, and T...

Page 164 - Table 80. Generic Own Bits Register

164 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers Table 80. Generic Own Bits Register The 21555 implements two generic own bits that can be accessed in either memory or I/O space from either the primary or secondary interface. These bits may be used as an aid to lock resource...

Page 165 - I2O Registers; Table 82. I2O Outbound Post_List Interrupt Mask

21555 Non-Transparent PCI-to-PCI Bridge User Manual 165 List of Registers 16.6 I2O Registers This section contains a description of the I2O registers. See Chapter 14 for theory of operation information. Table 81. I2O Outbound Post_List Status Byte Offset: 33:30h Bit Name R/W Description 2:0 Reserved...

Page 166 - Table 84. I2O Inbound Post_List Interrupt Mask; Table 85. I2O Inbound Queue

166 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers Table 84. I2O Inbound Post_List Interrupt Mask Byte Offset: 3F:3Ch Bit Name R/W Description 2:0 Reserved R Reserved. Read only as 0. 3 Inbound Post Mask R/W Interrupt mask for Inbound Post_List Status. • When 0, the 21555 asse...

Page 167 - Table 87. I2O Inbound Free_List Head Pointer; Table 88. I2O Inbound Post_List Tail Pointer; Table 89. I2O Outbound Free_List Tail Pointer; Table 90. I2O Outbound Post_List Head Pointer

21555 Non-Transparent PCI-to-PCI Bridge User Manual 167 List of Registers Table 87. I2O Inbound Free_List Head Pointer Byte Offsets: 04B:048h Bit Name R/W Description 1:0 Reserved R Reserved. Returns 0 when read. 31:2 Inbound Free Head Ptr R/W Specifies the local memory Dword address of the Inbound ...

Page 169 - Table 93. I2O Outbound Post_List Counter

21555 Non-Transparent PCI-to-PCI Bridge User Manual 169 List of Registers Table 93. I2O Outbound Post_List Counter Byte Offsets: 063:060h Bit Name R/W Description 15:0 Outbound Post Ctr R/(WS) When read, returns the number of entries in the Outbound Post_List. Increments by 1 when this location is w...

Page 170 - Interrupt Registers; Table 95. Chip Status CSR

170 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers 16.7 Interrupt Registers This section contains information about interrupt registers. See Chapter 11 for theory of operation information. Table 95. Chip Status CSR Byte Offsets: 083:082h Bit Name R/W Description 0 PM_D0 R/W1TC...

Page 171 - Table 97. Chip Clear IRQ Mask Register; Table 98. Upstream Page Boundary IRQ 0 Register

21555 Non-Transparent PCI-to-PCI Bridge User Manual 171 List of Registers Table 97. Chip Clear IRQ Mask Register Byte Offsets: 087:086h Bit Name R/W Description 0 Clr_D0M R/W1TC • When 0, signal s_inta_l is asserted on the 21555’s secondary interface when the corresponding chip event bit is a 1, ind...

Page 172 - Table 99. Upstream Page Boundary IRQ 1 Register; Table 100. Upstream Page Boundary IRQ Mask 0 Register; Table 101. Upstream Page Boundary IRQ Mask 1 Register

172 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers Table 99. Upstream Page Boundary IRQ 1 Register Byte Offset: 08F:08Ch Bit Name R/W Description 31:0 PAGE1_IRQ R/W1TC Each bit in this register corresponds to a page entry in the upper half of the Upstream Memory 2 range. Bit 0...

Page 173 - Table 102. Primary Clear IRQ and Secondary Clear IRQ Registers; Table 103. Primary Set IRQ and Secondary Set IRQ Registers

21555 Non-Transparent PCI-to-PCI Bridge User Manual 173 List of Registers Table 102. Primary Clear IRQ and Secondary Clear IRQ Registers These registers affect primary and secondary interrupts in the same way and are described together. Bit Name R/W Description 15:0 CLR_IRQ R/W1TC This register cont...

Page 174 - Table 106. Scratchpad 0 Through Scratchpad 7 Registers (Sheet 1 of 2)

174 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers 16.8 Scratchpad Registers See Chapter 11 for theory of operation information. Table 104. Primary Clear IRQ Mask and Secondary Clear IRQ Mask Registers Bit Name R/W Description 15:0 CLR_IRQM R/W1TC • When 0, an interrupt is gen...

Page 175 - PROM Registers; Table 107. Primary Expansion ROM BAR

21555 Non-Transparent PCI-to-PCI Bridge User Manual 175 List of Registers 16.9 PROM Registers This section describes the six PROM registers. See Chapter 8 for theory of operation information. . 31:0 SCRATCH3 R/W 0B7:0B4h 32-bit scratchpad register 3. 31:0 SCRATCH4 R/W 0BB:0B8h 32-bit scratchpad regi...

Page 176 - Table 108. Primary Expansion ROM Setup Register

176 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers Table 108. Primary Expansion ROM Setup Register This register may be preloaded by serial ROM or programmed by the local processor before host configuration. • Primary byte offset: C3:C0h • Secondary byte offset: C3:C0h Bit Nam...

Page 177 - Table 109. ROM Setup Register

21555 Non-Transparent PCI-to-PCI Bridge User Manual 177 List of Registers Table 109. ROM Setup Register Byte Offsets: 0C9:0C8h Bit Name R/W Description 1:0 Access Time R/W Number of p_clk cycles that pr_cs_l asserts low (in default mode) or pr_ale_l drives high (in multiple device mode) for a PROM o...

Page 178 - Table 111. ROM Address Register

178 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers Table 111. ROM Address Register Byte Offsets: 0CE:0CCh Bit Name R/W Description 23:0 ROM_ADDR R/W Contains the byte address of the PROM read or write access used when the PROM Start bit is set to a 1. Contains the byte address...

Page 179 - SROM Registers; Table 113. Mode Setting Configuration Register (Sheet 1 of 2)

21555 Non-Transparent PCI-to-PCI Bridge User Manual 179 List of Registers 16.10 SROM Registers This sections describes the SROM registers. See Chapter 9 for theory of operation information. 2 Read/Write Control R/W PROM read/write control bit. This bit may be written with the same CSR access that se...

Page 180 - Table 113. Mode Setting Configuration Register (Sheet 2 of 2)

180 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers 3 s_clk_o Enable R Indicates whether s_clk_o is enabled, determined by sampling pr_ad[5] during reset. • When 0, signal pr_ad[5] was sampled low, causing s_clk_o to be disabled. • When 1, signal pr_ad[5] was sampled high, caus...

Page 183 - Error Registers; Table 115. Arbiter Control Register

21555 Non-Transparent PCI-to-PCI Bridge User Manual 183 List of Registers 16.11 Arbiter Control This chapter describes the arbitration control registers. See Chapter 10 for theory of operation information. 16.12 Error Registers This section describes the primary and secondary SERR# disable registers...

Page 184 - Table 116. Primary SERR# Disable Register

184 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers Table 116. Primary SERR# Disable Register This register may be preloaded by serial ROM or programmed by the local processor before host configuration. This register controls the ability of the 21555 to assert p_serr_l for a pa...

Page 185 - Init; Table 118. Power Management ECP ID and Next Pointer Register; Table 117. Secondary SERR# Disable Register

21555 Non-Transparent PCI-to-PCI Bridge User Manual 185 List of Registers 16.13 Init Registers This section describes the Power management, Reset, and Hot-swap registers. See Chapter 2 for theory of operation information. 1 Upstream Delayed Read Transaction Discarded R/W Disables s_serr_l assertion ...

Page 186 - Table 119. Power Management Capabilities Register

186 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers . Table 119. Power Management Capabilities Register Bits [14:9,5,2:0] are loadable through the serial ROM or are programmable by the local processor. • Primary byte offset: DF:DEh • Secondary byte offset: DF:DEh Bit Name R/W D...

Page 187 - Table 120. Power Management Control and Status Register; Table 121. PMCSR Bridge Support Extensions

21555 Non-Transparent PCI-to-PCI Bridge User Manual 187 List of Registers Table 120. Power Management Control and Status Register Bits [14:13] are loadable by serial ROM or are programmable by the local processor. • Primary byte offset: E1:E0h • Secondary byte offset: E1:E0h Bit Name R/W Description...

Page 188 - Table 122. Power Management Data Register

188 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers Table 122. Power Management Data Register • Primary byte offset: E3h • Secondary byte offset: E3h Bit Name R/W Description 7:0 PM Data R Power Management Data register. Reflects one of eight bytes loaded by serial ROM, or read...

Page 189 - Table 124. CompactPCI Hot

21555 Non-Transparent PCI-to-PCI Bridge User Manual 189 List of Registers Table 124. CompactPCI Hot - Swap Capability Identifier and Next Pointer Register Bit Name R/W Description 7:0 HS ECP ID R Enhanced capabilities ID. Reads only as 06h to indicate that these are CompactPCI Hot - Swap registers. ...

Page 190 - JTAG; Registers; Table 125. CompactPCI Hot

190 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers 16.14 JTAG Registers This chapter presents the theory of operation information about the 21555 JTAG registers. See Chapter 13 for theory of operation information. 5:4 Reserved R Returns 0 when read. 6 REM STAT R/ W1TC Signal p...

Page 191 - Table 129. Boundary Scan Order; Table 127. Bypass Register

21555 Non-Transparent PCI-to-PCI Bridge User Manual 191 List of Registers Table 129. Boundary Scan Order TBD table lists the boundary-scan register order and the group disable controls. The group disable control either enables or tristates its corresponding group of bi-directional drivers. When the ...

Page 192 - VPD Registers; Table 130. Vital Product Data (VPD) ECP ID and Next Pointer Register

192 21555 Non-Transparent PCI-to-PCI Bridge User Manual List of Registers The group disable number column in TBD shows which group disable bit controls the corresponding output driver. Group disable bits do not affect input-only pins, so those pins have a blank rather than a group number in that col...

Page 193 - Table 132. VPD Data Register

21555 Non-Transparent PCI-to-PCI Bridge User Manual 193 List of Registers Table 131. Vital Product Data (VPD) Address Register • Primary byte offset: E7:E6h • Secondary byte offset: E7:E6h Bit Name R/W Description 8:0 VPD Addr R/W Vital Product Data Address. Contains the VPD byte address of the seri...

Page 195 - Acronyms

21555 Non-Transparent PCI-to-PCI Bridge User Manual 205 Acronyms A • 1D – One-dimensional • 2D – Two-dimensional • AGP – Accelerated Graphics Port • ANSI – American National Standards Institute • API – Application Programming Interface • BAR – Base Address Register • BiST – Built-In Self-Test • CLS ...

Page 197 - Index

21555 Non-Transparent PCI-to-PCI Bridge User Manual 197 Index 3-V 155-V 15Primary lockout bit on the PROM_AD 82 A Add-in card vendors 15address 33Address range locations Primary BARs 33Secondary BARs 33 Address space 34 64-bit 35expansion ROM decoding 34type of 130, 132type of for secondary 131 Addr...

Intel 21555 - Manual

Table of Contents:

Summary

Other Intel Models