Fujitsu MB89990 Series - Manual

iv FIGURES Figure 1.4-1 Pin Assignment (FPT-28P-M02, DIP-28P-M03) ........................................................................ 6 Figure 1.4-2 Pin Assignment (MQP-48C-P01) ................................................................................................ 7 Figure 2.1-1 Memor...

v TABLES Table 1.2-1 Types and Functions of MB89990 Series of Microcontrollers ..................................................... 3 Table 1.5-1 Pin Function Description .............................................................................................................. 8 Table 1.5-2 Pin...

1 CHAPTER 1 GENARAL The MB89990 series contains microcontrollers with a full range of resources such as timers, external interrupts, and remote-control function, as well as the F 2 MC-8L CPU core for low-voltage and high-speed operation. This single-chip microcontroller is suitable for small devices...

2 CHAPTER 1 GENARAL 1.1 Features This section describes the features. ■ Features • Minimum instruction execution time: 0.95 µ s at 4.2 MHz (V CC = 3 V) • CPU core common to F 2 MC-8L CPU • Instruction set suitable for controller: - Multiply/subtraction instruction, - 16-bit operation,- Instruction t...

3 1.2 Product Series 1.2 Product Series This section describes the product series. ■ Product Series Table 1.2-1 "Types and Functions of MB89990 Series of Microcontrollers"lists the types andfunctions of the MB89990 series of microcontrollers. Table 1.2-1 Types and Functions of MB89990 Series...

5 1.3 Block Diagram 1.3 Block Diagram This section describes the block diagram. ■ Block Diagram Main oscillator circuit Clock control Reset circuit Time-base timer RAM (128 x 8 bits) F 2MC-8L CPU ROM (32K x 8 bits) TEST Vcc, Vss Remote-control carrier frequency 8-bit timer/counter 8-bit timer/counte...

6 CHAPTER 1 GENARAL 1.4 Pin Assignment This section describes the pin assignment. ■ Pin Assignment Figure 1.4-1 Pin Assignment (FPT-28P-M02, DIP-28P-M03) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P04/INT24 P05/INT25 P06/INT26 P07/INT27 TEST RST X0 X1 V SS P37/RCO P36...

7 1.4 Pin Assignment Figure 1.4-2 Pin Assignment (MQP-48C-P01) 49 V PP 57 NC 65 04 73 OE 50 A12 58 A2 66 05 74 NC 51 A7 59 A1 67 06 75 A11 52 A6 60 A0 68 07 76 A9 53 A5 61 01 69 08 77 A8 54 A4 62 02 70 CE 78 A13 55 A3 63 03 71 A10 79 A14 56 NC 64 GND 72 NC 80 V CC 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34...

8 CHAPTER 1 GENARAL 1.5 Pin Function Description This section describes the pin functions. ■ Pin Function Description Table 1.5-1 "Pin Function Description" and Table 1.5-2 "Pins for External ROM" list the pinfunction and Table 1.5-3 "Input/Output Circuit Configurations" show...

11 1.5 Pin Function Description E • CMOS input/output • The pull-up resistor is available. F • N-ch open-drain output • Analog input • The pull-up resistor is available. (MB89990 series only) Table 1.5-3 Input/Output Circuit Configurations (Continued) Classification Circuit Remarks Pch Nch R Pch Nch...

12 CHAPTER 1 GENARAL 1.6 Handling Devices This section describes handling devices. ■ Handling Devices (1) Preventing latch-up Latch-up may occur if a voltage higher than V CC or lower than V SS is applied to the input or output pins other than middle- and high-level-resistant pins, or if voltage exc...

13 CHAPTER 2 HARDWARE CONFIGRATION This chapter describes each block of the CPU hardware. 2.1 CPU 2.2 Clock Control Block 2.3 Interrupt Controller 2.4 I/O Ports 2.5 8/16-bit Timer (Timer 1 and Timer 2) 2.6 External Interrupt 1 2.7 External Interrupt 2 (Wake up) 2.8 Remote-control Carrier Frequency G...

14 CHAPTER 2 HARDWARE CONFIGRATION 2.1 CPU • This section describes the memory space and register composing CPU hardware. ■ Memory Space The MB89990 series of microcontrollers have a memory area of 64K bytes. All I/O, data areas,and program areas are located in this space. The I/O area is at the low...

17 2.1 CPU The 16 bits of the processor status (PS) can be divided into 8 upper bits for a register bankpointer (RP) and 8 lower bits for a condition code register (CCR). (See Figure 2.1-4 "Structureof Processor Status".) Figure 2.1-4 Structure of Processor Status The RP indicates the addres...

18 CHAPTER 2 HARDWARE CONFIGRATION • General-purpose registers General-purpose registers are 8-bit long registers for storing data. The 8-bit long general-purpose registers are in the register banks in memory. One bank haseight registers and up to 16 banks are available for the MB89193 (8 banks for ...

19 2.2 Lock Control Block 2.2 Lock Control Block • This block controls the standby operation and software reset. ■ Machine Clock Control Block Diagram ■ Register List STP SLP SPL Clock control Pin stateStopSleep Clock generator CPU operation clockResource operation clock Selector 2 2 /f* 2 12 /f 2 1...

22 CHAPTER 2 HARDWARE CONFIGRATION • The input/output pins and output pins during the STOP state can be controlled by theSPL bit (bit5) of the STBC register so that they are held in the state immediately beforeentering the STOP state, or so that they enter in the high-impedance state. • If an interr...

25 2.3 Interrupt Controller 2.3 Interrupt Controller • The interrupt controller for the F 2 MC-8L family is located between the CPU and each resource. This controller receives interrupt requests from the resources, assigns priority to them, and transfers the priority to the CPU. It also decides the ...

26 CHAPTER 2 HARDWARE CONFIGRATION ■ Description of Registers The detail of each register is described below. (1) Interrupt levei setting register (ILR1 to ILR3) The ILRX sets the interrupt level of each resource. The digits in the center of each bitcorrespond to the interrupt numbers. When an inter...

28 CHAPTER 2 HARDWARE CONFIGRATION 2.4 I/O Ports • he MB89990 series of microcontrollers have three parallel ports and 22 pins. P00 to P07 and P30 to P37 serve as 8-bit I/O ports, P40 to P45 serve as 6-bit I/O ports. • Port0 and Port3 are also used as the I/O pin for the resource. ■ List of port fun...

29 2.4 I/O Ports ■ Description of Functions The function of each port is described below. • Switching input and output • This port has a data-direction register (DDR) and a port-data register (PDR) for each bit.Input and output can be set independently for each bit. The pin with the DDR set to 1 iss...

30 CHAPTER 2 HARDWARE CONFIGRATION Figure 2.4-1 Ports 00 to 07 and 30 to 37 • Operation for output port • The value written at the PDR is output to the pin. When the PDR is read in this port, thecontents of the output latch is always read instead of the value of the pin. • State when reset • The PDR...

31 2.4 I/O Ports Figure 2.4-2 Ports 40 to 45 Internal data bus Stop mode (SPL = 1) Pull-up resistor (option) Pin PDR Output latch PDR read (when Read Modify Write instruction is executed) PDR write Nch Pch PDR read Stop

33 2.5 8/16-bit Timer (Timer 1 and Timer 2) ■ Description of Register Details The detail of each register is described below. (1) Timer 1 control register (T1CR) [Bit 7] T1IF: Interrupt request flag (When write) (When read) 1 is always read when the Read Modify Write instruction is executed. [Bit 6]...

38 CHAPTER 2 HARDWARE CONFIGRATION (4) Precautions for use of timer stop bit Since an input clock pulse is fixed to High level when the timer is stopped by the timer start bits,the count value differs depending on the state of the input clock pulse. When writing 00 at the timer stop and timer start ...

39 2.6 External Interrupt 1 2.6 External Interrupt 1 • The edges of three external-interrupt sources (INT10 to INT12) can be detected to set the corresponding flag. • An interrupt can be generated at the same time the flag is set.• The three interrupts can release the STOP or SLEEP mode. ■ Block dia...

45 2.8 Remote-control Carrier Frequency Generator 2.8 Remote-control Carrier Frequency Generator • This generator is a remote-control circuit for generating remote-control carrier frequencies. • The 6-bit binary counter is built in.• Four internal clock pulses can be selected to set a duty (H width)...

46 CHAPTER 2 HARDWARE CONFIGRATION ■ Description of Registers (1) Remote-control register 1 (RCR1) This register is used to select the reference clock and set the duty of remote-control carrierfrequency. These bits are used to select the reference clock for the remote-control carrier frequency. [Bit...

48 CHAPTER 2 HARDWARE CONFIGRATION 2.9 Time-base Timer • This timer has a 20-bit binary counter and uses a clock pulse with 1/2 oscillation of the source clock. • Four interval times can be selected.• This function cannot be used in the STOP state. ■ Block Diagram *TBTC is a clock pulse with 1/2 osc...

49 2.9 Time-base Timer ■ Description of Registers The detail of time-base timer control register (TBCR) is described below. (1) Timer-base timer control register (TBCR) [Bit 4] TBIE: Interval-timer interrupt enable bit This bit is used to enable an interrupt by the interval timer. [Bit 3] TBOF: Inte...

50 CHAPTER 2 HARDWARE CONFIGRATION [Bit 1 and 0] TBC1, TBC0: Interval time specification bit These bits are used to specify interval timer cycle. TBC1 TBC0 Interval time Value at f = 4 MHz 0 0 2 13 /f 2.05 [ms] 0 1 2 15 /f 8.19 [ms] 1 0 2 18 /f 65.54 [ms] 1 1 2 21 /f 524.29 [ms] f = clock frequency

51 2.10 Watchdog Timer Reset 2.10 Watchdog Timer Reset • The watchdog timer is reset by using the time-base timer output as a clock. ■ Block Diagram ■ Registers The watchdog timer reset has watchdog timer control register (WDTE). ■ Description of Register The detail of the watchdog timer control reg...

53 CHAPTER 3 OPERATION The operation of MB89990 is described below. 3.1 Clock Pulse Generator 3.2 Reset 3.3 Interrupt 3.4 Low-power Consumption Modes 3.5 Pin States for Sleep, Stop and Reset

54 CHAPTER 3 OPERATION 3.1 Clock Pulse Generator This section describes the clock pulse generator. ■ Clock Pulse Generator The MB89990 series of microcontrollers incorporate the system clock pulse generator. Theceramic or crystal oscillator, or CR is connected to the X0 and X1 pins to generate clock...

55 3.2 Reset 3.2 Reset This section describes reset. ■ Reset The detail of reset operation and reset sources are described below.

56 CHAPTER 3 OPERATION 3.2.1 Reset Operation The reset operation is described below. ■ Reset Operation When reset conditions occur, the MB89990 series of microcontrollers suspend the currently-executing instruction to enter the reset state. The contents written at the RAM do not changebefore and aft...

57 3.2 Reset 3.2.2 Reset Source The reset sources are described below. ■ Reset Source The MB89990 series of microcontrollers have the following reset source. (1) External pin A Low level is input to the RST pin. (2) Specification by software 0 is written at the RST bit of the standby-control registe...

58 CHAPTER 3 OPERATION 3.3 Interrupt This section describes interrupt. ■ Interrupt If the interrupt controller and CPU are ready to accept interrupts when an interrupt request isoutput from the internal resources or by an external-interrupt input, the CPU temporarilysuspends the currently-executing ...

60 CHAPTER 3 OPERATION 3.4 Low-power Consumption Modes This section describes low-power consumption modes. ■ Low-power Consumption Modes The MB89990 series of microcontrollers have two standby modes: sleep and stop to reduce thepower consumption. Writing to the standby control register (STBC) switch...

61 3.5 Pin States for Sleep, Stop and Reset 3.5 Pin States for Sleep, Stop and Reset This section describes the pin states for sleep, stop, and reset. ■ Pin States for Sleep, Stop, and Reset The state of each pin of the MB89990 series of microcontrollers at sleep, stop, and reset is asfollows: (1) S...

63 CHAPTER 4 INSTRUCTIONS This chapter describes instructions. 4.1 Transfer Instructions 4.2 Operation Instruction 4.3 Branch Instructions 4.4 Other Instructions 4.5 F 2 MC-8L Family Instruction Map

64 CHAPTER 4 INSTRUCTIONS 4.1 Transfer Instructions This section describes the transfer instructions. ■ Transfer Instructions Mnemonic ~ # Operation TL TH AH N Z V C OP code MOV dir,AMOV @IX +off,AMOV ext,AMOV @EP,AMOV Ri,AMOV A,#d8MOV A,dirMOV A,@IX +offMOV A,extMOV A,@AMOV A,@EPMOV A,RiMOV dir,#d8...

66 CHAPTER 4 INSTRUCTIONS 4.2 Operation Instruction This section describes the operation instructions. ■ Operation Instructions Mnemonic ~ # Operation TL TH AH N Z V C OP code ADDC A,RiADDC A,#d8ADDC A,dirADDC A,@IX +offADDC A,@EPADDCW AADDC ASUBC A,RiSUBC A,#d8SUBC A,dirSUBC A,@IX +offSUBC A,@EPSUB...

67 4.2 Operation Instruction Mnemonic ~ # Operation TL TH AH N Z V C OP code AND AAND A,#d8AND A,dirAND A,@EPAND A,@IX +offAND A,RiOR AOR A,#d8OR A,dirOR A,@EPOR A,@IX +offOR A,RiCMP dir,#d8CMP @EP,#d8CMP @IX +off,#d8CMP Ri,#d8INCW SPDECW SP 223343223343545433 122121122121323211 (A) (AL) (TL) (A) (A...

68 CHAPTER 4 INSTRUCTIONS 4.3 Branch Instructions This section describes the branch instructions. ■ Branch Instructions Mnemonic ~ # Operation TL TH AH N Z V C OP code BZ/BEQ relBNZ/BNE relBC/BLO relBNC/BHS relBN relBP relBLT relBGE relBBC dir: b,relBBS dir: b,relJMP @AJMP extCALLV #vctCALL extXCHW ...

69 4.4 Other Instructions 4.4 Other Instructions This section describes the other instructions. ■ Other Instructions Mnemonic ~ # Operation TL TH AH N Z V C OP code PUSHW APOPW APUSHW IXPOPW IXNOPCLRCSETCCLRISETI 444411111 111111111 ––––––––– ––––––––– – dH ––––––– – – – –– – – –– – – –– – – –– – – ...

70 CHAPTER 4 INSTRUCTIONS 4.5 F 2 MC-8L Family Instruction Map This section describes the F 2 MC-8L family instruction map. ■ F 2 MC-8L Family Instruction Map 0 N O P S W A P R ET R E T I PU SH W A PO PW A MO V A, ex t MO V W A, PS C L R I SET I C L R B di r: 0 BB C di r: 0, rel I NCW A DE CW A JM P...

71 CHAPTER 5 MASK OPTIONS This chapter describes mask options. 5.1 Mask Options

72 CHAPTER 5 MASK OPTIONS 5.1 Mask Options This section describes the mask options. ■ Mask Options Table 5.1-1 Mask Options No. Part number MB89997 MB89P195 MB89PV190 Specifying procedure Specify when ordering masking Specify when ordering masking Fixed 1 Port pull-up resistors 00 to P07P30 to P37 S...

73 APPENDIX The appendix describes I/O map and EPROM setting for MB89P195. APPENDIX A I/ O Map APPENDIX B EPROM Setting for MB89P195

74 APPENDIX A I/O Map APPENDIX A I/O Map Appendix A describes the I/O map. ■ /O Map Address Read/write Register name Register description 00 H (R/W) PDR0 Port 0 data register 01 H (W) DDR0 Port 0 data direction register 02 H to 07 H Vacancy 08 H (R/W) STBC Standby control register 09 H (R/W) WDTC Wa...

76 APPENDIX B EPROM Setting for MB89P195 APPENDIX B EPROM Setting for MB89P195 Appendix B describes the EPROM setting for MB89P195. ■ EPROM Setting for MB89P195 MB89P195 is provided with the function corresponding to MBM27C256A by EPROM setting.The setting can be performed by writing program data wi...

77 INDEX INDEX The index follows on the next page.This is listed in alphabetic order.

78 INDEX Index Numerics 16-bit data in memory, arrangement of .................. 16 A arrangement of 16-bit data in memory ................... 16 B block diagram ................. 5, 25, 32, 39, 43, 45, 48, 51 branch instruction ................................................... 68 C clock pulse ge...

CM25-10133-2E FUJITSU SEMICONDUCTOR • MICROCONTROLLER MANUAL F 2 MC-8L FAMILY 8-BIT MICROCONTROLLER MB89990 Series HARDWARE MANUAL March 2000 the second edition Published FUJITSU LIMITED Electronic Devices Edited Technical Communication Dept.