Fujitsu MB15F74UV - Manual - manualsarea.com

Page 2 - PIN ASSIGNMENTS; TOP VIEW

MB15F74UV 2 (Continued) • Direct power saving function : Power supply current in power saving mode Typ 0.1 µ A (V CC = 3.0 V, Ta = + 25 ° C at 1 system) Max 10 µ A (V CC = 3.0 V at 1 system) • Software selectable charge pump current : 1.5 mA/6.0 mA Typ• Dual modulus prescaler : 4000 MHz prescaler (6...

Page 3 - PIN DESCRIPTION; Pin

MB15F74UV 3 ■ ■ ■ ■ PIN DESCRIPTION Pin no. Pin name I/O Descriptions 1 GND  Ground pin for OSC input buffer and the shift register circuit. 2 fin IF I Prescaler input pin for the IF-PLL.Connection to an external VCO should be AC coupling. 3 Xfin IF I Prescaler complimentary input for the IF-PLL se...

Page 4 - BLOCK DIAGRAM

MB15F74UV 4 ■ ■ ■ ■ BLOCK DIAGRAM (10) Clock Data LE PS RF Xfin RF fin RF OSC IN fin IF PS IF V CCIF GND IF fp IF Do IF LD IF T1 T2 T1 T2 FC RF SW RF LDS Do RF OR LD / fout LDfr IF fr RF fp IF fp RF fr IF fr RF fp RF CN 1 CN 2 AND V CCRF GND RF (18) ( ) (9) (16) (17) (11) (12) (8) (6) (4) (5) (2) (7...

Page 6 - ELECTRICAL CHARACTERISTICS

MB15F74UV 6 * ■ ■ ■ ■ ELECTRICAL CHARACTERISTICS (V CC = 2.7 V to 3.6 V, Ta = − 40 ° C to + 85 ° C) (Continued) Parameter Symbol Condition Value Unit Min Typ Max Power supply current I CCIF * 1 fin IF = 2000 MHz V CCIF = 3.0 V 2.1 2.5 3.2 mA I CCRF * 1 fin RF = 2500 MHz V CCRF = 3.0 V 5.7 6.5 8.4 mA...

Page 8 - FUNCTIONAL DESCRIPTION; Pulse swallow function; : Output frequency of external voltage controlled oscillator (VCO); Serial Data Input; • Programmable Reference Counter; : Charge pump current select bit; Data Flow

MB15F74UV 8 ■ ■ ■ ■ FUNCTIONAL DESCRIPTION 1. Pulse swallow function f VCO = [ (P × N) + A] × f OSC ÷ R f VCO : Output frequency of external voltage controlled oscillator (VCO) P : Preset divide ratio of dual modulus prescaler (32 or 64 for IF-PLL, 64or 128 for RF-PLL) N : Preset divide ratio of bin...

Page 9 - Divide ratio

MB15F74UV 9 (2) Data setting • Binary 14 - bit Programmable Reference Counter Data Setting Note : Divide ratio less than 3 is prohibited. • Binary 11 - bit Programmable Counter Data Setting Note : Divide ratio less than 3 is prohibited • Binary 7 - bit Swallow Counter Data Setting Divide ratio R14 R...

Page 10 - VCO Output

MB15F74UV 10 • Prescaler Data Setting • Charge Pump Current Setting • LD / fout output Selectable Bit Setting • Phase Comparator Phase Switching Data Setting Z : High-impedance Depending upon the VCO and LPF polarity, FC bit should be set. Divide ratio SW ==== “1” SW ==== “0” Prescaler divide ratio ...

Page 11 - Power Saving Mode (Intermittent Mode Control Circuit); Status; Normal mode; P S; s after the power supply becomes stable (V; “H”) at least 100 ns later after setting serial data.

MB15F74UV 11 3. Power Saving Mode (Intermittent Mode Control Circuit) The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. Seethe Electrical Characteristics chart for the sp...

Page 12 - Serial Data Data Input Timing; Clock

MB15F74UV 12 4. Serial Data Data Input Timing Divide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin.Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise ofthe LE signal. The following diagram sho...

Page 13 - PHASE COMPARATOR OUTPUT WAVEFORM; LD output; f r

MB15F74UV 13 ■ ■ ■ ■ PHASE COMPARATOR OUTPUT WAVEFORM • LD Output Logic Notes : • Phase error detection range = − 2 π to + 2 π • Pulses on Do IF/RF signals during locking state are output to prevent dead zone. • LD output becomes low when phase error is t WU or more. • LD output becomes high when ph...

Page 14 - TEST CIRCUIT (for Measuring Input Sensitivity fin/OSC; Oscilloscope

MB15F74UV 14 ■ ■ ■ ■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSC IN ) LD/ fout Do IF V CCIF 1000 pF 0.1 µ F 0.1 µ F PS IF GND IF fin IF Xfin IF GND OSC IN Do RF V CCRF PS RF GND RF Xfin RF fin RF LE Data Clock S.G. S.G. S.G. 1000 pF 50 Ω 1000 pF 50 Ω 1000 pF 50 Ω 10 9 8 7 6 5 4 3 2 1 11 12...

Page 15 - TYPICAL CHARACTERISTICS; fin input sensitivity; Catalog guaranteed range; RF-PLL input sensitivity vs. Input frequency

MB15F74UV 15 ■ ■ ■ ■ TYPICAL CHARACTERISTICS 1. fin input sensitivity 10 1500 2000 2500 3000 3500 4000 4500 5000 V CC = 2.7 V V CC = 3.0 V V CC = 3.6 V SPEC 0 − 10 − 20 − 30 − 40 − 50 Pfin RF [dBm] fin RF [MHz] Ta = +25 C Catalog guaranteed range 10 0 500 1000 1500 2000 2500 3000 V CC = 2.7 V V CC =...

Page 16 - input sensitivity; Input sensitivity vs. Input frequency; frequency f; Input sensitivity V

MB15F74UV 16 2. OSC IN input sensitivity 10 0 20 40 80 100 140 160 V CC = 2.7 V V CC = 3.0 V V CC = 3.6 V SPEC 0 − 10 − 20 − 30 − 40 − 50 60 120 Catalog guaranteed range Input sensitivity vs. Input frequency Input frequency f OSC (MHz) Input sensitivity V OSC (dBm)

Page 17 - Charge pump output current I; Charge pump output voltage V; Charge pump output voltage V

MB15F74UV 17 3. RF/IF-PLL Do output current • 1.5 mA mode • 6.0 mA mode 2.50 0.50 − 2.50 1.0 3.0 0.0 2.0 0.5 2.5 1.5 2.00 − 1.00 1.50 − 1.50 1.00 − 2.00 0.00 − 0.50 V CC = 2.7 V, Ta = +25 C Charge pump output current I DO (mA) I DO − V DO Charge pump output voltage V DO (V) I DO − V DO Charge pump o...

Page 18 - fin input impedance; input impedance

MB15F74UV 18 4. fin input impedance 494.28 Ω − 874.84 Ω 200 MHz 58.094 Ω − 216.47 Ω 1 GHz 39.773 Ω − 148 Ω 1.5 GHz 1 : 2 : 3 : START 100.000 000 MHz STOP 2 000.000 000 MHz − 102.92 Ω 2 000.000 000 MHz 4 : 30.266 Ω 1 2 3 4 773.21 fF 37.563 Ω − 109.96 Ω 2 GHz 26.125 Ω − 71.227 Ω 3 GHz 22.848 Ω − 54.02...

Page 20 - REFERENCE INFORMATION; for Lock; • PLL Reference Leakage

MB15F74UV 20 ■ ■ ■ ■ REFERENCE INFORMATION ( for Lock - up Time , Phase Noise and Reference Leakage ) (Continued) Test Circuit S.G. OSC IN fin Do LPF VCO Spectrum Analyzer 7.5 k Ω 1.6 k Ω 0.1 F 0.01 F 3300 pF V CC = 3.0 V Ta = + 25 ° C CP : 6 mA mode f VCO = 2113.6 MHz K V = 50 MHz/V fr = 50 kHz f O...

Page 22 - APPLICATION EXAMPLE; OUTPUT; Controller

MB15F74UV 22 ■ ■ ■ ■ APPLICATION EXAMPLE LD/ fout Do IF V CCIF 1000 pF 0.1 µ F 0.1 µ F PS IF GND IF fin IF Xfin IF GND OSC IN Do RF V CCRF PS RF GND RF Xfin RF fin RF LE Data Clock 1000 pF 1000 pF 1000 pF 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 MB15F74UV 1000 pF V CCRF Lock Detect OUTPUT VCO LP...

Page 23 - USAGE PRECAUTIONS; ORDERING INFORMATION; Part number

MB15F74UV 23 ■ ■ ■ ■ USAGE PRECAUTIONS (1) V CCRF and V CCIF must be equal voltage. Even if either RF-PLL or IF-PLL is not used, power must be supplied to V CCRF and V CCIF to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. (2) To protect against damag...

Page 24 - PACKAGE DIMENSION

MB15F74UV 24 ■ ■ ■ ■ PACKAGE DIMENSION 18-pin plastic BCC (LCC-18P-M05) Dimensions in mm (inches) Note : The values in parentheses are reference values. C 2003 FUJITSU LIMITED C18058S-c-1-1 0.05(.002) 1 2.70 ± 0.10 2.40 ± 0.10 (.094 ± .004) 0.45 ± 0.05 0.075 ± 0.025 (.003 ± .001) (.018 ± .002) (Stan...

Page 25 - FUJITSU LIMITED; FUJITSU LIMITED Printed in Japan

MB15F74UV FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU salesrepresentatives before ordering.The information, such as descriptions of function and applicationcircuit examples, in this document ar...

Fujitsu MB15F74UV - Manual

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