Fujitsu FR20 - Manual

v How to Read This Document. ■ Format of This Book The explanation concerning the main term used in this book is shown as follows. Term Meaning I-bus It is a bus of the width of 16 bits for an internal instruction. Because the FR20 series hasadopted internal Harvard Architecture, the instruction and...

vii CONTENTS CHAPTER 1 Overview of MB91191/MB91192 Series ..................................................... 1 1.1 Feature of MB91191/MB91192 Series ............................................................................................... 2 1.2 Block Diagram of All MB91191/MB91192 Series .....

viii 3.12.12 Clock Series of Peripheral Resource ........................................................................................... 81 3.12.13 Watchdog Function ...................................................................................................................... 82 CHAPTER ...

ix 8.5 Operation of PPG ........................................................................................................................... 175 CHAPTER 9 Real Timing Generator (RTG) ................................................................ 177 9.1 Overview of Real Timing Generator (RT...

5 1.3 Package Dimension MB91191/MB91192 series is available in one type of packages. ■ Package Dimension (LQFP-120) Figure 1.3-1 Package Dimension of FTP-120-M05 120-pin plastic LQFP Lead pitch 0.40 mm Package width × package length 14.0 × 14.0 mm Lead shape Gullwing Sealing method Plastic mold Moun...

7 1.4 Pin Assignment Figure 1.4-1 and Figure 1.4-2 show the pin assignment of the MB91191/MB91192 series. ■ Pin Assignment (LQFP-120) Figure 1.4-1 Pin assignment of LQFP-120 8bit MPX mode 16bi t M PX mode Top View P A1/ AN- 9/K EY1 P A2/ AN- A/K EY2 P A3/ AN- B/K EY3 P A4/ AN- C/K EY4 P A5/ AN- D/K ...

9 1.5 Pin Function Description Table 1.5-1 lists the pin function of MB91191/MB91192 series.The numbers shown in the tables has nothing to do with package pin numbers. For pin numbers, see "1.4 Pin Assignment". ■ Pin Function List Table 1.5-1 Pin Function List Pin No. (LQFP) Pin name Form Fu...

18 CHAPTER 2 Handling Devices 2.1 Precautions When Handling Devices The semiconductor device breaks down at a certain probability. Moreover, the failure of the semiconductor device is greatly controlled by the condition (circuit condition and environmental condition, etc.) used.To have the high use,...

19 ● Latch up The semiconductor device is composed by the formation of the region of the P-type and the N-type on the substrate. Internal parasitism PN junction (thyristor structure) might keep doing on-line when the voltage of an external abnormal voltage is added, and the heavy-current which excee...

21 ■ Precautions The reliability of the semiconductor is affected by the peripheral temperature as mentioned before, and other environmental conditions. Please note the following points. ● Humidity As for environment long-term use under the high humidity environment, something wrong with the leak ch...

22 CHAPTER 2 Handling Devices 2.2 Others The others are explained ■ External Reset Input When "L" level is input to the RST pin, to ensure the inside achieves reset status, "L" level input to theRST pin is required for at least five machine cycles. ■ Note on Using External Clock When...

24 CHAPTER 3 CPU 3.1 Memory Space The logical address space of the FR20 series is 4 Gbytes (2 32 addresses), and the CPU performs linear access. ■ Direct Addressing Area The under-mentioned area of the address space is used for I/O. This area is called the "direct addressing area" and operan...

26 CHAPTER 3 CPU 3.2 CPU Architecture The FR20 CPU is a high performance core that adopts highly functional commands for the embedded application as well as RISC architecture. ■ Feature of CPU Architecture ● Adoption of RISC architecture • Basic instruction: one instruction one cycle ● 32 bit archit...

27 Figure 3.2-1 shows the construction of internal architecture. Figure 3.2-1 Construction of Internal architecture ● CPU The FR20's 32-bit RISC architecture is compactly implemented on the CPU. A five-level command pipeline method is adopted to execute one command per cycle. The pipeline is compose...

29 3.3 Dedicated Registers Use the dedicated registers for specified purposes. Program counter (PC), program status (PS), table base register (TBR), return pointer (RP), system stack pointer (SSP), user stack pointer (USP), and multiplication/division results registers (MDH/MDL) are prepared. ■ Dedi...

34 CHAPTER 3 CPU [bit0] C: carrying flag This bit indicates whether or not carry or borrow was generated from the highest bit through the operation. Initial state by reset is irregular. ● System Condition code Register (SCR) Figure 3.3-10 shows the configuration of the system condition code register...

36 CHAPTER 3 CPU 3.4 General-purpose Register Register R0 to R15 is a general-purpose register. These registers are used as the pointer for memory access and accumulator for various operations. ■ General-purpose Register Figure 3.4-1 shows the configuration of the general-purpose register. Figure 3....

37 3.5 Data Construction The data allocation of the FR20 series uses as follow. • Bit ordering: Little endian • Byte ordering: Big endian ■ Bit Ordering In the FR20 series, the little endian has been adopted as a bit ordering. Figure 3.5-1 shows the data allocation of the bit ordering. Figure 3.5-1 ...

38 CHAPTER 3 CPU 3.6 Word Alignment As commands and data are accessed per byte, addresses to be allocated differ depending on the command length and data width. ■ Program Access It is necessary to arrange the program of the FR20 series in the address of the multiple of two. Bit 0 of the program coun...

39 3.7 Memory Map The memory map for the FR20 series is shown. ■ Memory Map The address space of the memory is 32 bit linear. Figure 3.7-1 shows the memory map. Figure 3.7-1 Memory map ● Direct addressing The under-mentioned region of the address space is a region for I/O. In this area, the operand ...

40 CHAPTER 3 CPU 3.8 Overview of Instructions The FR20 series supports logical operation and bit operations that are optimized for embedded application, and direct addressing commands as well as a general RISC command system. The set list shows the appendix. As each command is 16 bits length (some c...

42 CHAPTER 3 CPU 3.8.1 Branch Command with Delay Slot The operation with the delay slot branches prior to execute the command at the branch destination after executing the command located immediately after the branch command. ■ Branch Command with Delay Slot The following commands execute the branch...

43 ● The RP to be referred by the RET:D command will not be effected even if the command within the delay slot updates the RP. [example] RET:D ; Branch to address defined beforehand in RP MOV R8, RP ; No effect on the return operation ... ● The flag referred by the Bcc: Drel command is not effected ...

44 CHAPTER 3 CPU 3.8.2 Branch Command without Delay Slot Branch Command without Delay Slot is described. ■ Branch Command without Delay Slot The following commands execute the branch command without delay slot. JMP @Ri CALL label12 CALL @Ri RET BRA label9 BNO label9 BEQ label9 BNE label9 BC label9 B...

46 CHAPTER 3 CPU 3.9.1 Interrupt Level of EIT Interrupt levels is controlled by 0 to 31 by five bits. ■ Interrupt level of EIT The allocation of each level is as follow. It is a level of 16 to 31 that the operation is possible. Undefined command exception, coprocessor absence trap, coprocessor error...

47 3.9.2 Interrupt Stack Operation The value of PC and PS is saved and revived in the area shown by SSP. After an interrupt, PC is stored in the address indicated by the SSP, and PS is stored in the address (SSP+4). ■ Interrupt Stack Figure 3.9-1 shows the example of the interrupt stack. Figure 3.9-...

48 CHAPTER 3 CPU 3.9.3 EIT Vector Table From address which TBR shows to vector region for EIT region of 1KB ■ EIT Vector Table Each vector is 4 bytes, and the relationship between the vector number and vector address is expressed below. vctadr = TBR + vctofs = TBR +(03FCH - 4 × vct) vctadr: Vector A...

49 3.9.4 Multiple EIT Processing When a number of EIT factors are generated simultaneously, one of the EIT factors is selected and accepted in the CPU, and after the EIT sequence is executed, such EIT factors are detected again. This operation is repeated as necessary.When EIT factors are detected, ...

50 CHAPTER 3 CPU Figure 3.9-2 shows the example of multiple EIT processing. Figure 3.9-2 Example of multiple EIT processing Table 3.9-4 Execution sequence of EIT handler Execution sequence of handler Factor 1 Reset *1 2 Undefined instruction exception 3 Step trace trap *2 4 INTE instruction *2 5 NMI...

51 3.9.5 Operation of EIT This section explains operation of EIT ■ Operation of EIT As per the following explanation, the "PC" at the transfer origin indicates the address of the command that detected each EIT factor. The "following command address" means that the command that detect...

52 CHAPTER 3 CPU [Operation] 1. SSP-4 → SSP 2. PS → (SSP) 3. SSP-4 → SSP 4. Address of the following instruction → (SSP) 5. Interrupt level of accepted request → ILM 6. "0" → S Flag 7. (TBR + Vector offset of accepted interrupt request) → PC Prior to execute the front command of the handler ...

53 ■ Operation of Step Trace Trap When the T flag of the SCR within the PS is set, and the step trace function is set to Enabled, a trap is generated per command execution and creates a break. ● Condition of step trace trap detection • T Flag = 1 • There is no delayed branch instruction. • While exe...

54 CHAPTER 3 CPU ■ Coprocessor Absent Trap When a coprocessor command using an unmounted coprocessor is executed, a coprocessor absence trap is generated. [Operation] 1. SSP-4 → SSP 2. PS → (SSP) 3. SSP-4 → SSP 4. Address of the following instruction → (SSP) 5. "0" → S Flag 6. (TBR+3E0H) → P...

55 3.10 Reset Sequence This section explains the reset when the CPU is the operation state. ■ Reset Factor The reset factor is as follow. • Input from external reset pin • Software reset by the SRST bit operation of the standby control register (STCR) • Count up of watchdog timer • Power on reset ■ ...

56 CHAPTER 3 CPU 3.11 Memory Access Mode In the FR20 series, operation mode is controlled by the mode pins (MD2, 1, 0) and the mode register (MODR). ■ Operation Mode In the operation mode, there are a bus mode and an access mode. ● Bus Mode The bus mode controls the internal ROM operation and extern...

57 ■ Mode Data Data that the CPU writes at "0000 07FF H " after reset is called mode data. The mode register (MODR) exists in "0000 07FF H " and after setting to this register, operation is carried out under the set up mode of this register. The mode register can be written only once...

58 CHAPTER 3 CPU ■ Notes on Writing to Mode Register (MODR) Before writing to the MODR, AMD0 to AMD5 must be set, and the bus width in each chip select (CS) area must be decided. The MODR has no bits used to set the bus width. For the bus width, before writing to the MODR, the mode pins (MD2 to 0) a...

59 3.12 Clock Generation Section (Low Power Consumption Mechanism) The clock generation section is the modules that have the following functions: • CPU clock generation (including the gear function) • Peripheral clock generation (including the gear function) • Reset generation and cause retention • ...

60 CHAPTER 3 CPU ■ Block Diagram of Clock Generation Section Figure 3.12-2 Block Diagram of Clock Generation Section Statetransitioncontrolcircuit RSRR register WPR register CTBR register Watchdog F/F Timebase timer STCR regiter GCR register CPU gear Peripheralgear 1/ 2 PLL ResetgenerationF/F Osci-l...

62 CHAPTER 3 CPU Note: φ is twice as large as X0 when GCR CHC is 1, and is one time as large as X0 when GCR CHC is 0. Table 3.12-1 Watchdog timer cycle specified by WT1 and WT0 WT1 WT0 Writing spacing to at least necessary for control generation of watchdog reset WPR Timer from last 5A H write to WP...

64 CHAPTER 3 CPU 3.12.3 Timebase Timer Clear Register (CTBR) This register initializes the timebase timer contents to 0. ■ Timebase Timer Clear Register (CTBR) Figure 3.12-5 Timebase timer clear register (CTBR) [bit7 to 0] Writing A5 H , 5A H continuously to this register clears the timebase timer t...

67 3.12.5 Watchdog Reset Generation Delay Register (WPR) This register clears the flip-flop for the watchdog timer. Using this register postpones generation of the watchdog reset. ■ Watchdog Reset Generation Delay Register (WPR) Figure 3.12-7 Watchdog reset generation delay register (WPR) [bit7 to 0...

68 CHAPTER 3 CPU 3.12.6 Reset Factor Retention The reset factor retention holds the factor of previous generation. All flag is cleared to "0" by reading.Once a factor flag is set, it is not cleared unless the factor is read. ■ Block Diagram of Reset Factor Retention Circuit Figure 3.12-8 Res...

70 CHAPTER 3 CPU 3.12.7 Stop Status Stop status indicates the status that stops all internal clocks and oscillation circuit operation. It can be minimized the power consumption. ■ Overview of Stop Status Stop status indicates the status that stops all internal clocks and oscillation circuit operatio...

71 ■ Transition to Stop Status ● Transition to the stop state using an instruction Write "1" to bit 7 of the STCR register to enter stop status. After a stop request is issued, the status is changed such that the CPU does not use the internal bus, and then the clocks are stopped in the follo...

73 3.12.8 Sleep Status Sleep status indicates that the CPU clock and internal bus clock are stopped.Power consumption under the status where CPU operation is not required can be reduced in some extent. ■ Overview of Sleep Status Sleep status indicates that the CPU clock and internal bus clock are st...

74 CHAPTER 3 CPU ■ Transition to Sleep Status To enter sleep status, write "0" to bit 7 of the STCR register and "1" to bit 6. Issues the sleep request, and then stops clocks in the following order once the status of the CPU is changed so that the internal bus is not used. CPU clock ...

76 CHAPTER 3 CPU 3.12.9 State Transition in Standby Mode Figure 3.12-11 shows the state transition in standby mode. ■ State Transition in Standby Mode Figure 3.12-11 State transition in standby mode (1) Oscillation Stabilization Wait Time end (2) Reset cancellation (3) Reset input (4) STCR register ...

77 3.12.10 Gear Function The gear function supplies to thin out the clock. There are two types of independent circuits (for the CPU and for peripherals), and data can be transmitted and received between the CPU and peripherals even with different gear ratios. Furthermore, whether to use a clock with...

78 CHAPTER 3 CPU LDI:8 #00110000b,R1 ; CCK=00, PCK=00, CHC=0 STB R1,@R2 ; CPU clock=f, Peripheral clock=f, f=direct LDI:8 #10110000b,R1 ; CCK=10, PCK=00, CHC=0 STB R1,@R2 ; CPU clock=1/4f, Peripheral clock=f, f=direct Setting "1" to the CHC bit of the gear control register selects the 1/2 di...

80 CHAPTER 3 CPU 3.12.11 Clock Series Diagram Figure 3.12-14 shows the clock series diagram. ■ Clock Series Diagram Figure 3.12-14 Clock series diagram Clockgenerationunit φ θ XO CFG,DFG,FRG0-1 PC K EC 4 EC 5 PLL 1/2 CPU I/D C busconvert R busconvert ROM RAM Custom External bus control D RAM RAM Int...

81 3.12.12 Clock Series of Peripheral Resource Table 3.12-7 shows the table for the clock series list of peripheral resource. ■ Table for Clock Series List of Peripheral Resource Table 3.12-7 Table for clock series list of peripheral resource Peripheral resource Clock Division clock supply destinati...

82 CHAPTER 3 CPU 3.12.13 Watchdog Function The watchdog function detects any uncontrolled programs. If writing A5 H and 5A H to the watchdog reset postpone register is not performed within the predetermined period due to an uncontrolled program or suchlike, a watchdog reset request is generated by t...

83 ■ Reset Generation Delay Once the watchdog timer is initiated, A5 H and 5A H must be regularly written to the watchdog reset postpone register (WPR) by the program. The flip-flop for watchdog reset memorizes the falling edge of the tap selected by the timebase timer if this flip-flop is not clear...

86 CHAPTER 4 External Bus Interface 4.1 Overview of External Bus Interface The external bus interface controls the external memory and interface with the external I/O. ■ Feature of External Bus Interface • 16-bit (64KB) address output • Only 1 bank can be set by the chip select function - Capable of...

87 4.2 Block Diagram Figure 4.2-1 shows the block diagram of the external bus interface. ■ Block Diagram of External Bus Interface Figure 4.2-1 Block diagram of external bus interface +1or +2 writebuffer readbuffer ADDRESS BUS DATA BUS Internal pin control unit switch switch A-Out M U X External DAT...

88 CHAPTER 4 External Bus Interface 4.3 Area of Bus Interface A total of six types of chip select areas are prepared as bus interfaces. ■ Area of Bus Interface Each area position can be arbitrarily allocated in units of at least 64 KB in the 4 GB space by the area selectregisters (ASR1 to 5) and are...

89 4.4 Bus Interface The bus interface has an follow: • Normal bus interface • Time division I/O interface of address and data • DRAM control interface These interfaces can only be used in predetermined areas. ■ Bus Interface Table 4.4-1 shows the correspondence between each chip select area and the...

90 CHAPTER 4 External Bus Interface 4.5 Register of External bus Interface This section lists the register of external bus interface. ■ Register List of External Bus Interface Figure 4.5-1 Register list of external bus interface Note: Function pins for parts are not prepared under this product, so d...

93 Figure 4.5-4 Sample maps specified by chip select area Initial value Setting value in Example1 and 2 00000000 H 00000000 H Region 0 00010000 H Region 0 Region 1 64KB 00020000 H 00030000 H Region 2 64KB Region 1 64KB 00030000 H 00040000 H Region 3 64KB Region 0 00040000 H 0FFC0000 H Region 4 64KB ...

97 4.6 Bus Operation The basic item of the bus operation is explained as follow. • The relationship between the data bus width and control signal • Bus access of big endian • Bus access of little endian • Comparison of external access between big endian and little endian ■ Relationship between Data ...

98 CHAPTER 4 External Bus Interface 4.6.1 Relationship between Data Bus Width and Control Signal The control signal of WR0 to WR1 always supports the byte position of the data bus 1:1 regardless of big endian/little endian is used, or the data bus width. ■ The Relationship between the Data Bus Width...

99 4.6.2 Bus Access of Big Endian The data format in the FR20 series is normally big endian. Thus, external bus access is big endian for areas in which little endian (LER) is not set. ■ Data Format The relationship between the internal register and external data bus is indicated per data format. ● H...

100 CHAPTER 4 External Bus Interface ● 16-bit bus width Figure 4.6-4 Relationship between internal register and external data bus of 16-bit bus width ● 8-bit bus width Figure 4.6-5 Relationship between internal register and external data bus of 8-bit bus width ■ External Bus Access External bus acce...

103 ■ Connection Example with External Device Figure 4.6-8 Connection example with external device MB91191/MB91192 D31 D23 D24 D16 0 1 X D15 D08 D07 D00 D07 D00 16-bit device 8-bit device ("0"/"1" Address lower 1-bit) WR0 WR1

104 CHAPTER 4 External Bus Interface 4.6.3 Bus Access of Little Endian For areas in which little endian (LER) is set, external bus access is little endian.Bus access of the MB91191/MB91192 series is realized by swapping the byte position of the data bus in accordance with the bus width while the big...

105 ● Byte access (LDUB, STB instruction execution) Figure 4.6-10 Relationship between internal register and external data bus of byte access ■ Data Bus Width ● 32-bit bus width Figure 4.6-11 Relationship between internal register and external data bus of 32-bit bus width ● 16-bit bus width Figure 4...

108 CHAPTER 4 External Bus Interface 4.6.4 Comparison between Big Endian and Little Endian for External Access Comparison between big endian and little endian of external access for word access, half-word access, and byte access to the bus width is described. ■ Word Access Big endian mode Little end...

110 CHAPTER 4 External Bus Interface ■ Byte Access Big endian mode Little endian mode 16-bit bus width "0" D00 D31 D31 AA AA D16 D16 WR0 Control pin Internal Reg External pin address: "0" D00 D31 D31 AA AA D16 D16 WR0 Control pin Internal Reg External pin address: "1" D00 D31...

112 CHAPTER 4 External Bus Interface 4.7 Bus Timing The detailed bus access operation in each mode is shown. ■ Time Division I/O Interface In area 1, time division input/output interface for addresses/data is supported. The time division I/O isperformed the bus width specified by the BW1 and BW0. Fo...

113 4.8 Program Example of External Bus Operation A simple program example for operating the external bus is described. ■ Program Specification Example of External Bus Operation The setting of register is shown as follow. ● Area • Area 0 (AMD0) : 32-bit, usual bus, automatic wait 0 • Area 1 (AMD1) :...

117 CHAPTER 5 I/O Port This chapter describes an outline of the I/O port and the register configuration/functions. 5.1 Overview of I/O Port 5.2 Port 0 5.3 Port 1 5.4 Port 2, 3 5.5 Port 5 5.6 Port 6, 7 5.7 Port 4, 8, 9 5.8 Port A, B 5.9 Port C, D

118 CHAPTER 5 I/O Port 5.1 Overview of I/O Port The MB91191/MB91192 series have the 102 output ports. In terms of ports, there are ports 2, 3, 5, and 6 that are also used for external bus functions, and ports 0, 1, 4, and 7 to D that are also used for peripheral functions. Ports other than ports 0, ...

119 5.2 Port 0 Port 0 is the input/output port, and is also used for servo input, capture input, and PWC input. ■ Functions of I/O Port 0 Each port has two registers per bit, namely the data direction register (DDR) and port data register (PDR), and input/output can be set independently per bit. Pin...

120 CHAPTER 5 I/O Port ■ Registers for Port 0 ● Port 0 data register (PDR0) Figure 5.2-2 Port 0 data register (PDR0) ● Port 0 direction register (DDR0) Figure 5.2-3 Port 0 direction register (DDR0) 7 6 5 4 3 2 1 0 XXXX XXXX B Initial value bit Address: 000003 H Access PD07 PD06 PD05 PD04 PD03 PD02 P...

121 5.3 Port 1 Port 1 is an input/output port, and is also used for RTG output, timer clock/external interrupt input, and PWC input. ■ Functions of I/O Port 1 The port has three registers per bit, namely DDR, PDR, and PFS (port function select register), and the port input/output setup and function ...

122 CHAPTER 5 I/O Port ■ Registers for Port 1 ● Port 1 data register (PDR1) Figure 5.3-2 Port 1 data register (PDR1) ● Port 1 direction register (DDR1) Figure 5.3-3 Port 1 direction register (DDR1) ● Port 1 function selection register (PFS1) Figure 5.3-4 Port 1 function selection register (PFS1) Tab...

123 5.4 Port 2, 3 Ports 2 and 3 function as input/output ports under single-chip mode, and function as the address/data bus under external bus mode. ■ Functions of I/O Port 2, 3 Each port has two registers per bit, namely DDR and PDR, and input/output can be set independently per bit. Pins whose DDR...

124 CHAPTER 5 I/O Port ■ Registers for Port 2, 3 ● Port 2, 3 data register (PDR2, 3) Figure 5.4-2 Port 2 data register (PDR2) Figure 5.4-3 Port 3 data register (PDR3) ● Port 2, 3 direction register (DDR2, 3) Figure 5.4-4 Port 2 direction register (DDR2) Figure 5.4-5 Port 3 direction register (DDR3) ...

125 5.5 Port 5 Port 5 is the input/output port and is also used for the external bus function. ■ Functions of Port 5 The port has three registers per bit, namely DDR, PDR, and PFS, and the port input/output setup and function selection can be executed independently per bit. The external bus function...

126 CHAPTER 5 I/O Port ■ Registers for Port 5 ● Port 5 data register (PDR5) Figure 5.5-2 Port 5 data register (PDR5) ● Port 5 direction register (DDR5) Figure 5.5-3 Port 5 direction register (DDR5) ● Port 5 function selection register (PFS5) Figure 5.5-4 Port 5 function selection register (PFS5) Not...

128 CHAPTER 5 I/O Port ■ Block Diagram of Port 6, 7 Figure 5.6-1 Block Diagram of Port 6, 7 Pin P63 to P60 PDR PFS DDR Data register read Pin P67 to P64 PDR PFS DDR Data register read Pin P70 PCK 1/ 2 frequency division X0 CSEL XOUTE PDR PFS DDR PFS Data register read Peripheral output bus control P...

129 ■ Registers for Port 6, 7 ● Port 6, 7 data register (PDR6, 7) Figure 5.6-2 Port 6 data register (PDR6) Figure 5.6-3 Port 7 data register (PDR7) ● Port 6, 7 direction register (DDR6, 7) Figure 5.6-4 Port 6 direction register (DDR6) Figure 5.6-5 Port 7 direction register (DDR7) ● Port 6, 7 functio...

130 CHAPTER 5 I/O Port Note: The * setting is only valid when the external bus mode is specified. The general-purpose portfunction is always selected for single-chip mode. Figure 5.6-7 Port 7 function selection register (PFS7) Table 5.6-2 Operation of function selection bits Function selection bits ...

133 Figure 5.7-9 Port 8 function selection register (PFS8) Figure 5.7-10 Port 9 function selection register (PFS9) Table 5.7-1 Operation of function selection bits Function selection bits Register setting value 0 1 [bit7]: General-purpose port Setting disabled [bit6]: PG18E General-purpose port PPG ...

134 CHAPTER 5 I/O Port Table 5.7-3 Operation of function selection bits Function selection bits Register setting value 0 1 [bit7]: [bit6]: [bit5]: [bit4]: PG03E General-purpose port PPG output 03 [bit3]: PG02E General-purpose port PPG output 02 [bit2]: PG01E General-purpose port PPG output 01 [bit1]...

135 5.8 Port A, B Ports A and B are the input/output ports, and analog input and key input (for port A only) are shared. ■ Functions of Port A, B The port has three registers per bit, namely, DDR, PDR, and PIE (port input enable register), and input/ output can be selected independently per bit. In ...

136 CHAPTER 5 I/O Port ■ Registers for Port A, B ● Port A, B data register (PDRA, B) Figure 5.8-2 Port A data register (PDRA) Figure 5.8-3 Port B data register (PDRB) ● Port A, B direction register (DDRA, B) Figure 5.8-4 Port A direction register (DDRA) Figure 5.8-5 Port B direction register (DDRB) ...

137 5.9 Port C, D Ports C and D are input/output ports, and are also used as the PWM output, serial I/O, and external interrupt. ■ Functions of Port C, D The port has three registers per bit, namely, DDR, PDR, and PFS and input/output, setup and function selection can be executed independently per b...

138 CHAPTER 5 I/O Port ■ Registers for Port C, D ● Port C, D data register (PDRC, D) Figure 5.9-2 Port C data register (PDRC) Figure 5.9-3 Port D data register (PDRD) ● Port C, D direction register (DDRC, D) Figure 5.9-4 Port C direction register (DDRC) Figure 5.9-5 Port D direction register (DDRD) ...

139 Figure 5.9-7 Port D function selection register (PFSD) Table 5.9-1 Operation of function selection bits Function selection bits Register setting value 0 1 [bit7]: PWM00E General-purpose port PWM00 output [bit6]: PWM01E General-purpose port PWM01 output [bit5]: PWM02E General-purpose port PWM02 o...

142 CHAPTER 6 FG Input 6.1 Overview of FG Input The Frequency Generate (FG) input section comprises of the capstan input, drum input, and reel input sections. Each input section performs division of the input FG signal, generation of signals to be input to the FRC capture section and masking of the ...

143 6.2 Capstan Input The capstan input section is comprised of a multiplying circuit, 8-bit programmable divider, and mask timer. This section explains the operation of each section and control register. ■ Block Diagram of Capstan Input Figure 6.2-1 Block Diagram of Capstan Input ■ Register List of...

145 ■ Capstan Input Control Register (CAPDVC) Figure 6.2-4 Capstan Input Control Register (CAPDVC) [bit7 to 0]:DIV7 to 0 Executes division control of the capstan input and edge detection control depending on the set value. ■ Capstan Mask Timer Control Register (CAPMTC) Figure 6.2-5 Capstan mask time...

146 CHAPTER 6 FG Input ■ Operation of Capstan Input ● Operation of Multiplying circuit The capstan FG (CFG) input is input to the 8-bit programmable divider via "Slew" or double circuit by setting the multiplication select (DUB) bit of the capstan control register (CAPC). The input CFG signa...

147 Figure 6.2-8 Operation timing diagram of Mask Timer ● Limitation on using When double mode is specified for the capstan input, do not set "00 H " to the capstan input control register. It may cause the malfunction. CFGfrequency division Output edgeMask periodDVCFG output CFGD bit M.T Loa...

148 CHAPTER 6 FG Input 6.3 Drum Input The drum input section comprises of the 4-bit programmable divider and mask timer. This section explains the operation of each section and control register. ■ Block Diagram of Drum Input Figure 6.3-1 Block diagram of Drum Input ■ Register List of Drum Input Figu...

151 ■ Drum Mask Timer Control Register (DRMMTC) Figure 6.3-5 Drum mask timer control register (DRMMTC) [bit7 to 0]:D7 to 0 The masking period control of the drum input is performed by the set value. When Φ is specified as the clock cycle time selected by the mask timer clock select (CS) bit of the d...

152 CHAPTER 6 FG Input 6.4 Reel Input The reel input section comprises of the 8-bit programmable divider and mask timer. This section explains the register which controls the operation of each section. ■ Block Diagram of Reel Input Figure 6.4-1 Block Diagram of Reel Input ■ Register List of Reel Inp...

155 ■ Reel Mask Timer Control Register (RLxMTC) Figure 6.4-5 Reel mask timer control register (RLxMTC) [bit7 to 0]:D7 to 0 The masking period control of the reel input is performed by the set value. When Φ MT is specified as the clock cycle time selected by the mask timer clock select (CS) bit of th...

158 CHAPTER 7 FRC Capture 7.1 Overview of FRC Capture The FRC capture section has built-in 24-bit free-run counter and uses FIFO format. ■ Feature of FRC Capture • Built-in 24-bit free-run counter (Minimum resolution 50 ns:@20 MHz) • Built-in FIFO (Data 21-bit x 8, factor 8-bit x 8) ■ Register List ...

159 ■ Block Diagram of FRC Capture Figure 7.1-2 Block diagram of FRC capture CIC1 EIV0 EIV1 EIV2 FCIE FCLR FCIF Internal bus DVRFG1 DVRFG0 DVCFG DVDFG EXI2 EXI1 EXI0 Internal bus SOFT I0E I1EE EI2E DFGE CFGE F0ER RF1E FUL EMP CLR INC Fch (50ns FRC2-19 24bit FRC DVDFG FIFO-IN CAPS CAPD2 CAPD1 CAPD0 I...

160 CHAPTER 7 FRC Capture 7.2 Register of FRC Capture This section shows the register configuration/functions of the FRC capture. ■ Capture Input Control Register (CIC1, CIC0) ● Capture input control register (CIC1) Figure 7.2-1 Capture input control register (CIC1) [bit7]:FCIF It is capture request...

165 7.3 Operation of FRC Capture Up to eight capture data can be fetched in FIFO. If a new capture request is generated while data is full, the former data will be updated with the new data.If a capture request is generated while the FIFO storage is empty, overhead for a maximum of "fch x 18 cyc...

172 CHAPTER 8 Programmable Pulse Generator (PPG0, 1) ■ Timing Data Register (PPGxT) Figure 8.2-2 Timing data register (PPGxTH) Figure 8.2-3 Timing data register (PPGxTL) When the timing data register is updated continuously, write new data after 18/fch or more has passed after writing. Do not use th...

173 8.3 PPG Data RAM This section shows the relationship between the PPG data RAM and frame. ■ Relationship between PPG Data RAM and Frame Figure 8.3-1 Relationship between PPG data RAM and frame RAM Address PPGxSA 200 H /380 H 000 H 202 H /382 H 002 H PPG0 n+0 H Output timing dataOutput puttern dat...

174 CHAPTER 8 Programmable Pulse Generator (PPG0, 1) 8.4 Configuration of Frame Data Each frame is made up of 2-byte length output timing data (OTD) that specifies the output time and n x 2-byte length output pattern data (OPDx) that specifies the output value.In terms of the PPG0 frame configuratio...

175 8.5 Operation of PPG The operation of PPG has output and start operation. ■ Output Operation of PPG Clears the relative counter when the values set to the timing data register (PPGxTH, PPGxTL) and the FRC value match, and after loading the value of the address set register to the memory address ...

176 CHAPTER 8 Programmable Pulse Generator (PPG0, 1) Figure 8.5-3 Operation timing of PPG ■ Start Operation of PPG The PPG starts operation by setting "1" to the start bit. The initial operation is performed as follow. • Clears the relative counter and loads the initial address in synchroniz...

178 CHAPTER 9 Real Timing Generator (RTG) 9.1 Overview of Real Timing Generator (RTG) The real timing generator (RTG) has 3 built-in circuits, namely real timing generators 0 to 2 (RTG0 to 2). ■ Feature of Real Timing Generator (RTG) • Contain 3 RTG circuit • Output timing accuracy selectable 400 ns...

180 CHAPTER 9 Real Timing Generator (RTG) ■ Register List of Real Timing Generator (RTG) Figure 9.1-3 Register list of Real Timing Generator (RTG) 7 0 bit Address: 000034 H 000035 H 000036 H 000037 H RTG0C RTG0D RTG0TH RTG0TL RTG0 Control register RTG0 Output data register RTG0 Timing data register ...

183 9.3 Operation of Real Timing Generator (RTG) Initiation procedure of the real timing generator (RTG) and RTG output timing are described. ■ Initiation Procedure of Real Timing Generator (RTG) 1. Performs the initialization of control register. 2. Set the output data to RTGxD. In this case, do no...

185 CHAPTER 10 Timer This chapter describes an outline of the timer section, the register configuration/functions, and timer section operation. 10.1 Overview of Timer 10.2 Overview of 16-bit Timer (Timer 0 to 4) 10.3 Register of 16-bit Timer (Timer 0 to 4) 10.4 Operation of 16-bit Timer (Timer 0 to ...

186 CHAPTER 10 Timer 10.1 Overview of Timer The timer section comprises of a 16-bit timer and 8-/16-bit timer/counter. ■ Feature of Timer • 16-bit x 4ch • 16-bit timer/counter x 1ch (with square wave output) • 8-/16-bit timer/counter x 1ch (with square wave output) ■ Configuration of Timer Figure 10...

187 ■ Register List of Timer Figure 10.1-2 Register list of Timer bit 15 87 0 T0CD T0DR T0CR T1CR T1CD T1DR T2CD T2DR T2CR T3CR T3CD T3DR T4CD T4DR T4CR Timer 0 (16 bit Timer) Timer 1 (16 bit Timer) Timer 2 (16 bit Timer) Timer 3 (16 bit Timer) Timer 4 (16 bit Timer) Timer 5 (16 bit Timer) T5CR1 T5D...

194 CHAPTER 10 Timer ■ External Clock Mode (Only Timer 4) The external clock input is selected as the external clock mode by the clock source selection bit (TC1, TC0) of the timer control register (T4CR). In order to start up the timer, writing "1" to the T4CR timer start bit (TSTR) clears t...

201 10.7 Operation of 8-/16-bit Timer/Counter In terms of 8-/16-bit timer/counter operations, there are controls for the 8-bit internal clock mode, 8-bit external clock mode (event counter), and 16-bit mode. ■ Operation in 8-bit Internal Clock Mode In terms of the 8-bit internal clock mode, the inte...

202 CHAPTER 10 Timer Figure 10.7-2 Operation of external Clock Mode ■ Control in 16-bit Mode The 16-bit mode can be used as the 16-bit timer/counter in the same way as the 8-bit mode by setting each bit of the timer control register (TxCR1, TxCR1) as Figure 10.7-3 . Figure 10.7-3 Control in 16-bit m...

204 CHAPTER 11 12-bit PWM 11.1 Overview of 12-bit PWM The 12-bit PWM has a 12-bit resolution using the duty control and added pulse based on the selectable basic frequency. ■ Feature of 12-bit PWM • 12-bit resolution (rate, multi-type) • The conversion cycle can be selected: 0.2 ms/basic frequency 7...

205 ■ Register list of 12-bit PWM Figure 11.1-2 Register list of 12-bit PWM bit 15 87 0 PWM0 Control Register PWM00 Data Register PWM01 Data Register PWM02 Data Register PWM1 Control Register PWM10 Data Register PWM11 Data Register PWM12 Data Register Address: 000040 H 000042 H 000044 H 000046 H 000...

206 CHAPTER 11 12-bit PWM 11.2 Register of 12-bit PWM Register configuration/functions of 12-bit PWM is shown. ■ PWMx Control Register (PWMxC) Figure 11.2-1 PWMx Control Register (PWMxC) [bit7]:Test [bit6 to 4]: It is an unused bit. [bit3]:STR It is PWM operation enable bit. [bit2]:CKS It is clock s...

208 CHAPTER 11 12-bit PWM 11.3 Operation of 12-bit PWM The 12-bit PWM acquires a 12-bit resolution by inserting added pulse to the output waveform using the 8-bit and 4-bit counters. ■ Operation of 12-bit PWM The 12-bit PWM is operated by the 8-bit and 4-bit counters. The 8-bit counter will be the b...

209 ■ Update procedure of PWM data 1. Waits for load completion when the load request flag (LFLG) is set. 2. Sets the set value to each data register and writes "1" to the load request bit (LREQ). → The load request flag (LFLG) is set. Do not update the data when LFLG is 1. It may cause the ...

211 CHAPTER 12 8-bit Pulse Width Counter This chapter describes an outline of the 8-bit pulse width counter, the register configuration/functions, and 8-bit pulse width counter operations. 12.1 Overview of 8-bit Pulse Width Counter 12.2 Register of 8-bit Pulse Width Counter 12.3 Operation of 8-bit P...

212 CHAPTER 12 8-bit Pulse Width Counter 12.1 Overview of 8-bit Pulse Width Counter The 8-bit pulse width counter measures the pulse width by 400 ns accuracy. ■ Feature of 8-bit Pulse Width Counter • Pulse width measurement accuracy 400 ns (in fch = @20 MHz) • Mask input function ■ Block Diagram of ...

213 12.2 Register of 8-bit Pulse Width Counter The register configuration/functions of the 8-bit pulse width counter are mentioned. ■ PWC Control Register (PWCC) Figure 12.2-1 PWC Control Register (PWCC) [bit7]:Test It is test bit. [bit6 to 4]: It is an unused bit. [bit3]:CAPE It is capture enable b...

215 12.3 Operation of 8-bit Pulse Width Counter The pulse width counting operation of the 8-bit pulse width counter is described. ■ Pulse Input Mask Function Pulse input (PMI) can be directly masked by the pulse mask input signal (PMSK). In order to control PMI input by PMSK input, set "1" t...

217 CHAPTER 13 External Interrupt External interrupt comprises of the key input interrupt and external interrupt sections. This chapter describes an outline of the external interrupt 1 (key input circuit) and external interrupt (INT0 to 2), and the register configuration/functions, and their operati...

218 CHAPTER 13 External Interrupt 13.1 Overview of External Interrupt External interrupt comprises of the key input interrupt and external interrupt sections, and a total of 11 factors can be received. ■ Feature of External Interrupt External interrupts comprise of the key input interrupt and extern...

219 13.2 External Interrupt 1 (Key Input Circuit) The external interrupt 1 (key input circuit) has 8 inputs. ■ Block Diagram of External Interrupt 1 (Key Input Circuit) Figure 13.2-1 Block Diagram of Key input circuit ■ Register List of External Interrupt 1 (Key Input Circuit) Figure 13.2-2 Register...

220 CHAPTER 13 External Interrupt ■ Key Input Control Register (KEYC) Figure 13.2-3 Key input control register (KEYC) [bit7 to 0]:KIE7 to 0 There are input enable bit of KEY7 to 0. ■ Key Input Status Register (KEYS) Figure 13.2-4 Key input status register (KEYS) [bit7 to 0]:KIS7 to 0 There are edge ...

221 13.3 External Interrupt (INT0 to 2) The external interrupt (INT0 to 2) has 3 inputs. ■ Feature of External Interrupt (INT0 to 2) • Each interrupt is independent vector. • Usable for returning from standby. ■ Block Diagram of External Interrupt (INT0 to 2) Figure 13.3-1 Block diagram of external ...

223 ■ Operation of External Interrupt (INT0 to 2) The external interrupt sets the interrupt request flag (IF2 to 0) when the falling edge of the input signal is detected. In this case, if the supported interrupt is enabled (INTxE=1), an interrupt request is generated to the interrupt controller, whe...

225 CHAPTER 14 Delayed Interrupt Module This chapter describes an outline of the delayed interrupt module, the register configuration/functions, and delayed interrupt module operations. 14.1 Overview of Delayed Interrupt Module 14.2 Delayed Interrupt Control Register (DICR) 14.3 Operation of Delayed...

226 CHAPTER 14 Delayed Interrupt Module 14.1 Overview of Delayed Interrupt Module The delay interrupt module is used to generate interrupts for switching tasks.Using this module enables interrupt requests to the CPU to be generated or cancelled by the software. ■ Block Diagram of Delayed Interrupt M...

227 14.2 Delayed Interrupt Control Register (DICR) The delay interrupt control register (DICR) controls delay interrupts. ■ Delayed Interrupt Control Register (DICR) Figure 14.2-1 Delayed interrupt control register (DICR) [bit7 to 1]: It is an unused bit. [bit0]:DLYI It is EINT input edge detection ...

228 CHAPTER 14 Delayed Interrupt Module 14.3 Operation of Delayed Interrupt Module Delay interrupts are used to generate interrupts for switching tasks. Using this function enables interrupt requests to the CPU to be generated or cancelled by the software. ■ Interrupt Number The delay interrupt is a...

229 CHAPTER 15 Interrupt Controller This chapter describes an outline of the interrupt controller, the register configuration/functions, and the interrupt controller operations. 15.1 Overview of Interrupt Controller 15.2 Interrupt Control Register (ICRxx) 15.3 Operation of Interrupt Controller

230 CHAPTER 15 Interrupt Controller 15.1 Overview of Interrupt Controller The interrupt controller comprises of the interrupt control register, interrupt priority decision circuit, interrupt level, and interrupt number generation sections, and controls interrupt reception and adjustment. ■ Block Dia...

231 ■ Register List of Interrupt Controller Figure 15.1-2 Register list of interrupt controller 7 0 bit ICR00 ICR01 ICR02 ICR03 ICR04 Interrupt Control Register 00 Interrupt Control Register 01 Interrupt Control Register 02 Interrupt Control Register 03 Interrupt Control Register 04 Address: 000400 ...

232 CHAPTER 15 Interrupt Controller 15.2 Interrupt Control Register (ICRxx) This is interrupt control register. One is set per interrupt input, and sets the interrupt level for the interrupt request to be supported. ■ Interrupt Control Register (ICRxx) Figure 15.2-1 Interrupt control register (ICRxx...

233 15.3 Operation of Interrupt Controller The interrupt request generated at the resource is controlled by the interrupt-enabled bit that has been set per resource. If an interrupt is enabled at each resource, the generated interrupt request generates an interrupt request signal to the interrupt co...

235 ■ Return by Standby Mode (Stop/Sleep) The function returned from the stop mode is realized in the interrupt controller by generating an interrupt request. Even if an interrupt request is generated from a peripheral, a return request is generated from the standby mode to the clock control section...

240 CHAPTER 16 10-bit A/D Converter ● ADCL Figure 16.2-2 A/D converter control register (ADCL) [bit7 to 6]:Test Please set "0". [bit5]:Test It is test bit. [bit4, 3]: There are unused bit. [bit2 to 0]:Hi2 to 0 There are analog input selection bits for hard conversion. ■ Soft Conversion Analo...

242 CHAPTER 16 10-bit A/D Converter ■ Soft Conversion FIFO Data Register (SCFD) Figure 16.2-5 Soft conversion FIFO data register (SCFD) It is conversion result register for soft start. Reading this register enables data to be fetched sequentially. [bit11, 10]: It is an unused bit. [bit15 to 12]:C3 t...

243 [bit5]:HCIE It is hard conversion interrupt enable bit. The interrupt request is generated when HCEF=1 is HCIE=1. [bit2]:HFCR It is hard conversion FIFO clear bit. The read value of this bit is always "0". [bit1]:HFUL It is hard conversion FIFO full bit. [bit0]:HEMP It is hard conversion...

245 16.3 Operation of 10-bit A/D Converter In terms of 10-bit A/D converter operations, A/D operation is possible using both software and hardware conversions. ■ A/D Operation by Soft Conversion In order to carry out A/D conversion using software conversion, first select the required channel from th...

246 CHAPTER 16 10-bit A/D Converter ■ A/D Operation by Hard Conversion A/D conversion using hardware conversion can be operated by the ADST0 (PPG0) or ADST1 (PPG1, RTG) factors, and operation starts when the ADST0 or ADST1 rising edge is detected. Both ADST0 and ADST1 can select eight analog input p...

247 16.4 State Transition of 10-bit A/D Converter Figure 16.4-1 shows the state transition of 10-bit A/D converter. ■ State Transition of 10-bit A/D Converter Figure 16.4-1 State transition of 10-bit A/D converter The operation state can be known by the SCS, HCS, and HCNS bit of the ADCH register. A...

250 CHAPTER 17 Serial I/O 17.1 Overview of Serial I/O The serial I/O can automatically transfer 8-bit serial data and can select external initiation, multiple shift clock, and transfer interval time. ■ Feature of Serial I/O • 8-bit serial data can be transferred using clock synchronization. • Automa...

251 ■ Register List of Serial I/O Figure 17.1-2 Register list of Serial I/O 7 0 000300 H Serial 0 Data Buffer RAM 00037F H SIO0 DATA RAM 128byte 0003C8 H S0CR Serial Control Register 0003C9 H S0MR Clock Mode Setting Register 0003CA H S0AO Address Offset Register Serial 0 0003CB H S0BR Transfer Byte ...

252 CHAPTER 17 Serial I/O 17.2 Register of Serial I/O The register configuration/functions of the serial I/O is shown. ■ Serial Control Register (SxCR) Figure 17.2-1 Serial control register (SxCR) [bit7]:SIF It is serial I/O transfer completion flag. [bit6]:ICLR It is transfer completion flag clear ...

254 CHAPTER 17 Serial I/O [bit3]:IC0 It is selection bit of interval. Setting the interval is as follows. *:Tclk= Shift clock cycle time [bit2]:SC2 [bit1]:SC1 [bit0]:SC0 It is selection bit of shift clock. φ : Defined by peripheral clock gear (PCK1 and 0) fch: Source oscillation frequency IC1 IC0 In...

255 ■ Address Offset Register (SxAO) Figure 17.2-3 Address offset register (SxAO) Sets the start address offset of the serial data RAM. ■ Transfer Byte Number Setting Register (SxBR) Figure 17.2-4 Transfer byte number setting register (SxBR) [bit7]:BMOD It is serial buffer mode control bit. [bit6 to...

256 CHAPTER 17 Serial I/O 17.3 Serial Data RAM The serial data RAM has 128 bytes per channel. In this section, explanations are given based on serial 0. ■ Serial Data RAM For serial 0 of this RAM, the byte number set by the transfer byte number setting register from the address "300 H " is u...

257 17.4 Operation of Serial I/O The serial I/O has two modes, namely, transmission mode and transmission/reception mode. ■ Operation of Serial I/O The serial I/O has two modes, namely, transmission mode and transmission/reception mode. In the case of transmission mode (DIR=1), contents transferred ...

258 CHAPTER 17 Serial I/O ■ Operation Mode of Serial I/O In terms of the serial I/O operation mode, there are two types, namely, internal shift clock mode and external shift clock mode depending on the shift clock type, and these are specified by the SCMR. Mode switching and clock selection should b...

259 ■ Interrupt Function The serial I/O is set by the transfer end flag (SIF) bit when data transfer ends. In this case, the interrupt request is generated. When termination (suspension) is executed by inputting chip select, the chip select termination flag (CSAF) bit is set and an interrupt request...

260 CHAPTER 17 Serial I/O Figure 17.4-8 Shift operation start/stop timing by chip select ● External shift clock mode Figure 17.4-9 Shift operation start/stop timing by external clock #0 #1 #2 #3 #4 #5 #6 #7 #0 #1 #2 #3 #4 ST SIF SO SCK CSAF SO SCK ST XCS SIF XCS CSAF At 1 byte Transmission end At 1 ...

261 CHAPTER 18 10-bit General-purpose Prescaler This chapter describes an outline of the 10-bit general-purpose prescaler, the register configuration/functions, and the 10-bit general-purpose prescaler operations. 18.1 Overview of 10-bit General-purpose Prescaler 18.2 Register of 10-bit General-purp...

262 CHAPTER 18 10-bit General-purpose Prescaler 18.1 Overview of 10-bit General-purpose Prescaler The 10-bit general-purpose prescaler has built-in dedicated oscillation circuit and a load function using the PPG output. ■ Feature of 10-bit General-purpose Prescaler • 10-bit prescaler x 1ch (with squ...

263 18.2 Register of 10-bit General-purpose Prescaler The register configuration/functions of 10-bit general-purpose prescaler is shown. ■ Prescaler Control Register (GPRC) Figure 18.2-1 Prescaler control register (GPRC) [bit7, 6]: There are unused bits. [bit5]:INV It is external clock input polarit...

265 18.3 Operation of 10-bit General-purpose Prescaler Division operation of the 10-bit general-purpose prescaler and updating operation of the reload data latch are described. ■ Division Operation and PO Output Figure 18.3-1 shows the operation of general-purpose prescaler. Figure 18.3-1 Operation ...

266 CHAPTER 18 10-bit General-purpose Prescaler Figure 18.3-3 Update timing of reload data latch ● Update mode operation by both edges of PPG output Under this mode, exactly the same operation as the update mode by rewriting the data register is carried out except for detecting both edges of the PPG...

267 CHAPTER 19 Bit Search Module This chapter describes an outline of the bit search module, the register configuration/functions, the bit search module operations, and save/return processes. 19.1 Overview of Bit Search Module 19.2 Register of Bit Search Module 19.3 Operation of Bit Search Module

268 CHAPTER 19 Bit Search Module 19.1 Overview of Bit Search Module The bit search module detects 0, 1, or point of change for data written to the input register, and returns the detected bit position. ■ Feature of Bit Search Module • Search for the bit position that first changes between 1 and 0 be...

269 19.2 Register of Bit Search Module The register configuration/functions of bit search module is shown. ■ 0 Detection Data Register (BSD0) Figure 19.2-1 0 detection data register (BSD0) • The module detects 0 for the value written to this register. • The initial value by reset is irregular. • The...

271 19.3 Operation of Bit Search Module 0 detection and 1 detection by the bit search module, and detection operation are described. ■ 0 Detection Scans data that was written to the data register for 0 detection from the MSB to LSB, and returns the position where the first "0" was detected. ...

272 CHAPTER 19 Bit Search Module ■ Change Point Detection Scans data that was written to the data register for detecting the point of change from bit 30 to LSB, and compares it with the MSB value. Returns the position where the value different from the MSB was first detected. The detection result ca...

273 ■ Save/Return Processes When the internal status of the bit search module needs to be saved/returned, for example using the bit search module during interrupt handling, follow the procedure below. 1. Read the 1 detection data register and store the read data (Save). 2. Use the bit search module....

275 CHAPTER 20 Wait Controller This chapter describes an outline of the wait control section, and the register configuration/functions. 20.1 Outline of Wait Control Section 20.2 Wait Control Register (WAITC)

276 CHAPTER 20 Wait Controller 20.1 Outline of Wait Control Section The wait control section sets the access speed (wait number) for built-in memory. ■ Internal Memory Area The internal memory area is as follows. • MB91191 series: address:0xC0000 to 0xfffff • MB91192 series: address:0x80000 to 0xfff...

279 CHAPTER 21 Flash Memory This chapter describes an outline of the flash memory, the register configuration/functions and the flash memory operations. 21.1 Overview of Flash Memory 21.2 Flash Memory Status Register (FSTR) 21.3 Operation of Flash Memory 21.4 Flash Memory Auto Algorithm (Embedded Al...

280 CHAPTER 21 Flash Memory 21.1 Overview of Flash Memory The MB91F191A and MB91F192 devices have built-in flash memory that can erase all sectors in a block and erase per sector using a single +3V power source, and write per half-word (16-bit) using a FR-CPU with 254-Kbyte *1 (2-Mbit) / 384-Kbyte (...

281 ■ Block Diagram of Flash Memory Figure 21.1-1 Block Diagram of Flash memory ■ Register List of Flash Memory Figure 21.1-2 Register list of Flash memory INTE Interrupt request Bus control signal RDYINT RDY WE FR-C Bus (Instruction/Data) Address buffer Data buffer Control signalgeneration Rasing e...

282 CHAPTER 21 Flash Memory ■ Memory Map and Sector Construction Address mapping of the flash memory differs when accessed from the FR-CPU and by the ROM writer *1 . This shows the mapping at accessing from the CPU. Figure 21.1-3 Memory map and sector construction (MB91F191A) Table 21.1-1 Sector add...

286 CHAPTER 21 Flash Memory 21.3 Operation of Flash Memory When accessed by the FR-CPU, the following two types of access mode exist. • ROM mode: Word (32-bit) length data can be read in blocks, but not written. • Programming mode: Word (32-bit) length access is disabled, but writing in half-word (1...

287 The number of cycles taken for reading is 2 cycles per half-word (1 wait). • Writing command to the flash memory enables the auto algorithm to be initiated. Initiating auto algorithm enables the flash memory to be erased or written. Refer to "21.4 Flash Memory Auto Algorithm (Embedded Algori...

288 CHAPTER 21 Flash Memory 21.4 Flash Memory Auto Algorithm (Embedded Algorithm TM ) Writing or erasing of the flash memory cell is carried out by initiating the auto algorithm stored by the flash memory itself. ■ Command Operation In order to initiate the auto algorithm, execute continuous writing...

292 CHAPTER 21 Flash Memory 21.5 Auto Algorithm Execute State This flash memory has hardware that notifies the internal flash memory operation status and operation completion for outside of the flash memory to execute the write/erase flow by auto algorithm. One is a hardware sequence flag, and the o...

293 *1: Bit 2 toggles when reading continuously from the erase suspension sector. *2: Bit 6 toggles even when reading continuously from any address. *3: During writing erasure suspension, bit 2 will be "1" when reading the address that is being written. However, bit 2 toggles when reading co...

297 Appendix Details that could not be described within the body text, such as I/O map, interrupt vector, peripheral circuit measurement speed, restrictions and commands list for use of the MB91191/MB91192 series are described in the appendix. Appendix A I/O Map Appendix B Interrupt vector Appendix ...

306 Appendix B Interrupt vector Appendix B Interrupt vector Table B-1 shows interrupt vector table. The interrupt factor of the MB91191/MB91192 series and allocation of the interrupt vector/interrupt control register are described in the interrupt vector table. ■ Interrupt Vector Table B-1 Interrupt...

308 Appendix C Measurement accuracy of peripheral circuit Appendix C Measurement accuracy of peripheral circuit Figure C-1 shows the measurement accuracy of peripheral circuit relative to FRC and the output timing accuracy. ■ Measurement Accuracy of Peripheral Circuit Relative to FRC and Output Timi...

310 Appendix E Instruction List Appendix E Instruction List Instruction list of FR series is shown. Beforehand, the following matters are explained for better understanding of the command list. • How to Read the Instruction List • Symbol of addressing mode • Instruction format ■ How to Read the Inst...

312 Appendix E Instruction List ■ Symbol of Addressing Mode Table E-1 Description of symbol of addressing mode Symbol Explanation Ri Register direct (R0 to R15, AC, FP, SP) Rj Register direct (R0 to R15, AC, FP, SP) R13 Register direct (R13, AC) Ps Register direct (direct program status register) Rs...

313 ■ Instruction Format Table E-2 Instruction format Type Instruction format A B C C’ D E F MSB LSB 16bit OP Rj Ri 8 4 4 OP i8/o8 Ri 4 8 4 OP u4/m4 Ri 8 4 4 7 5 4 OP s5/u5 Ri Only ADD, ADDN, CMP, LSL, LSR, ASR instructions OP u8/rel8/dir/reglist 8 8 OP SUB-OP Ri 8 4 4 OP rel11 5 11

314 Appendix E Instruction List E.1 Instruction list of FR series Instruction list of FR series is described in order to following instruction. ■ Instruction List of FR Series Table E-3 Addition and subtraction instruction Table E-4 Comparison operation instruction Table E-5 Logical operation instru...

315 ■ Addition and Subtraction Instruction ■ Comparison Operation Instruction ■ Logical Operation Instruction Table E-3 Addition and subtraction instruction Mnemonic Type OP CYCLE NZVC Operation Remark ADD Rj, Ri *ADD #s5, Ri ADD #u4, Ri ADD2 #u4, Ri A C' C C A6 A4 A4 A5 1 1 1 1 CCCC CCCC CCCC CCCC ...

316 Appendix E Instruction List ■ Bit Manipulation Instructions ■ Multiplication and Division Instructions Table E-6 Bit manipulation instructions Mnemonic Type OP CYCLE NZVC Operation Remark BANDL #u4, @Ri BANDH #u4, @Ri *BAND #u8, @Ri *1 C C 80 81 1+2a 1+2a ------------ (Ri) &=(0xF0+u4) (Ri) &...

317 ■ Shift Instruction ■ Value Move Operation of Value Sets/16 Bits/32 Bits Immediately Table E-8 Shift instruction Mnemonic Type OP CYCLE NZVC Operation Remark LSL Rj, Ri *LSL #u5, Ri(u5:0 to 31) LSL #u4, Ri LSL2 #u4, Ri A C' C C B6 B4 B4 B5 1 1 1 1 CC-C CC-C CC-C CC-C Ri < <Rj → Ri Ri < ...

318 Appendix E Instruction List ■ Memory Loading Instruction ■ Memory Store Instruction Table E-10 Memory loading instruction Mnemonic Type OP CYCLE NZVC Operation Remark LD @Rj,Ri LD @(R13,Rj),Ri LD @(R14,disp10),Ri LD @(R15,udisp6),Ri LD @R15+,Ri LD @R15+,Rs LD @R15+,PS A A B C E E E 04 00 20 03 0...

319 ■ Transfer Instruction between Registers ■ Normal Divergence (There is no delay) Instruction Table E-12 Transfer instruction between registers Mnemonic Type OP CYCLE NZVC Operation Remark MOV Rj,Ri MOV Rs,Ri MOV Ri,Rs MOV PS,Ri MOV Ri,PS A A A E E 8B B7 B3 17-1 07-1 1 1 1 1 c ---------------- CC...

320 Appendix E Instruction List Note: • "2/1" of CYCLE number is following;2: branching1: not branching • The assembler calculates and sets values as follows in the rel11 and rel8 fields for hardware specifications. (label12-PC-2)/2 → rel11, (label9-PC-2)/2 → rel8, label12, label9 are with s...

321 ■ The Other Instruction Table E-15 The other Instruction Mnemonic Type OP CYCLE NZVC Operation Remark NOP E 9F-A 1 ---- Anything does not change either. ANDCCR #u8 ORCCR #u8 D D 83 93 c c CCCC CCCC CCR and u8 → CCR CCR or u8 → CCR STILM #u8 D 87 1 ---- i8 → ILM Value set of ILM immediately ADDSP...

322 Appendix E Instruction List ■ 20-bit Normal Divergence Macro Instruction Table E-16 20-bit Normal divergence macro instruction Mnemonic Operation Remark *CALL20 label20,Ri Address of the following instruction-->RP, label20 → PC Ri: Temporary register (Refer to reference 1.) *BRA20 label20,Ri ...

323 ■ 20-bit Delayed Divergence Macro Instruction Table E-17 20-bit Delayed divergence macro instruction Mnemonic Operation Remark *CALL20:D label20,Ri Address of the following instruction +2 → RP, label20 → PC Ri: Temporary register (Refer to reference 1.) *BRA20:D label20,Ri *BEQ20:D label20,Ri *B...

324 Appendix E Instruction List ■ 32-bit Normal Divergence Macro Instruction Table E-18 32-bit Normal divergence macro instruction Mnemonic Operation Remark *CALL32 label32,Ri Address of the following instruction → RP, label32 → PC Ri: Temporary register (Refer to reference 1.) *BRA32 label32,Ri *BE...

325 ■ 32-bit Delayed Divergence Macro Instruction Table E-19 32-bit Delayed divergence macro instruction Mnemonic Operation Remark *CALL32:D label32,Ri Address of the following instruction+2 → RP, label32 → PC Ri: Temporary register (Refer to reference 1.) *BRA32:D label32,Ri *BEQ32:D label32,Ri *BN...

326 Appendix E Instruction List ■ Direct Addressing Instruction ■ Resource Instruction ■ Coprocessor Control Instruction Table E-20 Direct addressing instruction Mnemonic Type OP CYCLE NZVC Operation Remark DMOV @dir10, R13 DMOV R13, @dir10 DMOV @dir10, @R13+ DMOV @R13+, @dir10 * DMOV @dir10, @-R15 ...

327 INDEX Numerics 0 Detection ........................................................... 271 0 Detection Data Register (BSD0) ....................... 269 1 Detection ........................................................... 271 1 Detection Data Register (BSD1) ....................... 269 20-bit ...

CM71-10113-1E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL FR20 32 BIT MICRO CONTROLLER MB91191/MB91192 SERIES HARDWARE MANUAL March 2004 the first edition Published FUJITSU LIMITED Electronic Devices Edited Business Promotion Dept.