Siemens S6 PCN - Manuals

Semiconductor Group 1-1 Introduction C515 1 Introduction The C515 is a member of the Siemens C500 family of 8-bit microcontrollers. lt is functionally fullyupward compatible with the SAB-80C515/80C535 microcontrollers. The C515 basically operates with internal and/or external program memory. The C51...

Introduction C515 Semiconductor Group 1-4 1.1 Pin Configurations This section describes the pin configuration of the C515. Figure 1-3 Pin Configuration of P-LCC-68 Package (top view) P5.7P0.7 P0.5 P0.6 P0.1 P2.6 P2.4 ALEPSEN EA P0.0 P4.4 P4.5 PE/SWD P4.3 P5.2 P5.3 P5.5 P5.4 P5.0 P5.1 P4.0 1 68 9 10 ...

Semiconductor Group 1-7 Introduction C515 P3.0-P3.7 21-28 21 22 23 24 252627 28 15-22 15 16 17 18 192021 22 I/O Port 3 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that stat...

Introduction C515 Semiconductor Group 1-8 P1.0 - P1.7 36-29 36 35 34 33 3231 3029 31-24 31 30 29 28 2726 2524 I/O Port 1is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that sta...

Semiconductor Group 1-9 Introduction C515 XTAL2 39 36 – XTAL2Input to the inverting oscillator amplifier and input to the internal clock generator circuits.To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected. Minimum and maximum high and low tim...

Semiconductor Group 2-1 Fundamental Structure C515 2 Fundamental Structure The C515 is fully compatible to the architecture of the standard 8051/C501 microcontroller family.While maintaining all architectural and operational characteristics of the C501, the C515incorporates a 8-bit A/D converter, a ...

Fundamental Structure C515 Semiconductor Group 2-2 2.1 CPU The C515 is efficient both as a controller and as an arithmetic processor. It has extensive facilitiesfor binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of programmemory results from an instruction set c...

Fundamental Structure C515 Semiconductor Group 2-4 2.2 CPU Timing A machine cycle of the C515 consists of 6 states (12 oscillator periods). Each state is devided intoa phase 1 half and a phase 2 half. Thus, a machine cycle consists of 12 oscillator periods,numbererd S1P1 (state 1, phase 1) through S...

Semiconductor Group 3-1 Memory Organization C515 3 Memory Organization The C515 CPU manipulates operands in the following four address spaces: – up to 64 Kbyte of program memory (8K on-chip program memory for C515-1R)– up to 64 Kbyte of external data memory– 256 bytes of internal data memory– a 128 ...

Memory Organization C515 Semiconductor Group 3-2 3.1 Program Memory, "Code Space" The C515-1R has 8 Kbytes of read-only program memory which can be externally expanded up to64 Kbytes. If the EA pin is held high, the C515-1R executes program code out of the internal ROMunless the program coun...

Semiconductor Group 3-3 Memory Organization C515 3.5 Special Function Registers The registers, except the program counter and the four general purpose register banks, reside inthe special function register area. The 43 special function registers (SFRs) include pointers and registers that provide an ...

Memory Organization C515 Semiconductor Group 3-4 Table 3-1 Special Function Registers - Functional Blocks Block Symbol Name Address Contents afterReset CPU ACCBDPHDPLPSWSPSYSCONSYSCON 4) AccumulatorB-RegisterData Pointer, High ByteData Pointer, Low ByteProgram Status Word RegisterStack PointerSystem...

Memory Organization C515 Semiconductor Group 3-6 Table 3-2 Contents of the SFRs, SFRs in Numeric Order of their Addresses Addr Register Contentafter Reset 1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 2) P0 FFH .7 .6 .5 .4 .3 .2 .1 .0 81H SP 07H .7 .6 .5 .4 .3 .2 .1 .0 82H DPL 00H .7 .6 .5 ...

Semiconductor Group 4-1 External Bus Interface C515 4 External Bus Interface The C515 allows for external memory expansion. The functionality and implementation of theexternal bus interface is identical to the common interface for the 8051 architecture with oneexception : if the C515 is used in syst...

Semiconductor Group 4-3 External Bus Interface C515 4.1.2 Timing The timing of the external bus interface, in particular the relationship between the control signalsALE, PSEN, RD, WR and information on port 0 and port 2, is illustated in figure 4-1 a) and b). Data memory: in a write cycle, the data ...

Semiconductor Group 4-4 External Bus Interface C515 4.4 ALE, Address Latch Enable The C515 allows to switch off the ALE output signal. If the internal ROM is used (EA=1 andPC £ 1FFFH) and ALE is switched off by EALE=0, then, ALE will only go active during external data memory accesses (MOVX instruct...

Semiconductor Group 4-5 External Bus Interface C515 4.5 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovativeway to control the execution of C500 MCUs and to gain extensive information on the internaloperation of the controllers...

Semiconductor Group 4-6 External Bus Interface C515 4.6 ROM Protection for the C515 The C515-1R allows to protect the contents of the internal ROM against unauthorized read out. Thetype of ROM protection (protected or unprotected) is fixed with the ROM mask. Therefore, thecustomer of a C515-1R versi...

Semiconductor Group 4-7 External Bus Interface C515 4.6.2 Protected ROM Mode If the ROM is protected, the ROM verification mode 2 as shown in figure 4-4 is used to verify thecontents of the ROM. The detailed timing characteristics of the ROM verification mode is shown inthe AC specifications (chapte...

Semiconductor Group 5-3 Reset / System Clock C515 5.2 Hardware Reset Timing This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase2. Thus, the external reset signal is synchronized to the internal C...

Semiconductor Group 5-4 Reset / System Clock C515 5.3 Oscillator and Clock Circuit XTAL1 and XTAL2 are the output and input of a single-stage on-chip inverter which can beconfigured with off-chip components as a Pierce oscillator. The oscillator, in any case, drives theinternal clock generator. The ...

Semiconductor Group 5-5 Reset / System Clock C515 Figure 5-4 On-Chip Oscillator Circuitry To drive the C515 with an external clock source, the external clock signal has to be applied toXTAL2, as shown in figure 5-5. XTAL1 has to be left unconnected. A pullup resistor is suggested(to increase the noi...

Semiconductor Group 5-7 Reset / System Clock C515 Figure 5-6 Timing Diagram - System Clock Output MCT01858 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 ALE PSEN RD,WR CLKOUT

Semiconductor Group 6-1 On-Chip Peripheral Components C515 6 On-Chip Peripheral Components This chapter gives detailed information about all on-chip peripherals of the C515 except for theintegrated interrupt controller, which is described separately in chapter 7. 6.1 Parallel I/O The C515 has six 8-...

Semiconductor Group 6-2 On-Chip Peripheral Components C515 Table 6-1 Alternate Functions of Port 1 and 3 Port Alternate Functions Description P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7 P3.0 P3.1 P3.2P3.3P3.4P3.5P3.6P3.7 INT3 / CC0INT4 / CC1INT5 / CC2INT6 / CC3INT2T2EXCLKOUTT2 RxD TxD INT0INT1T0T1WRRD External...

Semiconductor Group 6-4 On-Chip Peripheral Components C515 The output drivers of port 1 to 5 have internal pullup FET’s (see figure 6-2). Each I/O line can beused independently as an input or output. To be used as an input, the port bit stored in the bit latchmust contain a one (1) (that means for f...

Semiconductor Group 6-5 On-Chip Peripheral Components C515 6.1.2.1 Port 0 Circuitry Port 0, in contrast to ports 1 to 4, is considered as "true" bidirectional, because the port 0 pins floatwhen configured as inputs. Thus, this port differs in not having internal pullups. The pullup FET inthe...

Semiconductor Group 6-6 On-Chip Peripheral Components C515 6.1.2.2 Port 1, Port 3 to Port 5 Circuitry The pins of ports 1, 3, 4, and 5 are multifunctional. They are port pins and also serve to implementspecial features as listed in table 6-1. Figure 6-4 shows a functional diagram of a port latch wit...

Semiconductor Group 6-7 On-Chip Peripheral Components C515 6.1.2.3 Port 2 Circuitry As shown in figure 6-3 and below in figure 6-5, the output drivers of ports 0 and 2 can be switchedto an internal address or address/data bus for use in external memory accesses. In this applicationthey cannot be use...

Semiconductor Group 6-8 On-Chip Peripheral Components C515 Figure 6-6 Port 2 Pull-up Arrangement Port 2 in I/O function works similar to the standard port driver circuitry (section 6.1.2.4) whereas inaddress output function it works similar to Port 0 circuitry. MCS03229 1 1 = 1 = 1 V CC PortPin SS V...

Semiconductor Group 6-9 On-Chip Peripheral Components C515 6.1.2.4 Detailed Output Driver Circuitry In fact, the pullups mentioned before and included in figure 6-2, 6-4 and 6-5 are pulluparrangements. Figure 6-7 shows the detailed output driver (pullup arrangement) circuit of the the port 1 and 3 t...

Semiconductor Group 6-10 On-Chip Peripheral Components C515 – The pullup FET p3 is of p-channel type. It is only activated if the voltage at the port pin is higher than approximately 1.0 to 1.5 V. This provides an additional pullup current if a logichigh level shall be output at the pin (and the vol...

Semiconductor Group 6-11 On-Chip Peripheral Components C515 6.1.3 Port Timing When executing an instruction that changes the value of a port latch, the new value arrives at thelatch during S6P2 of the final cycle of the instruction. However, port latches are only sampled bytheir output buffers durin...

Semiconductor Group 6-12 On-Chip Peripheral Components C515 6.1.4 Port Loading and Interfacing The output buffers of ports 1 to 5 can drive TTL inputs directly. The maximum port load which stillguarantees correct logic output levels can be be looked up in the DC characteristics in the DataSheet of t...

Semiconductor Group 6-13 On-Chip Peripheral Components C515 6.1.5 Read-Modify-Write Feature of Ports 0 to 5 Some port-reading instructions read the latch and others read the pin. The instructions reading thelatch rather than the pin read a value, possibly change it, and then rewrite it to the latch....

Semiconductor Group 6-14 On-Chip Peripheral Components C515 6.2 Timers/Counters The C515 contains three general purpose 16-bit timers/counters, timer 0, 1, and 2, which are usefulin many applications for timing and counting. In "timer" function, the timer register is incremented every machin...

Semiconductor Group 6-15 On-Chip Peripheral Components C515 6.2.1.1 Timer/Counter 0 and 1 Registers Totally six special function registers control the timer/counter 0 and 1 operation : – TL0/TH0 and TL1/TH1 - counter registers, low and high part– TCON and TMOD - control and mode select registers Spe...

Semiconductor Group 6-16 On-Chip Peripheral Components C515 Special Function Register TCON (Address 88H) Reset Value : 00H Bit Function TR0 Timer 0 run control bitSet/cleared by software to turn timer/counter 0 ON/OFF. TF0 Timer 0 overflow flagSet by hardware on timer/counter overflow.Cleared by har...

Semiconductor Group 6-17 On-Chip Peripheral Components C515 Special Function Register TMOD (Address 89H) Reset Value : 00H Bit Function GATE Gating controlWhen set, timer/counter "x" is enabled only while "INT x" pin is high and "TRx" control bit is set.When cleared timer ...

Semiconductor Group 6-18 On-Chip Peripheral Components C515 6.2.1.2 Mode 0 Putting either timer/counter 0,1 into mode 0 configures it as an 8-bit timer/counter with a divide-by-32 prescaler. Figure 6-9 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. A...

Semiconductor Group 6-19 On-Chip Peripheral Components C515 6.2.1.3 Mode 1 Mode 1 is the same as mode 0, except that the timer register is running with all 16 bits. Mode 1 isshown in figure 6-10. Figure 6-10 Timer/Counter 0, Mode 1: 16-Bit Timer/Counter P3.2/INT0 MCS02095 1 & OSC C/T = 0 TL0 TH0...

Semiconductor Group 6-20 On-Chip Peripheral Components C515 6.2.1.4 Mode 2 Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown infigure 6-11. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0,which is preset by software. The...

Semiconductor Group 6-21 On-Chip Peripheral Components C515 6.2.1.5 Mode 3 Mode 3 has different effects on timer 0 and timer 1. Timer 1 in mode 3 simply holds its count. Theeffect is the same as setting TR1=0. Timer 0 in mode 3 establishes TL0 and TH0 as two seperatecounters. The logic for mode 3 on...

Semiconductor Group 6-22 On-Chip Peripheral Components C515 6.2.2 Timer/Counter 2 with Additional Compare/Capture/Reload The timer 2 with additional compare/capture/reload features is one of the most powerful peripheralunits of the C515. lt can be used for all kinds of digital signal generation and ...

Semiconductor Group 6-24 On-Chip Peripheral Components C515 6.2.2.1 Timer 2 Registers This chapter describes all timer 2 related special function registers of timer 2. The interrupt relatedSFRs are also included in this section. Table 6-4 summarizes all timer 2 SFRs. Table 6-4 Special Function Regis...

Semiconductor Group 6-25 On-Chip Peripheral Components C515 The T2CON timer 2 control register is a bitaddressable register which controls the timer 2 functionand the compare mode of registers CRC, CC1 to CC3. Special Function Register T2CON (Address C8H) Reset Value : 00H Bit Function T2PS Prescale...

Semiconductor Group 6-27 On-Chip Peripheral Components C515 Special Function Register IEN0 (Address A8H) Reset Value : 00H Special Function Register IEN1 (Address B8H) Reset Value : 00H Special Function Register IRCON (Address C0H) Reset Value : 00H Bit Function ET2 Timer 2 overflow / external reloa...

Semiconductor Group 6-29 On-Chip Peripheral Components C515 6.2.2.2 Timer 2 Operation The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. Thedetailed operation is described below. Timer Mode In timer function, the count rate is derived from the oscillat...

Semiconductor Group 6-30 On-Chip Peripheral Components C515 Reload of Timer 2 The reload mode for timer 2 is selected by bits T2R0 and T2R1 in SFR T2CON. Figure 6-14 showsthe configuration of timer 2 in reload mode. Mode 0 : When timer 2 rolls over from all l’s to all 0’s, it not only sets TF2 but a...

Semiconductor Group 6-31 On-Chip Peripheral Components C515 6.2.2.3 Compare Function of Registers CRC, CC1 to CC3 The compare function of a timer/register combination can be described as follows. The 16-bit valuestored in a compare/capture register is compared with the contents of the timer register...

Semiconductor Group 6-33 On-Chip Peripheral Components C515 Figure 6-17 Function of Compare Mode 0 6.2.2.3.2 Modulation Range in Compare Mode 0 Generally it can be said that for every PWM generation in compare mode 0 with n-bit wide compareregisters there are 2 n different settings for the duty cycl...

Semiconductor Group 6-34 On-Chip Peripheral Components C515 Figure 6-18 Modulation Range of a PWM Signal, generated with a Timer 2/CCx Register Combination inCompare Mode 0* The following example shows how to calculate the modulation range for a PWM signal. To calculatewith reasonable numbers, a red...

Semiconductor Group 6-37 On-Chip Peripheral Components C515 6.2.2.4 Using Interrupts in Combination with the Compare Function The compare service of registers CRC, CC1, CC2 and CC3 is assigned to alternate output functionsat port pins P1.0 to P1.3. Another option of these pins is that they can be us...

Semiconductor Group 6-39 On-Chip Peripheral Components C515 6.2.2.5 Capture Function Each of the compare/capture registers CC1 to CC3 and the CRC register can be used to latch thecurrent 16-bit value of the timer 2 registers TL2 and TH2. Two different modes are provided for thisfunction. In mode 0, ...

Semiconductor Group 6-41 On-Chip Peripheral Components C515 6.3 Serial Interface The serial port of the C515 is full duplex, meaning it can transmit and receive simultaneously. It isalso receive-buffered, meaning it can commence reception of a second byte before a previouslyreceived byte has been re...

Semiconductor Group 6-43 On-Chip Peripheral Components C515 Special Function Register SCON (Address 98H) Reset Value : 00H Special Function Register SBUF (Address 99H) Reset Value : XXH Bit Function SM0SM1 Serial port 0 operating mode selection bits SM2 Enable serial port multiprocessor communicatio...

Semiconductor Group 6-44 On-Chip Peripheral Components C515 6.3.3 Baud Rate Generation There are several possibilities to generate the baud rate clock for the serial port depending on themode in which it is operating. For clarification some terms regarding the difference between "baud rate clock...

Semiconductor Group 6-45 On-Chip Peripheral Components C515 Figure 6-23 Baud Rate Generation for the Serial Port Depending on the programmed operating mode different paths are selected for the baud rate clockgeneration. Figure 6-23 shows the dependencies of the serial port 0 baud rate clock generati...

Semiconductor Group 6-46 On-Chip Peripheral Components C515 6.3.3.3 Baud Rate in Mode 1 and 3 In these modes the baud rate is variable and can be generated alternatively by a baud rategenerator with a fixed prescaler or by timer 1. 6.3.3.3.1 Using the Baud Rate Generator In modes 1 and 3, the C515 c...

Semiconductor Group 6-47 On-Chip Peripheral Components C515 Table 6-5 Timer 1 generated Commonly used Baud Rates Baud Rate f OSC (MHz) SMOD BD Timer 1 Mode Reload Value Mode 1, 3: 62.5 Kbaud 125 Kbaud 19.5 Kbaud 9.6 Kbaud4.8 Kbaud2.4 Kbaud1.2 Kbaud 110 Baud110 Baud 4.8 Kbaud9.6 Kbaud6.4 Kbaud 12.8 K...

Semiconductor Group 6-49 On-Chip Peripheral Components C515 Figure 6-24 Serial Interface, Mode 0, Functional Diagram MCS02101 Internal Bus 1 SBUF Zero Detector D S CLK Q Shift Send 1 TX Control Start TX Clock TI RX Control Start RI Receive Shift Serial Port Interrupt Input Shift Register SBUF Intern...

Semiconductor Group 6-50 On-Chip Peripheral Components C515 Figure 6-25 Serial Interface, Mode 0, Timing Diagram S 12 S 3 S 4 S 5 S 6 S S 6 S 5 S 4 S 3 S 2 1 S S 6 S 5 S 4 S 3 S 2 1 S S 6 S 5 S 4 S 3 S 2 1 S S 6 S 5 S 4 S 3 S 2 1 S S 6 S 5 S 4 S 3 S 2 1 S S 6 S 5 S 4 S 3 S 2 1 S S 6 S 5 S 4 S 3 S 2 ...

Semiconductor Group 6-57 On-Chip Peripheral Components C515 6.4 A/D Converter The C515 provides an A/D converter with the following features: – 8 multiplexed input channels– The possibility of using the analog inputs (port 6) also as digital inputs– Programmable internal reference voltages (16 steps...

Semiconductor Group 6-58 On-Chip Peripheral Components C515 Figure 6-30 A/D Converter Block Diagram MCB03207 .1 .2.3.4.5.6 MSB (D9 ) H A/D ADDAT Single/ContinuousMode Start ofConversion MUX S & H ÷ 4 Conversion Clock f ADC OSC f Port 6 Shaded bit locations are not used in ADC-functions. IN f Inp...

Semiconductor Group 6-59 On-Chip Peripheral Components C515 6.4.2 A/D Converter Registers This section describes the bits/functions of the registers which are used by the A/D converter. – ADCON (A/D converter control register)– ADDAT (A/D converter data register)– IEN1 and IRCON (A/D converter Inter...

Semiconductor Group 6-60 On-Chip Peripheral Components C515 Note : Generally, before entering the power-down mode, an A/D conversion in progress must be stopped. If a single A/D conversion is running, it must be terminated by polling the BSY bit orwaiting for the A/D conversion interrupt. In continu...

Semiconductor Group 6-61 On-Chip Peripheral Components C515 6.4.2.3 A/D Converter Interrupt Control Bits in IEN1 and IRCON The A/D converter interrupt is controlled by bits which are located in the SFRs IEN1 and IRCON. Special Function Register IEN1 (Address B8H) Reset Value : 00H Special Function R...

Semiconductor Group 6-62 On-Chip Peripheral Components C515 6.4.2.4 Programmable Reference Voltages of the A/D Converter (DAPR Register) The C515 has two pins to which a reference voltage range for the on-chip A/D converter is applied(pin V AREF for the upper voltage and pin V AGND for the lower vol...

Semiconductor Group 6-63 On-Chip Peripheral Components C515 DAPR.3-.0 is the contents of the low-order nibble, and DAPR.7-.4 the contents of the high-ordernibble of DAPR. If DAPR.3-.0 or DAPR.7-.4 = 0, the internal reference voltages correspond to the external referencevoltages V AGND and V AREF , r...

Semiconductor Group 6-66 On-Chip Peripheral Components C515 6.4.3 A/D Conversion Timing An A/D conversion is internally started by writing the SFR DAPR. A write to SFR DAPR will start anew conversion even if a conversion is currently in progress. The conversion begins with the nextmachine cycle, and...

Semiconductor Group 6-68 On-Chip Peripheral Components C515 An A/D conversion is always started with the beginning of a processor cycle when it has beeninitiated by writing SFR ADDAT. The ADDAT write operation may take one or two machine cycles.In figure 6-33, the instruction MOV ADDAT,#0 starts the...

Semiconductor Group 7-1 Interrupt System C515 7 Interrupt System The C515 provides 12 interrupt sources with four priority levels. Five interrupts can be generated bythe on-chip peripherals (timer 0, timer 1, timer 2, A/D converter, and serial interface) and seveninterrupts may be triggered external...

Semiconductor Group 7-2 Interrupt System C515 Figure 7-1 Interrupt Structure, Overview Part 1 MCS03208 Bit addressable Request Flag iscleared by hardware IP1.0 H 0003 TCON.1 IEN0.0 IE0 EX0 P3.2/ IT0 TCON.0 IP0.0 Highest Priority Level EADC IADC IEN1.0 IRCON.0 0043 H A/D Converter IP1.2 IP0.2 Timer 0...

Semiconductor Group 7-4 Interrupt System C515 7.1 Interrupt Registers 7.1.1 Interrupt Enable Registers Each interrupt vector can be individually enabled or disabled by setting or clearing thecorresponding bit in the interrupt enable registers IEN0 and IEN1. Register IEN0 also contains theglobal disa...

Semiconductor Group 7-5 Interrupt System C515 The IEN1 register contains enable/disable flags of the timer 2 external timer reload interrupt, theexternal interrupts 2 to 6, and the A/D converter interrupt. Special Function Register IEN1 (Address B8H) Reset Value : 00H The shaded bit is not used for ...

Semiconductor Group 7-6 Interrupt System C515 7.1.2 Interrupt Request / Control Flags Special Function Register TCON (Address 88H) Reset Value : 00H The shaded bits are not used for interrupt control. The external interrupts 0 and 1 (INT0 and INT1) can each be either level-activated or negativetrans...

Semiconductor Group 7-8 Interrupt System C515 Special Function Register IRCON (Address C0H) Reset Value : 00H Bit Function EXF2 Timer 2 external reload flagEXF2 is set when a reload is caused by a falling edge on pin T2EX while EXEN2 = 1. If ET2 in IEN0 is set (timer 2 interrupt enabled), EXF2 = 1 w...

Semiconductor Group 7-11 Interrupt System C515 7.1.3 Interrupt Priority Registers The lower six bits of these two registers are used to define the interrupt priority level of the interruptgroups as they are defined in table 7-1 in the next section. Special Function Register IP0 (Address A9H) Reset V...

Semiconductor Group 7-12 Interrupt System C515 7.2 Interrupt Priority Level Structure The following table shows the interrupt grouping of the C515 interrupt sources. Each pair of interrupt sources can be programmed individually to one of four priority levels by settingor clearing one bit in the spec...

Semiconductor Group 7-13 Interrupt System C515 7.3 How Interrupts are Handled The interrupt flags are sampled at S5P2 in each machine cycle. The sampled flags are polled duringthe following machine cycle. If one of the flags was in a set condition at S5P2 of the preceedingcycle, the polling cycle wi...

Semiconductor Group 7-14 Interrupt System C515 Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cyclelabeled C3 in figure 7-3 then, in accordance with the above rules, it will be vectored to during C5and C6 without any instruction for the lower priority r...

Semiconductor Group 7-15 Interrupt System C515 7.4 External Interrupts The external interrupts 0 and 1 can be programmed to be level-activated or negative-transitionactivated by setting or clearing bit IT0, respectively in register TCON. If ITx = 0 (x = 0 or 1), externalinterrupt x is triggered by a...

Semiconductor Group 7-16 Interrupt System C515 Figure 7-4 External Interrupt Detection MCD01860 P3.x/INTx e.g. P3.x/INTx > 1 Machine Cycle Low-Level Threshold > 1 Machine Cycle > 1 Machine Cycle Transition to be detected High-Level Threshold Low-Level Threshold b) Transition-Activated Inter...

Semiconductor Group 7-17 Interrupt System C515 7.5 Interrupt Response Time If an external interrupt is recognized, its corresponding request flag is set at S5P2 in every machinecycle. The value is not polled by the circuitry until the next machine cycle. If the request is active andconditions are ri...

Semiconductor Group 8-1 Fail Safe Mechanisms C515 8 Fail Safe Mechanisms 8.1 Watchdog Timer 8.1.1 General Operation As a means of graceful recovery from software or hardware upset a watchdog timer is provided inthe C515. lf the software fails to clear the watchdog timer at least every 65532 m s (at ...

Semiconductor Group 8-2 Fail Safe Mechanisms C515 8.1.3 Refreshing the Watchdog Timer Once started, the watchdog timer can only be cleared to 0000H by first setting bit WDT and with thenext instruction setting bit SWDT. Bit WDT will automatically be cleared during the second machinecycle after havin...

Semiconductor Group 8-3 Fail Safe Mechanisms C515 8.1.5 WDT Control and Status Flags The watchdog timer is controlled by two control flags (located in SFR IEN0 and IEN1) and onestatus flags (located in SFR IP0). Special Function Register IEN0 (Address A8H) Reset Value : 00H Special Function Register...

Semiconductor Group 9-1 Power Saving Modes C515 9 Power Saving Modes The C515 provides two basic power saving modes, the idle mode and the power down mode.Additionally, a slow down mode is available. This power saving mode reduces the internal clock ratein normal operating mode and it can be also us...

Semiconductor Group 9-2 Power Saving Modes C515 9.2 Power Saving Mode Control Register The functions of the power saving modes are controlled by bits which are located in the specialfunction register PCON. The bits PDE, PDS and IDLE, IDLS located in SFR PCON select the powerdown mode or the idle mod...

Semiconductor Group 9-3 Power Saving Modes C515 9.3 Idle Mode In the idle mode the oscillator of the C515 continues to run, but the CPU is gated off from the clocksignal. However, the interrupt system, the serial port, the A/D converter, and all timers with theexception of the watchdog timer are fur...

Semiconductor Group 9-4 Power Saving Modes C515 The idle mode is entered by two consecutive instructions. The first instruction sets the flag bit IDLE(PCON.0) and must not set bit IDLS (PCON.5), the following instruction sets the start bit IDLS(PCON.5) and must not set bit IDLE (PCON.0). The hardwar...

Semiconductor Group 9-5 Power Saving Modes C515 9.4 Slow Down Mode Operation (C515-LM/1RM only) In some applications, where power consumption and dissipation are critical, the controller might runfor a certain time at reduced speed (e.g. if the controller is waiting for an input signal). Since inCMO...

Semiconductor Group 9-6 Power Saving Modes C515 9.5 Power Down Mode In the power down mode, the RC osciillator and the on-chip oscillator which operates with the XTALpins is stopped. Therefore, all functions of the microcontroller are stopped and only the contents ofthe on-chip RAM and the SFR's are...

Semiconductor Group 10-1 Device Specifications C515 10 Device Specifications 10.1 Absolute Maximum Ratings Ambient temperature under bias ( T A ) .............................................................. 0 ˚C to + 110 ˚C Storage temperature ( T ST ) ................................................

Semiconductor Group 10-2 Device Specifications C515 10.2 DC Characteristics V CC = 5 V + 10%, – 15%; V SS = 0 V T A = 0 to 70 ° C for the SAB-C515 T A = – 40 to 85 ° C for the SAF-C515 T A = – 40 to 110 ° C for the SAH-C515 Notes see next page Parameter Symbol Limit Values Unit Test Condition min. m...

Semiconductor Group 10-3 Device Specifications C515 Power Supply Current 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V OL of ALE and ports1, 3, 4, and 5. The noise is due to external bus capacitance discharging into the port 0 and port 2 pinswhen ...

Semiconductor Group 10-4 Device Specifications C515 ICC Diagram MCD03282 0 0 f OSC CC I 4 8 12 16 20 24 5 10 15 20 25 30 MHz mA Active Mode Idle Mode Active Mode with Slow Down = 0.68 x + 2.8 f OSC CC typ I : = 0.85 x + 4.6 : CC max I OSC f = 0.39 x + 3.4 = 0.28 x + 2.4 : : CC max CC typ I I OSC OSC...

Semiconductor Group 10-8 Device Specifications C515 10.5 AC Characteristics (24 MHz) V CC = 5 V + 10%, – 15%; V SS = 0 V T A = 0 to 70 ° C for the SAB-C515 T A = – 40 to 85 ° C for the SAF-C515 T A = – 40 to 110 ° C for the SAH-C515 ( C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other ...

Semiconductor Group 10-10 Device Specifications C515 Program Memory Read Cycle MCT00096 ALE PSEN Port 2 LHLL t A8 - A15 A8 - A15 A0 - A7 Instr.IN A0 - A7 Port 0 t AVLL PLPH t t LLPL t LLIV t PLIV t AZPL t LLAX t PXIZ t PXIX t AVIV t PXAV

Semiconductor Group 10-11 Device Specifications C515 Data Memory Read Cycle MCT00097 ALE PSEN Port 2 WHLH t Port 0 RD t LLDV t RLRH t LLWL t RLDV t AVLL t LLAX2 t RLAZ t AVWL t AVDV t RHDX t RHDZ A0 - A7 from Ri or DPL from PCL A0 - A7 Instr.IN Data IN A8 - A15 from PCH P2.0 - P2.7 or A8 - A15 from ...

Semiconductor Group 10-12 Device Specifications C515 Data Memory Write Cycle MCT00098 ALE PSEN Port 2 WHLH t Port 0 WR t WLWH t LLWL t QVWX t AVLL t LLAX2 t QVWH t AVWL t WHQX A0 - A7 from Ri or DPL from PCL A0 - A7 Instr.IN Data OUT A8 - A15 from PCH P2.0 - P2.7 or A8 - A15 from DPH

Semiconductor Group 10-13 Device Specifications C515 CLKOUT Timing External Clock Drive on XTAL2 MCT00083 ALE CLK OUT PSEN RD,WR t LLSH SLLH t SHSL t SLSH t LLSH t Program Memory Access Data Memory Access MCT00033 t CHCX t CLCX CHCL t CLCH t V CC t CLCL - 0.5V 0.45V CC 0.7 V V - 0.1 CC 0.2

Semiconductor Group 10-14 Device Specifications C515 10.6 ROM Verification Characteristics for the C515-1R ROM Verification Mode 1 ROM Verification Mode 1 Parameter Symbol Limit Values Unit min. max. Address to valid data t AVQV – 10 t CLCL ns MCT03212 t AVQV New Address New Data Out Port 0 Inputs :...

Semiconductor Group 10-15 Device Specifications C515 ROM Verification Mode 2 ROM Verification Mode 2 Parameter Symbol Limit Values Unit min. typ max. ALE pulse width t AWD – 2 t CLCL – ns ALE period t ACY – 12 t CLCL – ns Data valid after ALE t DVA – – 4 t CLCL ns Data stable after ALE t DSA 8 t CLC...

Semiconductor Group 10-16 Device Specifications C515 AC Testing: Input, Output Waveforms AC Testing: Float Waveforms Recommended Oscillator Circuits for Crystal Oscillator AC Inputs during testing are driven at V CC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at ...

Semiconductor Group 10-17 Device Specifications C515 10.7 Package Information (P-LCC-68) GPL05099 0.81 max 1.27 0.43 ±0.1 0.18 M 68x D A-B 20.32 0.1 5.08 max 3.5 ±0.2 0.5 min 0.2 1.2 x 45˚ 23.3 ±0.3 24.21 ±0.07 25.28 -0.26 1) 0.38 M D A-B 34x A B D 1 68 0.5 x 45˚3 x 24.21 ±0.07 1) 25.28 -0.26 1.1 x ...

Semiconductor Group 11-1 Index C515 11 Index A A/D converter . . . . . . . . . . . . . . . 6-57–6-68 Conversion timing . . . . . . . . . . 6-66–6-68General operation . . . . . . . . . . . . . . 6-57Programmable reference voltages . 6-62– 6-65 Registers . . . . . . . . . . . . . . . . . 6-59–6-61 A/D...

Semiconductor Group 11-4 Index C515 Timer/counter 0 and 1 . . . . . . . 6-14–6-21 Mode 0, 13-bit timer/counter . . . . 6-18Mode 1, 16-bit timer/counter . . . . 6-19Mode 2, 8-bit rel. timer/counter . . 6-20Mode 3, two 8-bit timer/counter . . 6-21Registers . . . . . . . . . . . . . . . 6-15–6-17 Timer...