MSI PM-104 Series- Manuals

Page 2 - Features

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Contents 1 Features ........................................................................................................................... 11 2 Introduction ...............................................................................

Page 12 - power switch, and downstream port PCI Hot; Description

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 2 Introduction The Texas Instruments XIO3130 switch is an integrated PCI Express fanout switch solution with oneupstream x1 port and three downstream x1 ports. This high-performance integrated solution provides thelatest in PCI Express sw...

Page 14 - Terminal Assignments; The XIO3130 is packaged in a 196-ball ZHC MicroStarTM BGA.

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 2.5 Terminal Assignments The XIO3130 is packaged in a 196-ball ZHC MicroStar™ BGA. Table 2-1. XIO3130 Terminal Assignments A B C D E F G H J K L M N P VSSA DN2_ VSSA DN2_ DN2_ DN2_ 14 GPIO12 SCL VDD15 GPIO4 VDD15 GPIO15 VDD15 VDD15 (2) PE...

Page 15 - Table 2-2. XIO3130 Terminals Sorted Alphanumerically

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 2-2. XIO3130 Terminals Sorted Alphanumerically Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name A01 DN3_PERST C13 VDD15 F11 VSSA(2) J08 VSS M06 VDDA15(3) A02 DN2_PERST C14 VDD15 F12 VSSA(2) J09 VS...

Page 16 - Table 2-3. XIO3130 Signal Names Sorted Alphabetically

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 2-3. XIO3130 Signal Names Sorted Alphabetically Signal Name Ball Signal Name Ball CLKREQ_UP N02 GPIO5 L12 DN1_DPSTRP C10 GPIO6 M13 DN1_PERn B06 GPIO7 P13 DN1_PERp A06 GPIO8 M10 DN1_PERST B05 GPIO9 N03 DN1_PETn B08 GRST C02 DN1_PETp ...

Page 17 - Terminal Descriptions

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 2.6 Terminal Descriptions Table 2-4. Power Supply Terminals Signal Ball I/O Type External parts Description G04, H02, H04, J04, 1.5-V analog power terminals for PCI-Express upstream port VDDA15(0) PWR Filter K03 0 1.5-V analog power termi...

Page 18 - Table 2-7. PCI Express Reference Clock Terminals

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 2-6. Ground Terminals Signal Ball I/O Type Description D05, D06, D10, D11, E05, E06, E07, E08, E09, E10, E11, E12, F05, F06, F07, F08, F09, F10, G05, G06, G07, G08, G09, G10, VSS GND Digital ground terminals H05, H06, H07, H08, H09,...

Page 19 - Table 2-9. PCI Hot Plug Strapping Terminals

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 2-8. PCI Express Terminals Signal Ball I/O Type External Parts Description UP_PETp G01 HS DIFF Series capacitors High-speed differential transmit pair for upstream port 0 UP_PETn G02 OUT DN1_PETp A08 HS DIFF Series capacitors High-s...

Page 23 - Express Interface; External Reference Clock

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Figure 3-2. Power-Up Sequence Diagram 3.1.2 Power-Down Sequence • Assert PERST to the device. • Remove the reference clock. • Remove 3.3-V and 1.5-V voltages. See the power-down sequence diagram in Figure 3-3 . If the VAUX33REF terminal i...

Page 24 - Table 3-1. Initial Flow Control Credit Advertisements; PCI Express Message Transactions; outlines

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 3.2.3 Beacon The XIO3130 supports the PCI Express in-band beacon feature. Beacon is driven on the PCI Express linkby the XIO3130 to request the re-application of main power when in the L2 link state. Once beacon isactivated, the XIO3130 c...

Page 25 - Table 3-2. Messages Supported by the XIO3130; GPIO Terminals; through; Serial EEPROM; Serial Bus Interface Implementation

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 3-2. Messages Supported by the XIO3130 Message Supported XIO3130 Action Assert_INTx Yes Passed through upstream Deassert_INTx Yes Passed through upstream PM_Active_State_Nak Yes Received and processed Passed through upstream PM_PME ...

Page 26 - Serial Bus Interface Protocol

XIO3130 SCL SDA SERIAL EEPROM SCL A2 A1 SDA A0 VDD3 3 XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com edge of PERST or GRST, whichever occurs last, the SCL terminal is checked for a pullup resistor. If oneis detected, bit 3 (SBDETECT) in the serial bus control and status register (see ...

Page 27 - illustrates the acknowledge protocol.

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Figure 3-5. Serial-Bus Start/Stop Conditions and Bit Transfers Data is transferred serially in 8-bit bytes. During a data transfer operation, an unlimited number of bytesare transmitted. However, each byte must be followed by an acknowled...

Page 28 - Serial Bus EEPROM Application

S b6 b1 b2 b3 b4 b5 b0 1 A b7 b6 b1 b2 b3 b4 b5 b0 A Slave Address Word Address Start R/W S Restart b6 b1 b2 b3 b4 b5 b0 0 A Slave Address R/W b7 b6 b1 b2 b3 b4 b5 b0 M Data Byte P A = Slave Acknowledgement M = Master Acknowledgement S/P = Start/Stop Condition XIO3130 SLLS693F – MAY 2007 – REVISED J...

Page 31 - Accessing Serial Bus Devices Through Software; Monitors REQBUSY until this bit is negated.; Switch Reset Features; Four XIO3130 reset options are available:

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 This download table must be explicitly followed for the XIO3130 to correctly load initialization values froma serial EEPROM. All byte locations must be considered when programming the EEPROM. The XIO3130 addresses the serial EEPROM using ...

Page 33 - PCI Configuration Register Space Overview; illustrates the enumeration topology.; NOTE

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4 XIO3130 Configuration Register Space This chapter specifies the configuration registers that are used to enumerate the XIO3130 device within aPC system. An overview of the configuration register space is provided along with a detailed d...

Page 34 - Virtual Internal PCI Bus; Figure 4-1. XIO3130 Enumerations Topology; PCI Express Upstream Port Registers

** Example values. Actual bus numbers may change based on system hierarchy. Virtual Internal PCI Bus Downstream Port Header Type 01h PCI Capability Structures / Proprietary Register Space Extended Configuration Space / PCI Express Capability Structures 000h 03Fh 040h 0FFh 100h FFFh Port# 1 Bus# N+2*...

Page 35 - PCI Configuration Space (Upstream Port) Register Map

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.2.1 PCI Configuration Space (Upstream Port) Register Map Table 4-1. PCI Express Upstream Port Configuration Register Map (Type 1) Register Name Offset Device ID Vendor ID 000h Status Command 004h Class Code Revision ID 008h BIST Header ...

Page 37 - Table 4-3. Bit Descriptions – Command Register; Status Register; Read Only Cleared by a Write of One Hardware Update

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-3. Bit Descriptions – Command Register BIT FIELD NAME ACCESS DESCRIPTION 15:11 RSVD r Reserved. When read, these bits return zeros. INTx disable. This bit is used to enable device-specific interrupts. The XIO3130 upstream port doe...

Page 38 - Table 4-4. Bit Descriptions – Status Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-4. Bit Descriptions – Status Register BIT FIELD NAME ACCESS DESCRIPTION Detected parity error. This bit is set when the PCI Express interface receives a poisoned TLP on theupstream port. This bit is set regardless of the state of ...

Page 39 - Class Code and Revision ID Register; Read only; Table 4-5. Bit Descriptions – Class Code and Revision ID Register; Cache Line Size Register; Read Only

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.2.6 Class Code and Revision ID Register This read-only register categorizes the Base Class, Sub Class, and Programming Interface of theXIO3130. The Base Class is 06h, identifying the device as bridge device. The Sub Class is 04h,identif...

Page 40 - Header Type Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.2.9 Header Type Register This read-only register indicates that this function has a type one PCI header. Bit seven of this register is azero, indicating that the upstream port is a single device. PCI register offset: 0Eh Register type: ...

Page 42 - Table 4-8. Bit Descriptions – Secondary Status Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.2.16 I/O Limit Register This read/write register specifies the upper limit of the I/O addresses that the XIO3130 forwardsdownstream. PCI register offset: 1Dh Register type: Read/Write; Read Only Default value: 01h BIT NUMBER 7 6 5 4 3 2...

Page 47 - Table 4-17. Bit Descriptions – Bridge Control Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-17. Bit Descriptions – Bridge Control Register BIT FIELD NAME ACCESS DESCRIPTION 15:12 RSVD r Reserved. When read, these bits return zeros. 11 DTSERR r Discard timer SERR enable. This bit is hardwired to zero. This bit does not ap...

Page 48 - 2 Power Management Capabilities Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-17. Bit Descriptions – Bridge Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Parity error response enable. It is assumed that the relevant error checking is unnecessary for the 0 PERR_EN rw XIO3130’s internal PCI b...

Page 50 - 4 Power Management Bridge Support Extension Register; Table 4-20. Bit Descriptions – PM Bridge Support Extension Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.2.34 Power Management Bridge Support Extension Register This read-only register is used to indicate to host software the state of the secondary bus when theXIO3130 is placed in D3. PCI register offset: 56h Register type: Read only Defau...

Page 51 - This register is used to control the sending of MSI messages.; Table 4-21. Bit Descriptions – MSI Message Control Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 1 0 0 0 0 0 0 0 4.2.38 MSI Message Control Register This register is used to control the sending of MSI messages. PCI register offset: 72h Register type: Read/Write; Read Only Default value: 0080h BI...

Page 52 - Table 4-22. Bit Descriptions – MSI Message Address Register; 0 MSI Message Upper Address Register; Table 4-23. Bit Descriptions – MSI Data Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-22. Bit Descriptions – MSI Message Address Register BIT FIELD NAME ACCESS DESCRIPTION 31:2 ADDRESS rw System Specified Message Address. 1:0 RSVD r Reserved. When read, these bits return zeros. 4.2.40 MSI Message Upper Address Regi...

Page 53 - 6 PCI Express Capability ID Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 1 1 0 1 4.2.43 Next-Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for theXIO3130. This register reads 90h, which poin...

Page 54 - Table 4-24. Bit Descriptions – PCI Express Capabilities Register; Read Only Hardware Update

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.2.47 Next-Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for theXIO3130. This register reads 00h, which indicates that no additional capabilities are supported. PC...

Page 56 - Read Only Clear by a Write of One Hardware Update

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-26. Bit Descriptions – Device Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Enable no snoop. Since the XIO3130 does not initiate such transactions, this bit is read-only 11 ENS r zero. Auxiliary power PM enable. T...

Page 57 - Table 4-27. Bit Descriptions – Device Status Register; Table 4-28. Bit Descriptions – Link Capabilities Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-27. Bit Descriptions – Device Status Register BIT FIELD NAME ACCESS DESCRIPTION 15:6 RSVD r Reserved. When read, these bits return zeros. Transaction PENDING. This bit is set when the XIO3130 has issued a non-posted transaction 5 ...

Page 58 - Table 4-29. Bit Descriptions – Link Control Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-28. Bit Descriptions – Link Capabilities Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Maximum link width. This field is encoded 000001b to indicate that the device only supports 9:4 MLW r an x1 PCI Express link. Maximum ...

Page 59 - Table 4-30. Bit Descriptions – Link Status Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.2.54 Link Status Register The Link Status register indicates the current state of the PCI Express Link. PCI register offset: A2h Register type: Read only Default value: 1X11h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE ...

Page 60 - Table 4-31. Bit Descriptions – Serial Bus Slave Address Register; 8 Serial Bus Control and Status Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.2.57 Serial Bus Slave Address Register The Serial Bus Slave Address register is used to indicate the address of the device being targeted by theserial bus cycle. This register also indicates whether the cycle will be a read or a write c...

Page 61 - 9 Upstream Port Link PM Latency Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-32. Bit Descriptions – Serial Bus Control and Status Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the XIO3130device is downloading register d...

Page 63 - Table 4-34. Bit Descriptions – Global Chip Control Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-33. Bit Descriptions – Upstream Port Link PM Latency Register (continued) BIT FIELD NAME ACCESS DESCRIPTION L1 exit latency. This field is used to program the maximum latency for the PHY to exit the L1state. This field is used to ...

Page 64 - BCh

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-34. Bit Descriptions – Global Chip Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Minimum power scale. This value is programmed to indicate the scale of the MinimumPower Value field. 00 – 1.0x MIN_POWER_SCA 01 – 0....

Page 65 - Table 4-35. Bit Descriptions – GPIO A Control Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-35. Bit Descriptions – GPIO A Control Register BIT FIELD NAME ACCESS DESCRIPTION 15 RSVD r Reserved. Reads back zero. GPIO 4 Control. Thi...

Page 66 - BEh

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-35. Bit Descriptions – GPIO A Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION GPIO 1 Control. This field controls the GPIO1 pin as follows: 000 – General Purpose Input (default) 001 – General Purpose Output 010 – Po...

Page 67 - Table 4-36. Bit Descriptions – GPIO B Control Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-36. Bit Descriptions – GPIO B Control Register BIT FIELD NAME ACCESS DESCRIPTION 15 RSVD r Reserved, reads back zero GPIO 9 Control. This field controls the GPIO9 pin as follows: 000 – General Purpose Input (default) 001 – General...

Page 69 - Table 4-37. Bit Descriptions – GPIO C Control Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-37. Bit Descriptions – GPIO C Control Register BIT FIELD NAME ACCESS DESCRIPTION 15 RSVD r Reserved. Reads back zero. GPIO 14 Control. This field controls the GPIO14 pin as follows: 000 – General Purpose Input (default) 001 – Gene...

Page 71 - Table 4-38. Bit Descriptions – GPIO D Control Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-38. Bit Descriptions – GPIO D Control Register BIT FIELD NAME ACCESS DESCRIPTION 15:10 RSVD r Reserved. When read, these bits return zeros. GPIO 18 Control. This field controls the GPIO18 pin as follows: 00 – General Purpose Input...

Page 72 - Table 4-39. Bit Descriptions – GPIO Data Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.2.65 GPIO Data Register This register is used to read the state of the GPIO pins and to change the state of GPIO pins that are inoutput mode. Reads to this register return the state of the GPIO pins, regardless of PCI Hot Plugstrapping ...

Page 75 - CCh

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.2.66 TI Proprietary Register This read/write TI proprietary register is located at offset C8h and controls TI proprietary functions. Thisregister must not be changed from the specified default state. If the default value is changed in e...

Page 76 - DCh

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.2.69 TI Proprietary Register This read/write TI proprietary register is located at offset D4h and controls TI proprietary functions. Thisregister must not be changed from the specified default state. If the default value is changed in e...

Page 78 - 4 Downstream Ports Link PM Latency Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.2.74 Downstream Ports Link PM Latency Register This read/write register is used to program L0s and L1 exit latencies for all XIO3130 downstream ports.Similar information is provided in a separate register for the upstream port. PCI regi...

Page 79 - EAh; Table 4-43. Bit Descriptions – Global Switch Control Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-42. Bit Descriptions – Downstream Ports Link PM Latency Register (continued) BIT FIELD NAME ACCESS DESCRIPTION L1 exit latency. This field is used to program the maximum latency for the PHY to exit theL1 state. This is used to set...

Page 80 - 6 Advanced Error Reporting Capability ID Register; 8 Uncorrectable Error Status Register; Read Only, Cleared by a Write of one

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-43. Bit Descriptions – Global Switch Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Beacon detect disable. This bit disables beacon detection on all downstream ports and allows thereference macro to be placed in lo...

Page 82 - 0 Uncorrectable Error Severity Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-45. Uncorrectable Error Mask Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Malformed TLP mask. 18 MAL_TLP_MASK rwh 0 - Error condition is unmasked. 1 - Error condition is masked. Receiver Overflow mask. 17 RX_OVERFLOW_MAS...

Page 83 - Table 4-46. Uncorrectable Error Severity Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-46. Uncorrectable Error Severity Register BIT FIELD NAME ACCESS DESCRIPTION 31:21 RSVD r Reserved. Return zeros when read. Unsupported Request error severity. 20 UR_ERROR_SEVR rwh 0 - Error condition is signaled using ERR_NONFATAL...

Page 85 - 3 Advanced Error Capabilities and Control Register; Table 4-49. Advanced Error Capabilities and Control Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-48. Correctable Error Mask Register (continued) BIT FIELD NAME ACCESS DESCRIPTION REPLAY_NUM rollover mask. 8 REPLAY_ROLL_MASK rwh 0 – Error condition is unmasked 1 – Error condition is masked Bad DLLP error mask. 7 BAD_DLLP_MASK ...

Page 87 - PCI Express Downstream Port Registers; PCI Configuration Space (Downstream Port) Register Map

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.3 PCI Express Downstream Port Registers The default reset domain for all downstream port registers is SBRST. Some register fields are placed in adifferent reset domain from the default reset domain; all bit and field descriptions identi...

Page 88 - Vendor ID Register; Device ID Register; Command Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-51. Extended Configuration Space (Downstream Port) Register Name Offset Next Capability Offset / Capability Version PCI Express Advanced Error Reporting Capabilities ID 100h Uncorrectable Error Status Register 104h Uncorrectable E...

Page 89 - Table 4-52. Bit Descriptions – Command Register; Table 4-53. Bit Descriptions – Status Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-52. Bit Descriptions – Command Register BIT FIELD NAME ACCESS DESCRIPTION 15:11 RSVD r Reserved. When read, these bits return zeros. INTx disable. This bit is used to enable device-specific INTx interrupts. The XIO3130downstream p...

Page 90 - Table 4-54. Bit Descriptions – Class Code and Revision ID Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-53. Bit Descriptions – Status Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Received master abort. This bit is hardwired to zero. It is assumed that the relevant error 13 MABORT r checking is unnecessary for the XIO3130 i...

Page 95 - Table 4-59. Bit Descriptions – Memory Limit Register; Table 4-60. Descriptions – Pre-fetchable Memory Base Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.3.19 Memory Limit Register This read/write register specifies the upper limit of the memory addresses that the downstream portforwards downstream. PCI register offset: 22h Register type: Read/Write; Read Only Default value: 0000h BIT NU...

Page 96 - Table 4-61. Bit Descriptions – Pre-fetchable Memory Limit Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-61. Bit Descriptions – Pre-fetchable Memory Limit Register BIT FIELD NAME ACCESS DESCRIPTION Pre-fetchable memory limit. This field defines the top address of the pre-fetchable memoryaddress range that is used to determine when to...

Page 97 - Table 4-64. Bit Descriptions – I/O Base Upper 16 Bits Register; Table 4-65. Bit Descriptions – I/O Limit Upper 16 Bits Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.3.24 I/O Base Upper 16 Bits Register This read/write register specifies the upper 16 bits of the I/O Base register. PCI register offset: 30h Register type: Read/Write Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 98 - Table 4-66. Bit Descriptions – Bridge Control Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.3.27 Interrupt Line Register This read/write register, which the system programs, indicates to the software which interrupt line that theXIO3130 downstream port has assigned to it. The default value of this register is FFh, which indica...

Page 100 - 2 Power Management Capabilities Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.3.30 Capability ID Register This read-only register identifies the linked list item as the register for PCI power management. It returns01h when read. PCI register offset: 50h Register type: Read only Default value: 01h BIT NUMBER 7 6 5...

Page 102 - 4 Power Management Bridge Support Extension Register; Table 4-69. Bit Descriptions – PM Bridge Support Extension Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.3.34 Power Management Bridge Support Extension Register This read-only register is used to indicate to the host software what the state of the downstream port’ssecondary bus will be when the downstream port is placed in D3. PCI register...

Page 103 - Table 4-70. Bit Descriptions – MSI Message Control Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 1 0 0 0 0 0 0 0 4.3.38 MSI Message Control Register This register is used to control the sending of MSI messages. PCI register offset: 72h Register type: Read/Write; Read Only Default value: 0080h BI...

Page 104 - Table 4-71. Bit Descriptions – MSI Message Address Register; 0 MSI Message Upper Address Register; Table 4-72. Bit Descriptions – MSI Data Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-71. Bit Descriptions – MSI Message Address Register BIT FIELD NAME ACCESS DESCRIPTION 31:2 ADDRESS rw System-specified message address. 1:0 RSVD r Reserved. When read, these bits return zeros. 4.3.40 MSI Message Upper Address Regi...

Page 106 - 6 PCI Express Capability ID Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.3.43 Next-Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for theXIO3130 downstream port. This register reads 90h, which points to the PCI Express Capabilities regi...

Page 107 - Table 4-73. Bit Descriptions – PCI Express Capabilities Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4.3.47 Next-Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for theXIO3130 downstream port. This register reads 00h, which indicates that no additional capabilities a...

Page 110 - Table 4-76. Bit Descriptions – Device Status Register; Table 4-77. Bit Descriptions – Link Capabilities Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-76. Bit Descriptions – Device Status Register BIT FIELD NAME ACCESS DESCRIPTION 15:6 RSVD r Reserved. When read, these bits return zeros. Transaction pending. This bit is set when the XIO3130 downstream port has issued a 5 PEND ru...

Page 111 - Table 4-78. Bit Descriptions – Link Control Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-77. Bit Descriptions – Link Capabilities Register (continued) BIT FIELD NAME ACCESS DESCRIPTION L1 exit latency. This field indicates the time required to transition from the L1 state to the L0state. This field is a direct reflect...

Page 112 - Table 4-79. Bit Descriptions – Link Status Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-78. Bit Descriptions – Link Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Read completion boundary. This bit specifies the minimum size read completion packet that theXIO3130 can send when breaking a read request ...

Page 113 - Table 4-80. Bit Descriptions – Slot Capabilities Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 Table 4-80. Bit Descriptions – Slot Capabilities Register BIT FIELD NAME ACCESS DESCRIPTION Physical slot number. This field indicates a system-d...

Page 114 - The Slot Control register controls slot-specific parameters.; Table 4-81. Bit Descriptions – Slot Control Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-80. Bit Descriptions – Slot Capabilities Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Manual retention latch sensor present. This bit indicates whether a manual retention latch(MRL) sensor is implemented on the chassis f...

Page 116 - Table 4-82. Bit Descriptions – Slot Status Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-81. Bit Descriptions – Slot Control Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Attention button pressed enable. This bit enables generation of a • ＝＝＝＝＝＝＝＝＝ PCI Hot Plug interrupt • ＝＝＝＝＝＝＝＝＝ PME when the ABP bit in th...

Page 118 - Table 4-83. Bit Descriptions – General Control Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 4.3.60 TI Proprietary Register This read/write TI proprietary register is located at offset D0h and controls TI proprietary functions. Thisregister must not be changed from the specified default state. If the default value is changed in e...

Page 121 - Table 4-84. Bit Descriptions – General Slot Info Register; 4 Advanced Error Reporting Capabilities ID Register; 6 Uncorrectable Error Status Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-84. Bit Descriptions – General Slot Info Register BIT FIELD NAME ACCESS DESCRIPTION Slot number. This field is used to program the Physic...

Page 123 - 8 Uncorrectable Error Severity Register

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 4-86. Uncorrectable Error Mask Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Malformed TLP mask. 18 MAL_TLP_MASK rwh 0 - Error condition is unmasked. 1 - Error condition is masked. Receiver Overflow mask. 17 RX_OVERFLOW_MAS...

Page 124 - Table 4-87. Uncorrectable Error Severity Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-87. Uncorrectable Error Severity Register BIT FIELD NAME ACCESS DESCRIPTION 31:21 RSVD r Reserved. Return zeros when read. Unsupported Request error severity. 20 UR_ERROR_SEVR rwh 0 - Error condition is signaled using ERR_NONFATAL...

Page 126 - 1 Advanced Error Capabilities and Control Register; Table 4-90. Advanced Error Capabilities and Control Register

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Table 4-89. Correctable Error Mask Register (continued) BIT FIELD NAME ACCESS DESCRIPTION Bad DLLP error mask. 7 BAD_DLLP_MASK rwh 0 – Error condition is unmasked 1 – Error condition is masked Bad TLP error mask. 6 BAD_TLP_MASK rwh 0 – Er...

Page 128 - PCI Hot Plug Architecture Overview

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 5 PCI Hot Plug Implementation Overview 5.1 PCI Hot Plug Architecture Overview The PCI Express architecture is designed to natively support both hot-add and hot-removal (collectivelyHot-Plug) of adapters. The architecture also provides a ‘...

Page 129 - In; Table 5-3. Pins Assigned to GPIO Control Registers

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 Table 5-1. GPIO Matrix (continued) GPIO[#] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EMILENG3 7 7 In Table 2-11 , S indicates a strapping option. If the appropriate DNn_DPSTRP pin is pulled high, the GPIO is mapped to this value and is no ...

Page 130 - PCI Hot Plug Timing; NonPCI Hot Plug Power-Up Cycle; PCI Hot Plug Power-Up Cycle With No PWRGDn Feedback

PERSTn# REFCLKn PERST# Stable Unstable <100 s m PWRGDn CLKREQn# REFCLKn PERSTn# PWRONn# Unstable Stable 100 ms >100 s m XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 5.2 PCI Hot Plug Timing 5.2.1 Power-Up Cycle The XIO3130 switch can be powered up numerous ways depending on the...

Page 131 - Figure 5-3. PCI Hot Plug Power-Up Cycle With No PWGRDn Feedback

PWRGDn CLKREQn# REFCLKn PERSTn# PWRONn# Unstable Stable 100 ms >100 s m 100 ms PWRGDn CLKREQn# REFCLKn PERSTn# PWRONn# Stable < 100 s m XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 power-up cycle. The XIO3130 switch asserts PWRONn and because the PWRGDn signal is tied high, th...

Page 132 - Note that once PERSTn goes low, it must remain low for at least 100 ms.

PWRONn# CLKREQn# REFCLKn PERSTn# PRSNTn# Stable PWRGDn <500 ns <100 s m PWRONn# CLKREQn# REFCLKn PERSTn# PWRGDn Stable Unstable Stable <500 ns 100 ms >100 s m XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com Figure 5-5. Surprise Removal In the case of surprise removal, the X...

Page 133 - Debounce Circuits; A timeout of approximately 10 ms is used.

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 5.2.4 Debounce Circuits Integrated de-bounce circuits are provided for the following input pins: • PRSNT[2:0] present detects for each downstream port; used with PCI Express or ExpressCard(formerly NEWCARD) slots. • ATN_BTN[2:0], which ar...

Page 134 - Absolute Maximum Ratings

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 6 Electrical Characteristics This chapter describes the electrical characteristics of the XIO3130. 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VALUE UNIT VDDRC,VAUX33REF, –0.5 to 3.6...

Page 135 - PCI Express Differential Transmitter Output Ranges

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 6.3 PCI Express Differential Transmitter Output Ranges PARAMETER TERMINALS MIN NOM MAX UNIT COMMENTS UI PETP, Each UI is 400 ps ±300 ppm. UI does not account 399.88 400 400.12 ps Unit interval PETN for SSC dictated variations.See (1) V TX...

Page 136 - PCI Express Differential Transmitter Output Ranges (continued); PCI Express Differential Receiver Input Ranges

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com PCI Express Differential Transmitter Output Ranges (continued) PARAMETER TERMINALS MIN NOM MAX UNIT COMMENTS Maximum time to meet all TX specifications when T TX-IDLE-to-DIFF-DATA transitioning from electrical idle to sending Maximum time...

Page 137 - PCI Express Differential Receiver Input Ranges (continued); PCI Express Differential Reference Clock Input Ranges

XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 PCI Express Differential Receiver Input Ranges (continued) PARAMETER TERMINALS MIN NOM MAX UNIT COMMENTS Measured over 50 MHz to 1.25 GHz with the P RL RX-DIFF PERP, and N lines biased at +300 mV and –300 mV, 10 dB Differential return los...

Page 138 - PCI Express Reference Clock Output Requirements

XIO3130 SLLS693F – MAY 2007 – REVISED JANUARY 2010 www.ti.com 6.6 PCI Express Reference Clock Output Requirements 100-MHz INPUT SYMBOL PARAMETER UNIT NOTES MIN MAX Rise Edge Rate Rising edge rate 0.6 4 V/ns See (1) and (2) . Fall Edge Rate Falling edge rate 0.6 4 V/ns See (1) and (2) . V IH Differen...

Page 140 - PACKAGE OPTION ADDENDUM; PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM www.ti.com 15-Dec-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples XIO3130IZHC ACTIVE BGA MICROSTAR ZHC 196 126 Gr...

Page 143 - IMPORTANT NOTICE

IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherchanges to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latestissue. Buyers ...