Lucent Technologies MN102F85K - Manuals

Page 3 - and semiconductors described in this book; of patents or any other rights owned by a third party.

PanaXSeries is a trademark of Matsushita Electric Industrial Co., Ltd.The other corporation names, logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations. Request for your special attention and precautions in using the technical in...

Page 4 - M N 1 0 2 H 7 5 K / F 7 5 K L S I U s e r M a n u a l; C o n t e n t s

C o n t e n t s M N 1 0 2 H 7 5 K / F 7 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 3 Panasonic C o n t e n t s About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5 - P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y; Setting Up I

C o n t e n t s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K L S I U s e r M a n u a l 4 Panasonic 4.5.1 Setting Up an Event Counter Using Timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4...

Page 8 - Setting Up the I; Appendix A

C o n t e n t s M N 1 0 2 H 7 5 K / F 7 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 7 Panasonic 11 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

Page 10 - L i s t o f T a b l e s; M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l; L i s t o f Ta b l e s

L i s t o f T a b l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 9 Panasonic L i s t o f Ta b l e s 1-1 General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 11 - Operating Modes for Devices on an I

L i s t o f T a b l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 10 Panasonic 8-5 IR Remote Signal Receiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

Page 12 - L i s t o f F i g u r e s

L i s t o f F i g u r e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 11 Panasonic L i s t o f F i g u r e s 1-1 Conventional vs. MN102H Series Code Assignments . . . . . . . . . . . . . . . ....

Page 14 - Master Transmitter Timing in I

L i s t o f F i g u r e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 13 Panasonic 5-12 Serial Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 16 - Example of I

L i s t o f F i g u r e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 15 Panasonic 11-16 P30/CLH and P33/CLL (Port 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 17 - U s i n g T h i s M a n u a l; U s i n g T h i s M a n u a l; REGISTER: Register Name; Key information; These notes summarize key points relating to an operation.

A b o u t T h i s M a n u a l U s i n g T h i s M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 16 Panasonic A b o u t T h i s M a n u a l This manual is intended for assembly-language...

Page 18 - R e l a t e d D o c u m e n t s; MN102H Series LSI User Manual

A b o u t T h i s M a n u a l R e l a t e d D o c u m e n t s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 17 Panasonic R e l a t e d D o c u m e n t s ■ MN102H Series LSI User Manual (Describe...

Page 19 - M N 1 0 2 H S e r i e s O v e r v i e w; G e n e r a l D e s c r i p t i o n; M N 1 0 2 H S e r i e s O v e r v i e w; speed and functionality.; M N 1 0 2 H S e r i e s F e a t u r e s; High-speed signal processing

G e n e r a l D e s c r i p t i o n M N 1 0 2 H S e r i e s O v e r v i e w P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 18 Panasonic 1 G e n e r a l D e s c r i p t i o n 1 . 1 M N 1 0 2 H S e...

Page 20 - Single-byte basic instruction length; load/store operations occupy only one byte.; High-speed pipeline throughput; most frequently used basic instructions are single-byte.; New Panasonic code assignments

G e n e r a l D e s c r i p t i o n M N 1 0 2 H S e r i e s F e a t u r e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 19 Panasonic ■ Single-byte basic instruction length The MN102H series ha...

Page 21 - Fast interrupt response; The MN102H series combines hardware optimized for C language pro-

G e n e r a l D e s c r i p t i o n M N 1 0 2 H S e r i e s F e a t u r e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 20 Panasonic ■ Fast interrupt response MN102H series devices can stop ex...

Page 22 - Outstanding power savings; array of embedded designs.; M N 1 0 2 H S e r i e s D e s c r i p t i o n; operation results; VX: Extension overflow

G e n e r a l D e s c r i p t i o n M N 1 0 2 H S e r i e s D e s c r i p t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 21 Panasonic ■ Outstanding power savings The MN102H series contain...

Page 23 - NX: Extension negative flag

G e n e r a l D e s c r i p t i o n M N 1 0 2 H S e r i e s D e s c r i p t i o n P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 22 Panasonic NX: Extension negative flag If the most significant b...

Page 26 - CPU Core; Interrupt Controller; Figure 1-7 Interrupt Servicing Sequence

G e n e r a l D e s c r i p t i o n M N 1 0 2 H S e r i e s D e s c r i p t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 25 Panasonic ■ Interrupt controller An interrupt controller extern...

Page 27 - G e n e r a l S p e c i f i c a t i o n s; Table 1-1 General Specifications

G e n e r a l D e s c r i p t i o n G e n e r a l S p e c i f i c a t i o n s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 26 Panasonic 1 . 4 G e n e r a l S p e c i f i c a t i o n s Table 1-1...

Page 29 - B l o c k D i a g r a m; B l o ck D i a g r a m; Figure 1-8 Functional Block Diagram

G e n e r a l D e s c r i p t i o n B l o c k D i a g r a m P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 28 Panasonic 1 . 5 B l o ck D i a g r a m Figure 1-8 Functional Block Diagram A1 A0 A3 A...

Page 31 - P i n D e s c r i p t i o n s; M N 1 0 2 H 8 5 K P i n D e s c r i p t i o n; Figure 1-9 MN102H85K Pin Configuration in Single-Chip Mode; Top View

G e n e r a l D e s c r i p t i o n P i n D e s c r i p t i o n s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 30 Panasonic 1 . 6 P i n D e s c r i p t i o n s 1 . 6 . 1 M N 1 0 2 H 8 5 K P i n...

Page 32 - M N 1 0 2 H 7 5 K P i n D e s c r i p t i o n; Figure 1-10 MN102H75K Pin Configuration in Single-Chip Mode

G e n e r a l D e s c r i p t i o n P i n D e s c r i p t i o n s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 31 Panasonic 1 . 6 . 2 M N 1 0 2 H 7 5 K P i n D e s c r i p t i o n Notes: 1. Pin...

Page 36 - B u s I n t e r f a c e; D e s c r i p t i o n; memory space for the MCU in this mode.; External Expansion Mode

G e n e r a l D e s c r i p t i o n B u s I n t e r f a c e M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 35 Panasonic 1 . 7 B u s I n t e r f a c e 1 . 7 . 1 D e s c r i p t i o n The bus inter...

Page 37 - B u s I n t e r f a c e C o n t r o l R e g i s t e r s; the external oscillator is 4 MHz, one wait is 83 ns.

G e n e r a l D e s c r i p t i o n B u s I n t e r f a c e P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 36 Panasonic 1 . 7 . 2 B u s I n t e r f a c e C o n t r o l R e g i s t e r s The exter...

Page 38 - I n t e r r u p t s; parable MCU in the previous generation of the 16-bit series.

I n t e r r u p t s D e s c r i p t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 37 Panasonic 2 I n t e r r u p t s 2 . 1 D e s c r i p t i o n The most important factor in real-time cont...

Page 40 - Program

I n t e r r u p t s D e s c r i p t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 39 Panasonic Figure 2-3 Interrupt Servicing Time Table 2-2 Handler Preprocessing Sequence Assembler Bytes ...

Page 41 - I n t e r r u p t S e t u p E x a m p l e s; S e t t i n g U p a n E x t e r n a l P i n I n t e r r u p t; external interrupt pin, and the interrupt priority level is 5.; CORE

I n t e r r u p t s I n t e r r u p t S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 40 Panasonic 2 . 2 I n t e r r u p t S e t u p E x a m p l e s 2 . 2 . 1 S e t t i n...

Page 43 - S e t t i n g U p a Wa t ch d o g Ti m e r I n t e r r u p t; Enabling watchdog timer interrupts; Clearing the watchdog timer; Figure 2-6 Block Diagram of Watchdog Timer Interrupt

I n t e r r u p t s I n t e r r u p t S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 42 Panasonic 2 . 2 . 2 S e t t i n g U p a Wa t ch d o g Ti m e r I n t e r r u p t ...

Page 44 - Figure 2-7 Timing for Watchdog Timer Interrupt Setup (Example)

I n t e r r u p t s I n t e r r u p t S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 43 Panasonic The main program normally gen- erates and branches to the inter- rupt s...

Page 45 - I n t e r r u p t C o n t r o l R e g i s t e r s; ID : Interrupt detect flag; : Interrupt undetected; IE: Interrupt enable flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 44 Panasonic 2 . 3 I n t e r r u p t C o n t r o l R e g i s t e r s A control...

Page 46 - IR: Interrupt request flag; : No interrupt requested; ID: Interrupt detect flag; Example 2-1 Setting the Interrupt Priority Level

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 45 Panasonic XnICL (System Interrupt) IR: Interrupt request flag 0: No interru...

Page 47 - Register

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 46 Panasonic Table 2-4 Interrupt Control Registers Register Address R/W Descri...

Page 49 - WDID : Watchdog interrupt detect flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 48 Panasonic IAGR: Accepted Interrupt Group Number Register x’00FC0E’ IAGR ret...

Page 50 - PIID : Undefined instruction interrupt detect flag; EIICR: Interrupt error Interrupt Control Register; IQ0IR: External interrupt 0 interrupt request flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 49 Panasonic PIICR: Undefined Instruction Interrupt Control Register x’00FC44’...

Page 51 - IQ0IE: External interrupt 0 interrupt enable flag; IQ1ICL: External Interrupt 1 Interrupt Control Register (Low); IQ1IR: External interrupt 1 interrupt request flag; IQ1IE: External interrupt 1 interrupt enable flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 50 Panasonic IQ0ICH: External Interrupt 0 Interrupt Control Register (High) x’...

Page 52 - IQ2IR: External interrupt 2 interrupt request flag; IQ2ICH: External Interrupt 2 Interrupt Control Register (High); IQ2IE: External interrupt 2 interrupt enable flag; IQ3ICL: External Interrupt 3 Interrupt Control Register (Low); IQ3IR: External interrupt 3 interrupt request flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 51 Panasonic IQ2ICL: External Interrupt 2 Interrupt Control Register (Low) x’0...

Page 53 - IQ3IE: External interrupt 3 interrupt enable flag; IQ4ICL: External Interrupt 4 Interrupt Control Register (Low); IQ4IR: External interrupt 4 interrupt request flag; IQ4IE: External interrupt 4 interrupt enable flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 52 Panasonic IQ3ICH: External Interrupt 3 Interrupt Control Register (High) x’...

Page 54 - IQ5IR: External interrupt 5 interrupt request flag; IQ5ICH: External Interrupt 5 Interrupt Control Register (High); IQ5IE: External interrupt 5 interrupt enable flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 53 Panasonic IQ5ICL: External Interrupt 5 Interrupt Control Register (Low) x’0...

Page 55 - TM4CBIE: Timer 4 compare/capture B interrupt enable flag; TM4CAID: Timer 4 compare/capture A interrupt detect flag; TM4CAICH enables timer 4 compare/capture interrupts. It is an 8-bit; TM4CAIE: Timer 4 compare/capture A interrupt enable flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 54 Panasonic TM4CBICH: Timer 4 Compare/Capture B Interrupt Control Register (H...

Page 56 - TM4UDIR : Timer 4 underflow interrupt request flag; TM4UDICH: Timer 4 Underflow Interrupt Control Register (High); TM4UDIE: Timer 4 underflow interrupt enable flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 55 Panasonic TM4UDICL: Timer 4 Underflow Interrupt Control Register (Low) x’00...

Page 57 - TM5CBIR : Timer 5 compare/capture B interrupt request flag; TM5CBIE: Timer 5 compare/capture B interrupt enable flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 56 Panasonic VBIICH: VBI (1) Interrupt Control Register (High) x’00FC67’ VBIIC...

Page 58 - TM5CAIR : Timer 5 compare/capture A interrupt request flag; TM5CAICH enables timer 5 compare/capture interrupts. It is an 8-bit; TM5CAIE: Timer 5 compare/capture A interrupt enable flag; TM5UDID: Timer 5 underflow interrupt detect flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 57 Panasonic TM5CAICL: Timer 5 Compare/Capture A Interrupt Control Register (L...

Page 59 - TM5UDIE: Timer 5 underflow interrupt enable flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 58 Panasonic TM5UDICH: Timer 5 Underflow Interrupt Control Register (High) x’0...

Page 60 - TM2UDIR : Timer 2 underflow interrupt request flag; TM2UDICH: Timer 2 Underflow Interrupt Control Register (High); TM2UDIE: Timer 2 underflow interrupt enable flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 59 Panasonic TM2UDICL: Timer 2 Underflow Interrupt Control Register (Low) x’00...

Page 61 - TM1UDIE: Timer 1 underflow interrupt enable flag; TM0UDIE: Timer 0 underflow interrupt enable flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 60 Panasonic TM1UDICH: Timer 1 Underflow Interrupt Control Register (High) x’0...

Page 62 - RMCIR : Remote signal receive interrupt request flag; RMCICH: Remote Signal Receive Interrupt Control Register (High); RMCIE: Remote signal receive interrupt enable flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 61 Panasonic RMCICL: Remote Signal Receive Interrupt Control Register (Low) x’...

Page 63 - ADM3IE: Address match 3 interrupt enable flag; access register. Use the MOVB instruction to access it.; ADM2IR : Address match 2 interrupt request flag; ADM2IE: Address match 2 interrupt enable flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 62 Panasonic ADM3ICH: Address 3 Match Interrupt Control Register (High) x’00FC...

Page 64 - ADM1IR : Address match 1 interrupt request flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 63 Panasonic ADM1ICL: Address 1 Match Interrupt Control Register (Low) x’00FC7...

Page 65 - ADM0IE: Address match 0 interrupt enable flag; ANIE: A/D conversion end interrupt enable flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 64 Panasonic ADM0ICH: Address 0 Match Interrupt Control Register (High) x’00FC...

Page 66 - SCT0IR : Serial 0 transmission end interrupt request flag; SCR0ICL: Serial 0 Reception End Interrupt Control Register (Low); SCT0IR : Serial 0 reception end interrupt request flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 65 Panasonic SCT0ICL: Serial 0 Transmission End Interrupt Control Register (Lo...

Page 67 - SCR0IE: Serial 0 reception end interrupt enable flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 66 Panasonic SCR0ICH: Serial 0 Reception End Interrupt Control Register (High)...

Page 68 - TM3UDIR : Timer 3 underflow interrupt request flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 67 Panasonic VBIVWICL: VBIVSYNC (2) Interrupt Control Register (Low) x’00FC8A’...

Page 69 - TM3UDIE: Timer 3 underflow interrupt enable flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 68 Panasonic TM3UDICH: Timer 3 Underflow Interrupt Control Register (High) x’0...

Page 70 - SCT1IR : Serial 1 transmission end interrupt request flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 69 Panasonic OSDCICL: OSD (Text) Interrupt Control Register (Low) x’00FC92’ OS...

Page 71 - SCT1IE: Serial 1 transmission end interrupt enable flag; SCR1ICL: Serial 1 Reception End Interrupt Control Register (Low); SCT1IR : Serial 1 reception end interrupt request flag; SCT1ID: Serial 1 reception end interrupt detect flag; SCR1ICH: Serial 1 Reception End Interrupt Control Register (High); SCR1IE: Serial 1 reception end interrupt enable flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 70 Panasonic SCT1ICH: Serial 1 Transmission End Interrupt Control Register (Hi...

Page 72 - C interrupt request flag

I n t e r r u p t s I n t e r r u p t C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 71 Panasonic I2CICL: I 2 C Interrupt Control Register (Low) x’00FC9C’ I2CICL d...

Page 73 - L o w - P o w e r M o d e s; L o w - Po w e r M o d e s; C P U M o d e s; A normal reset or an interrupt wakes the MCU from a standby mode.

L o w - P o w e r M o d e s C P U M o d e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 72 Panasonic 3 L o w - Po w e r M o d e s The MN102H75K/85K provides two ways to reduce power consumptio...

Page 74 - E x i t i n g f r o m S L OW M o d e t o N O R M A L M o d e; routine immediately after power up.

L o w - P o w e r M o d e s C P U M o d e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 73 Panasonic 3 . 1 . 2 E x i t i n g f r o m S L OW M o d e t o N O R M A L M o d e The MN102H75K/85K re...

Page 75 - N o t e s o n I nvo k i n g a n d E x i t i n g S TO P a n d H A LT M o d e s; MCU exits on reset, it always exits to SLOW mode.

L o w - P o w e r M o d e s C P U M o d e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 74 Panasonic 3 . 1 . 3 N o t e s o n I nvo k i n g a n d E x i t i n g S TO P a n d H A LT M o d e s ■ W...

Page 76 - T u r n i n g I n d i v i d u a l F u n c t i o n s O n a n d O f f; Tu r n i n g I n d i v i d u a l F u n c t i o n s O n a n d O f f

L o w - P o w e r M o d e s T u r n i n g I n d i v i d u a l F u n c t i o n s O n a n d O f f M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 75 Panasonic 3 . 2 Tu r n i n g I n d i v i d u a l ...

Page 77 - C P U C o n t r o l R e g i s t e r; This register controls the invoking of all of the CPU modes.; NWDEN: Watchdog timer reset; System clock monitor; STOP: STOP mode request; All unindicated bit settings are reserved.

L o w - P o w e r M o d e s C P U C o n t r o l R e g i s t e r P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 76 Panasonic 3 . 3 C P U C o n t r o l R e g i s t e r CPUM: CPU Mode Control Regist...

Page 78 - - B i t T i m e r D e s c r i p t i o n; - B i t T i m e r D e s c r i p t i o n; interrupt is generated by a timer underflow.; Figure 4-1 Timer Configuration Examples; Cascading Connections

T i m e r s 8 - B i t T i m e r D e s c r i p t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 77 Panasonic 4 T i m e r s 4 . 1 8 - B i t T i m e r D e s c r i p t i o n The MN102H75K/85K c...

Page 79 - - B i t T i m e r F e a t u r e s; When B

T i m e r s 8 - B i t T i m e r F e a t u r e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 78 Panasonic 4 . 2 8 - B i t T i m e r F e a t u r e s Table 4-1 8-Bit Timer Functions and Features ...

Page 80 - - B i t T i m e r B l o c k D i a g r a m s; - B i t T i m e r B l o ck D i a g r a m s; Figure 4-3 Timer 0 Block Diagram

T i m e r s 8 - B i t T i m e r B l o c k D i a g r a m s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 79 Panasonic 4 . 3 8 - B i t T i m e r B l o ck D i a g r a m s Figure 4-3 Timer 0 Block D...

Page 82 - - B i t T i m e r T i m i n g

T i m e r s 8 - B i t T i m e r T i m i n g M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 81 Panasonic 4 . 4 8 - B i t T i m e r T i m i n g Figure 4-7 Event Timer Input Timing (8-Bit Timers) Fi...

Page 83 - - B i t T i m e r S e t u p E x a m p l e s; S e t t i n g U p a n E ve n t C o u n t e r U s i n g Ti m e r 0; edge of the TM0IO signal.; signal resulting from the B; sampling of the TMnIO signal input.; Figure 4-9 Block Diagram of Event Counter Using Timer 0

T i m e r s 8 - B i t T i m e r S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 82 Panasonic 4 . 5 8 - B i t T i m e r S e t u p E x a m p l e s 4 . 5 . 1 S e t t i n g U...

Page 84 - underflow interrupt request is sent to the CPU.

T i m e r s 8 - B i t T i m e r S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 83 Panasonic TM0UDICL (example) x’00FC74’ TM0UDICH (example) x’00FC75’ 4. Set the divide-b...

Page 85 - S e t t i n g U p a n I n t e r v a l Ti m e r U s i n g Ti m e r s 1 a n d 2; In this example, timers 1 and 2 are cascaded to divide B; generate an underflow interrupt.; Timer 1

T i m e r s 8 - B i t T i m e r S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 84 Panasonic 4 . 5 . 2 S e t t i n g U p a n I n t e r v a l Ti m e r U s i n g Ti m e r s...

Page 87 - Set TM2LD to 0 and TM2EN to 1, then set TM1LD to 0 and TM1EN to 1.

T i m e r s 8 - B i t T i m e r S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 86 Panasonic TM2MD (example) x’00FE22’ In the bank and linear address- ing versions of the...

Page 88 - - B i t T i m e r C o n t r o l R e g i s t e r s; TMnEN: TMnBC count enable

T i m e r s 8 - B i t T i m e r C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 87 Panasonic 4 . 6 8 - B i t T i m e r C o n t r o l R e g i s t e r s Table 4-2 sho...

Page 89 - 6 - B i t T i m e r D e s c r i p t i o n; Figure 4-14 Block Diagram of 16-Bit Timers

T i m e r s 1 6 - B i t T i m e r D e s c r i p t i o n P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 88 Panasonic 4 . 7 1 6 - B i t T i m e r D e s c r i p t i o n The MN102H75K/85K contains tw...

Page 90 - 6 - B i t T i m e r F e a t u r e s; Table 4-3 16-Bit Timer Functions and Features

T i m e r s 1 6 - B i t T i m e r F e a t u r e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 89 Panasonic 4 . 8 1 6 - B i t T i m e r F e a t u r e s Table 4-3 16-Bit Timer Functions and Feat...

Page 91 - 6 - B i t T i m e r B l o c k D i a g r a m s; 6 - B i t T i m e r B l o ck D i a g r a m s; Figure 4-15 Timer 4 Block Diagram; TMnIOA

T i m e r s 1 6 - B i t T i m e r B l o c k D i a g r a m s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 90 Panasonic 4 . 9 1 6 - B i t T i m e r B l o ck D i a g r a m s 4 . 1 0 1 6 - B i t T ...

Page 92 - 6 - B i t T i m e r T i m i n g

T i m e r s 1 6 - B i t T i m e r T i m i n g M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 91 Panasonic Figure 4-18 Single-Phase PWM Output Timing with Data Change (16-Bit Timers) Figure 4-19 T...

Page 94 - Time

T i m e r s 1 6 - B i t T i m e r T i m i n g M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 93 Panasonic Figure 4-24 Two-Phase Capture Input Timing (16-Bit Timers) Figure 4-25 Two-Phase 4x Encod...

Page 95 - 6 - B i t T i m e r S e t u p E x a m p l e s; . 1 1 1 6 - B i t T i m e r S e t u p E x a m p l e s; . 1 1 . 1 S e t t i n g U p a n E ve n t C o u n t e r U s i n g Ti m e r 4; In this example, timer 4 counts the TM4IB input signal (B; and generates an interrupt on the second and fifth cycles.; Set the operating mode in the timer 4 mode register (TM4MD). Disable; Controller

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 94 Panasonic 4 . 1 1 1 6 - B i t T i m e r S e t u p E x a m p l e s 4 . 1 1 . 1 S e t t...

Page 97 - . 1 1 . 2 S e t t i n g U p a S i n g l e - P h a s e P W M O u t p u t S i g n a l U s i n g; In this example, timer 4 is used to divide B; To set up the output port:

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 96 Panasonic 4 . 1 1 . 2 S e t t i n g U p a S i n g l e - P h a s e P W M O u t p u t S...

Page 98 - Set the divide-by ratio for timer 4. To divide B; prevents timing errors.

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 97 Panasonic P2DIR (example) x’00FFE2’ ■ To set up timer 4: Use the MOV instruction for ...

Page 102 - . 1 1 . 3 S e t t i n g U p a Two - P h a s e P W M O u t p u t S i g n a l U s i n g

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 101 Panasonic 4 . 1 1 . 3 S e t t i n g U p a Two - P h a s e P W M O u t p u t S i g n ...

Page 103 - as B

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 102 Panasonic P2DIR (example) x’00FFE2’ ■ To set up timer 0: 1. Disable timer 0 counting...

Page 107 - . 1 1 . 4 S e t t i n g U p a S i n g l e - P h a s e C a p t u r e I n p u t U s i n g Ti m e r 4; from the contents of TMnCB.; select looped counting from 0 to x’FFFF’. Select B; Interrupt B; Timer 4

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 106 Panasonic 4 . 1 1 . 4 S e t t i n g U p a S i n g l e - P h a s e C a p t u r e I n ...

Page 108 - To enable timer 4 capture B interrupts:; Timer 4 does not operate in STOP mode, when B; is off. If you use an external

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 107 Panasonic change any other operating modes during this step. When TM4MD[1:0] = b’10’...

Page 109 - . 1 1 . 5 S e t t i n g U p a Two - P h a s e C a p t u r e I n p u t U s i n g Ti m e r 4; unnecessary immediately after a reset, since TM0MD resets to 0.; Figure 4-37 Block Diagram of Two-Phase Capture Input Using Timer 4

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 108 Panasonic 4 . 1 1 . 5 S e t t i n g U p a Two - P h a s e C a p t u r e I n p u t U ...

Page 111 - does not operate in STOP mode, when B; is off. If you use an external clock, it; read during the interrupt service routine.

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 110 Panasonic ■ To service the interrupts and calculate the signal width: 1. Run the int...

Page 112 - . 1 1 . 6 S e t t i n g U p a 4 x Two - P h a s e E n c o d e r I n p u t U s i n g Ti m e r 5; Timer 5

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 111 Panasonic 4 . 1 1 . 6 S e t t i n g U p a 4 x Two - P h a s e E n c o d e r I n p u ...

Page 113 - occurs at the beginning of the next cycle.

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 112 Panasonic ■ To set up timer 5: Use the MOV instruction for this setup and only use 1...

Page 114 - is off. If you use an external clock, it must be synchronized to; Table 4-4 Count Direction for 4x Two-Phase Encoder Timing Example

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 113 Panasonic ■ To service the interrupts: Run the interrupt service routine. The routin...

Page 115 - Setting Up a 1x Two-Phase Encoder Input U s i n g Ti m e r 5

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 114 Panasonic 4.11.7 Setting Up a 1x Two-Phase Encoder Input U s i n g Ti m e r 5 In thi...

Page 117 - Table 4-5 Count Direction for 1x Two-Phase Encoder Timing Example

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 116 Panasonic ■ To service the interrupts: Run the interrupt service routine. The routin...

Page 118 - . 1 1 . 8 S e t t i n g U p a O n e - S h o t P u l s e O u t p u t U s i n g Ti m e r 5

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 117 Panasonic 4 . 1 1 . 8 S e t t i n g U p a O n e - S h o t P u l s e O u t p u t U s ...

Page 119 - counting and interrupts. Select up counting. Select B; same as it does during two-phase PWM output.

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 118 Panasonic ■ To set up timer 5: Use the MOV instruction for this setup and only use 1...

Page 120 - is off. If you use an external clock, it must be synchronized to B

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 119 Panasonic Timer 5 can output a one-shot pulse. Timer 5 does not operate in STOP mode...

Page 121 - . 1 1 . 9 S e t t i n g U p a n E x t e r n a l C o u n t D i r e c t i o n C o n t r o l l e r; In this example, timer 5 counts B; /4 and the TM5IA pin controls the count

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 120 Panasonic 4 . 1 1 . 9 S e t t i n g U p a n E x t e r n a l C o u n t D i r e c t i ...

Page 123 - when the timer switches from down to up counting.

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 122 Panasonic ■ To service the interrupts: Run the interrupt service routine. The routin...

Page 124 - . 1 1 . 1 0 S e t t i n g U p E x t e r n a l R e s e t C o n t r o l U s i n g Ti m e r 5; Set the operating mode in the timer 5 mode register (TM5MD). Disable; Figure 4-52 Block Diagram of External Reset Control Using Timer 5

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 123 Panasonic 4 . 1 1 . 1 0 S e t t i n g U p E x t e r n a l R e s e t C o n t r o l U ...

Page 125 - Figure 4-53 shows an example timing chart.

T i m e r s 1 6 - B i t T i m e r S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 124 Panasonic TM5CA (example) x’00FE94’ 3. Set the TM5NLD bit of the TM5MD register to 1...

Page 126 - 6 - B i t T i m e r C o n t r o l R e g i s t e r s; . 1 2 1 6 - B i t T i m e r C o n t ro l R e g i s t e r s

T i m e r s 1 6 - B i t T i m e r C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 125 Panasonic 4 . 1 2 1 6 - B i t T i m e r C o n t ro l R e g i s t e r s Table 4...

Page 127 - TMnTGE: External trigger enable for start count

T i m e r s 1 6 - B i t T i m e r C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 126 Panasonic TM4MD/TM5MD: Timer n Mode Register x’00FE80’/x’00FE90’ TMnEN: TMnBC ...

Page 128 - S e r i a l I n t e r f a c e s; C modes. The maximum baud rate in synchronous; F e a t u r e s

S e r i a l I n t e r f a c e s D e s c r i p t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 127 Panasonic 5 S e r i a l I n t e r f a c e s 5 . 1 D e s c r i p t i o n The MN102H75K/85K ...

Page 129 - C o n n e c t i n g t h e S e r i a l I n t e r f a c e s; S y n ch r o n o u s S e r i a l M o d e C o n n e c t i o n s; chronous serial transfers.; UA RT M o d e C o n n e c t i o n s; The serial interfaces can connect to I; . Either connect a pullup; A. Simplex Connection; A. Simplex Connection; Figure 5-3 UART Mode Connections; Transmit; SBO; Slave

S e r i a l I n t e r f a c e s C o n n e c t i n g t h e S e r i a l I n t e r f a c e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 128 Panasonic 5 . 3 C o n n e c t i n g t h e S e r i a l ...

Page 130 - U A R T M o d e B a u d R a t e s; UA R T M o d e B a u d R a t e s; S e r i a l I n t e r f a c e T i m i n g; S y n ch r o n o u s S e r i a l M o d e Ti m i n g; Table 5-2 Example Baud Rate Settings for the UART Mode

S e r i a l I n t e r f a c e s U A R T M o d e B a u d R a t e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 129 Panasonic 5 . 4 UA R T M o d e B a u d R a t e s In UART mode, the serial inte...

Page 131 - UA RT M o d e Ti m i n g; Figure 5-6 Synchronous Serial Reception Timing

S e r i a l I n t e r f a c e s S e r i a l I n t e r f a c e T i m i n g P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 130 Panasonic 5 . 5 . 2 UA RT M o d e Ti m i n g In these timing charts, t...

Page 132 - S e r i a l I n t e r f a c e S e t u p E x a m p l e s; S e t t i n g U p UA RT Tr a n s m i s s i o n U s i n g S e r i a l I n t e r f a c e 0; -bit character length

S e r i a l I n t e r f a c e s S e r i a l I n t e r f a c e S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 131 Panasonic 5 . 6 S e r i a l I n t e r f a c e S e t u p ...

Page 136 - S e t t i n g U p t h e S e r i a l I n t e r f a c e C l o ck; UART interface by using timer 1 to divide B; Transfer clock = baud rate x 8; This means that the timer 1 underflow must be divided by 39.; Figure 5-11 Block Diagram of Serial Interface Clock

S e r i a l I n t e r f a c e s S e r i a l I n t e r f a c e S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 135 Panasonic 5 . 6 . 3 S e t t i n g U p t h e S e r i a l ...

Page 137 - Figure 5-12 shows an example timing chart.; Figure 5-12 Serial Interface Clock Timing

S e r i a l I n t e r f a c e s S e r i a l I n t e r f a c e S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 136 Panasonic Do not change the clock source once you select...

Page 138 - S e t t i n g U p I; timer 0 underflow rate divided by 8 as the clock source.; output. The SBO0 pin begins data output to the I

S e r i a l I n t e r f a c e s S e r i a l I n t e r f a c e S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 137 Panasonic 5 . 6 . 4 S e t t i n g U p I 2 C Tr a n s m i...

Page 139 - Figure 5-13 shows an example timing chart.

S e r i a l I n t e r f a c e s S e r i a l I n t e r f a c e S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 138 Panasonic Reception must be enabled for the circuit to d...

Page 140 - To set up the I; To set up data reception:

S e r i a l I n t e r f a c e s S e r i a l I n t e r f a c e S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 139 Panasonic 5 . 6 . 5 S e t t i n g U p I 2 C R e c e p t ...

Page 141 - S e r i a l I n t e r f a c e C o n t r o l R e g i s t e r s; S e r i a l I n t e r f a c e C o n t ro l R e g i s t e r s; Do not change this bit during transmission or reception.

S e r i a l I n t e r f a c e s S e r i a l I n t e r f a c e C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 140 Panasonic 5 . 7 S e r i a l I n t e r f a c e C o ...

Page 142 - SCnICM: Serial por t n I

S e r i a l I n t e r f a c e s S e r i a l I n t e r f a c e C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 141 Panasonic SCnICM: Serial por t n I 2 C mode select...

Page 144 - A n a l o g - t o - D i g i t a l C o n v e r t e r; A n a l o g - t o - D i g i t a l C o nv e r t e r; is 24 MHz, you must set the reference clock to; Figure 6-1 ADC Architecture; Sample; Table 6-1 ADC Functions and Features

A n a l o g - t o - D i g i t a l C o n v e r t e r D e s c r i p t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 143 Panasonic 6 A n a l o g - t o - D i g i t a l C o nv e r t e r 6 . 1 D...

Page 145 - S e l e c t i n g t h e A D C C l o ck S o u r c e; Calculate the A/D conversion time as follows:; For example, if you set the clock source to B; Figure 6-2 ADC Block Diagram

A n a l o g - t o - D i g i t a l C o n v e r t e r B l o c k D i a g r a m P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 144 Panasonic 6 . 3 B l o ck D i a g r a m 6 . 4 A / D C o nv e r s i o ...

Page 146 - A / D C o n v e r s i o n T i m i n g; S i n g l e C h a n n e l / S i n g l e C o nve r s i o n Ti m i n g; version, then clears to 0 when the conversion ends.; M u l t i p l e C h a n n e l / S i n g l e C o nve r s i o n Ti m i n g; Figure 6-4 Single Channel/Single Conversion Timing

A n a l o g - t o - D i g i t a l C o n v e r t e r A / D C o n v e r s i o n T i m i n g M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 145 Panasonic 6 . 4 . 2 S i n g l e C h a n n e l / S i n ...

Page 147 - S i n g l e C h a n n e l / C o n t i n u o u s C o nve r s i o n Ti m i n g; Figure 6-6 Single Channel/Continuous Conversion Timing

A n a l o g - t o - D i g i t a l C o n v e r t e r A / D C o n v e r s i o n T i m i n g P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 146 Panasonic 6 . 4 . 4 S i n g l e C h a n n e l / C o n ...

Page 148 - A D C S e t u p E x a m p l e s; To set up the input port:

A n a l o g - t o - D i g i t a l C o n v e r t e r A D C S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 147 Panasonic 6 . 5 A D C S e t u p E x a m p l e s 6.5.1 Settin...

Page 149 - A/D converter data registers

A n a l o g - t o - D i g i t a l C o n v e r t e r A D C S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 148 Panasonic AN6BUF (example) x’00FF14’ 6.5.2 Setting Up Hardwa...

Page 150 - To set up the conversion cycle; Set the TM1LD bit of the TM1MD register to 1 and the TM1EN bit to 0.

A n a l o g - t o - D i g i t a l C o n v e r t e r A D C S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 149 Panasonic ■ To set up the input port: Set the P0DIR[5:3] bit...

Page 151 - A D C C o n t r o l R e g i s t e r s; A D C C o n t ro l R e g i s t e r s

A n a l o g - t o - D i g i t a l C o n v e r t e r A D C C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 150 Panasonic 6 . 6 A D C C o n t ro l R e g i s t e r s T...

Page 152 - ANTC: Conversion start at timer 1 underflow; Always set this bit to 0.; 1: Multiple channels, continuous conversion

A n a l o g - t o - D i g i t a l C o n v e r t e r A D C C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 151 Panasonic ANCTR: ADC Control Register x’00FF00’ ANNCH[...

Page 153 - C a u t i o n s a b o u t A n a l o g - t o - D i g i t a l C o n v e r t e r; C a u t i o n s a b o u t A n a l o g - t o - D i g i t a l C o nv e r t e r; accurancy of convension:; or

A n a l o g - t o - D i g i t a l C o n v e r t e r C a u t i o n s a b o u t A n a l o g - t o - D i g i t a l C o n v e r t e r P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 152 Panasonic 6 . ...

Page 154 - O n - S c r e e n D i s p l a y; This allows you to adjust the memory space to fit your application.; Table 7-1 OSD Functions and Features

O n - S c r e e n D i s p l a y D e s c r i p t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 153 Panasonic 7 O n - S c r e e n D i s p l a y If you use the OSD function, the DMA function ...

Page 155 - Figu

O n - S c r e e n D i s p l a y B l o c k D i a g r a m P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 154 Panasonic 7 . 3 B l o ck D i a g r a m Figu re 7-1 O S D Bloc k Dia g ra m VSYNC Vertica...

Page 156 - P o w e r - S a v i n g C o n s i d e r a t i o n s i n t h e O S D B l o c k; This section explains how to use these bits.

O n - S c r e e n D i s p l a y P o w e r - S a v i n g C o n s i d e r a t i o n s i n t h e O S D B l o c k M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 155 Panasonic 7 . 4 Po w e r - S a v i...

Page 157 - O S D O p e r a t i o n; section 7 provides more detailed specifications.; O S D C l o ck; OSC clock source; E x t e r n a l I n p u t S y n c S i g n a l s; that you must these parameters separately.; M u l t i - L a y e r Fo r m a t; Text layer

O n - S c r e e n D i s p l a y O S D O p e r a t i o n P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 156 Panasonic 7 . 5 O S D O p e r a t i o n This section describes the basic operation of th...

Page 158 - O u t p u t P i n S e t u p

O n - S c r e e n D i s p l a y O S D O p e r a t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 157 Panasonic ■ Graphics layer The graphics layer contains tiled images. In the 16-color mod...

Page 159 - C o n d i t i o n s fo r V R A M W r i t e s; that order, at the end of the preceding line.

O n - S c r e e n D i s p l a y O S D O p e r a t i o n P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 158 Panasonic 7 . 5 . 7 C o n d i t i o n s fo r V R A M W r i t e s ■ Text layer Set CHP, C...

Page 160 - S t a n d a r d a n d E x t e n d e d D i s p l a y M o d e s; S t a n d a r d a n d E x t e n d e d D i s p l ay M o d e s; C u r s o r L a y e r D i s p l a y M o d e s; Figure 7-2 Cursor Tiles in Standard and Extended Modes

O n - S c r e e n D i s p l a y S t a n d a r d a n d E x t e n d e d D i s p l a y M o d e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 159 Panasonic 7 . 6 S t a n d a r d a n d E x t e n d ...

Page 161 - G r a p h i c s L a y e r D i s p l a y M o d e s

O n - S c r e e n D i s p l a y S t a n d a r d a n d E x t e n d e d D i s p l a y M o d e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 160 Panasonic In standard mode, STC0 is the only curso...

Page 162 - D i s p l a y S e t u p E x a m p l e s; D i s p l ay S e t u p E x a m p l e s; S e t t i n g U p t h e G r a p h i c s L a y e r; Register settings

O n - S c r e e n D i s p l a y D i s p l a y S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 161 Panasonic 7 . 7 D i s p l ay S e t u p E x a m p l e s 7 . 7 . 1 S e t t...

Page 164 - S e t t i n g U p t h e Te x t L a y e r; This section shows how to set up the text display data in the VRAM.; A CC code must immediately follow a COL code.

O n - S c r e e n D i s p l a y D i s p l a y S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 163 Panasonic 7 . 7 . 2 S e t t i n g U p t h e Te x t L a y e r This sectio...

Page 165 - Figure 7-5 Text Display Example; Display end

O n - S c r e e n D i s p l a y D i s p l a y S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 164 Panasonic The text display starts one dot to the right of the HP setting...

Page 166 - V R A M; V R A M O p e r a t i o n; Specifies the address of one of 1024 characters stored in the ROM.; CSHAD; Specifies character shadowing for a 3D effect.; FRAME; Table 7-7 VRAM Bit Allocation in Internal RAM

O n - S c r e e n D i s p l a y V R A M M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 165 Panasonic 7 . 8 V R A M 7 . 8 . 1 V R A M O p e r a t i o n ■ Text LayerCC: Character Code ID Code: 00 C...

Page 168 - CSHT; CVP: Character Vertical Position Control Code; CLAST; Specifies the V size of the characters on the next line.; CINT; Specifies an OSD interrupt.; GCBF

O n - S c r e e n D i s p l a y V R A M M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 167 Panasonic CHP: Character Horizontal Position Control Code ID Code: 11 CHSZ[1:0] Specifies the H size of ...

Page 169 - GPRT; Specifies graphics color palette 1 or 2.; GSHT; GVP: Graphics Vertical Position Control Code; GLAST; Specifies the V size of the tiles on the next line.; GINT

O n - S c r e e n D i s p l a y V R A M P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 168 Panasonic GCB[3:0] Specifies the number of times (up to 16) a blank or graphic tile is repeated. GPRT Sp...

Page 170 - V R A M O r g a n i z a t i o n; Graphics RAM Addresses; Text RAM Addresses

O n - S c r e e n D i s p l a y V R A M M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 169 Panasonic 7 . 8 . 2 V R A M O r g a n i z a t i o n Notes: 1. All addresses are expressed in hex notatio...

Page 172 - C a u t i o n s a b o u t t h e n u m b e r o f d i s p l a y c o d e s e t t o V R A M; the display data of the next line.

O n - S c r e e n D i s p l a y V R A M M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 171 Panasonic 7 . 8 . 3 C a u t i o n s a b o u t t h e n u m b e r o f d i s p l a y c o d e s e t t o V R ...

Page 173 - R O M; RO M O r g a n i z a t i o n; Figure 7-9 ROM Organization; Text ROM Addresses; Text character; Graphics ROM Addresses; Graphics

O n - S c r e e n D i s p l a y R O M P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 172 Panasonic 7 . 9 R O M 7 . 9 . 1 RO M O r g a n i z a t i o n Notes: 1. All addresses are expressed in hex ...

Page 174 - Graphics ROM Organization in Different Color Modes; zation for each color mode.

O n - S c r e e n D i s p l a y R O M M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 173 Panasonic 7.9.2 Graphics ROM Organization in Different Color Modes The graphics layer supports up to sixte...

Page 175 - Graphic Tile Codes; colors

O n - S c r e e n D i s p l a y R O M P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 174 Panasonic Figure 7-11 Graphics ROM in the Four Color Modes (16W x 16H Tiles) ROMEND − 80 × N + 1 ROMEND − ...

Page 179 - S e t t i n g U p t h e O S D; . 1 0 S e t t i n g U p t h e O S D; . 1 0 . 1 S e t t i n g U p t h e O S D D i s p l a y C o l o r s; This section describes how to set up the display colors for the OSD.; GPRT (GTC bit 9 in the RAM data) selects tile color palette 1 or 2.

O n - S c r e e n D i s p l a y S e t t i n g U p t h e O S D P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 178 Panasonic 7 . 1 0 S e t t i n g U p t h e O S D 7 . 1 0 . 1 S e t t i n g U p t h ...

Page 180 - FRAME (COL bit 9 in the RAM data) enables character outlining when; This function is unavailable in the closed-caption mode.; BBSHD (x’007FA4’) specifies the “black” color for box shadowing.; To set up functions applying to all layers:

O n - S c r e e n D i s p l a y S e t t i n g U p t h e O S D M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 179 Panasonic ■ To set up the text display colors: Write to the fields described below...

Page 181 - : Output color 15 as specified

O n - S c r e e n D i s p l a y S e t t i n g U p t h e O S D P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 180 Panasonic Translucency Selecting YS palette output, by setting the YSPLT bit of OS...

Page 184 - Int ernal DAC; YM; To pins

O n - S c r e e n D i s p l a y S e t t i n g U p t h e O S D M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 183 Panasonic Figure 7-22 OSD Signal Output Switches *** YM3 Bit 15 *** R1 1 *** R2 2 ...

Page 185 - . 1 0 . 2 Te x t L a y e r F u n c t i o n s; Outlining

O n - S c r e e n D i s p l a y S e t t i n g U p t h e O S D P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 184 Panasonic 7 . 1 0 . 2 Te x t L a y e r F u n c t i o n s This section describes th...

Page 187 - Italics

O n - S c r e e n D i s p l a y S e t t i n g U p t h e O S D P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 186 Panasonic ■ Italicizing In closed-caption mode, writing a 1 to bit 10 (ITALIC) of ...

Page 190 - . 1 0 . 4 S e t t i n g U p t h e O S D D i s p l a y Po s i t i o n; To set up the horizontal position:; About the horizontal start position on the screen; of Horizontal Display Position

O n - S c r e e n D i s p l a y S e t t i n g U p t h e O S D M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 189 Panasonic 7 . 1 0 . 4 S e t t i n g U p t h e O S D D i s p l a y Po s i t i o n T...

Page 192 - D M A a n d I n t e r r u p t T i m i n g; . 1 1 D M A a n d I n t e r r u p t T i m i n g; DMA; ) after the leading edge of the HSYNC pulse.

O n - S c r e e n D i s p l a y D M A a n d I n t e r r u p t T i m i n g M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 191 Panasonic 7 . 1 1 D M A a n d I n t e r r u p t T i m i n g This secti...

Page 194 - S e l e c t i n g t h e O S D D o t C l o c k; . 1 2 S e l e c t i n g t h e O S D D o t C l o c k; This section describes how to set up the OSD dot clock.

O n - S c r e e n D i s p l a y S e l e c t i n g t h e O S D D o t C l o c k M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 193 Panasonic 7 . 1 2 S e l e c t i n g t h e O S D D o t C l o c k Th...

Page 195 - C o n t r o l l i n g t h e S h u t t e r i n g E f f e c t; . 1 3 C o n t r o l l i n g t h e S h u t t e r i n g E f f e c t; The MN102H75K/85K OSD achieves a shuttering effect using four pro-; . 1 3 . 1 C o n t r o l l i n g t h e S h u t t e r e d A r e a; Determining the vertical shutter positions (VST0 and VST1)

O n - S c r e e n D i s p l a y C o n t r o l l i n g t h e S h u t t e r i n g E f f e c t P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 194 Panasonic 7 . 1 3 C o n t r o l l i n g t h e S h u ...

Page 197 - . 1 3 . 2 C o n t r o l l i n g S h u t t e r M ove m e n t; must reset the bits each time.

O n - S c r e e n D i s p l a y C o n t r o l l i n g t h e S h u t t e r i n g E f f e c t P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 196 Panasonic 7 . 1 3 . 2 C o n t r o l l i n g S h u t ...

Page 198 - ABCDE

O n - S c r e e n D i s p l a y C o n t r o l l i n g t h e S h u t t e r i n g E f f e c t M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 197 Panasonic Figure 7-32 Shutter Movement Setup Example...

Page 199 - . 1 3 . 3 C o n t r o l l i n g S h u t t e r i n g E ff e c t s; You cannot shutter the cursor layer.; Function

O n - S c r e e n D i s p l a y C o n t r o l l i n g t h e S h u t t e r i n g E f f e c t P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 198 Panasonic 7 . 1 3 . 3 C o n t r o l l i n g S h u t ...

Page 200 - CDE

O n - S c r e e n D i s p l a y C o n t r o l l i n g t h e S h u t t e r i n g E f f e c t M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 199 Panasonic ■ To shutter the color background: Set the...

Page 201 - . 1 3 . 4 C o n t r o l l i n g L i n e S h u t t e r i n g; To disable shuttering on the next line:; Figure 7-35 Line Shuttering Setup Example; ABCDEFG

O n - S c r e e n D i s p l a y C o n t r o l l i n g t h e S h u t t e r i n g E f f e c t P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 200 Panasonic 7 . 1 3 . 4 C o n t r o l l i n g L i n e ...

Page 202 - F i e l d D e t e c t i o n C i r c u i t; . 1 4 F i e l d D e t e c t i o n C i rc u i t; Figure 7-36 Field Detection Circuit Block Diagram

O n - S c r e e n D i s p l a y F i e l d D e t e c t i o n C i r c u i t M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 201 Panasonic 7 . 1 4 F i e l d D e t e c t i o n C i rc u i t 7 . 1 4 . 1...

Page 203 - . 1 4 . 3 C o n s i d e r a t i o n s fo r I n t e r l a c e d D i s p l a y s; following two bits to have the display start at field 2.

O n - S c r e e n D i s p l a y F i e l d D e t e c t i o n C i r c u i t P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 202 Panasonic 7 . 1 4 . 3 C o n s i d e r a t i o n s fo r I n t e r l a c...

Page 204 - O S D R e g i s t e r s; . 1 5 O S D R e g i s t e r s; CROMEND: Text ROM End Address Register

O n - S c r e e n D i s p l a y O S D R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 203 Panasonic 7 . 1 5 O S D R e g i s t e r s All registers in OSD block cannot be written b...

Page 205 - SPRT0: Cursor 0 color palette select; SPRT1: Cursor 1 color palette select; Use the same ROM data as that used for the graphics.; SPRT2: Cursor 2 color palette select; Use the same ROM data as that used for the graphics.

O n - S c r e e n D i s p l a y O S D R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 204 Panasonic is x’900F’ to x’9FFF’, with a programmable range from x’00’ to x’FF’. STC0: Cu...

Page 206 - : Graphics color palette 1

O n - S c r e e n D i s p l a y O S D R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 205 Panasonic STC3: Cursor Tile Code Register 3 x’007E2E’ SPRT3: Cursor 3 color palette sele...

Page 207 - : Shutter control on; CISHT: Graphics initial shutter control

O n - S c r e e n D i s p l a y O S D R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 206 Panasonic 00: 1 dot = 1 VCLK period 01: 1 dot = 2 VCLK periods10: 1 dot = 3 VCLK periods...

Page 210 - SPEXT: Cursor extended mode select; Specifies translucency for color 15 in all palettes.; COLB: Color background control

O n - S c r e e n D i s p l a y O S D R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 209 Panasonic OSD2: OSD Register 2 x’007F08’ SPEXT: Cursor extended mode select 0: Standard ...

Page 213 - SHTC: Shutter Control Register

O n - S c r e e n D i s p l a y O S D R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 212 Panasonic HSHT1: Horizontal Shutter 1 Register x’007F26’ HSON: Horizontal shutter 1 on/o...

Page 217 - I R R e m o t e S i g n a l R e c e i v e r; block in the circuit and describes the operation of the receiver.; is formed by dividing PWM3 by the value

I R R e m o t e S i g n a l R e c e i v e r D e s c r i p t i o n P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 216 Panasonic 8 I R R e m o t e S i g n a l R e c e i v e r 8 . 1 D e s c r i p t ...

Page 219 - I R R e m o t e S i g n a l R e c e i v e r O p e r a t i o n; O p e r a t i n g M o d e s; interrupt status register, RMIS, monitors the operating mode.; N o i s e Fi l t e r; Figure 8-2 IR Remote Signal Noise Filtering

I R R e m o t e S i g n a l R e c e i v e r I R R e m o t e S i g n a l R e c e i v e r O p e r a t i o n P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 218 Panasonic 8 . 3 I R R e m o t e S i g ...

Page 220 - - B i t D a t a R e c e p t i o n; Figure 8-3 Reception of 8-Bit Data with No Leader

I R R e m o t e S i g n a l R e c e i v e r I R R e m o t e S i g n a l R e c e i v e r O p e r a t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 219 Panasonic 8 . 3 . 3 8 - B i t D a t a ...

Page 221 - I d e n t i f y i n g t h e D a t a Fo r m a t

I R R e m o t e S i g n a l R e c e i v e r I R R e m o t e S i g n a l R e c e i v e r O p e r a t i o n P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 220 Panasonic 8 . 3 . 4 I d e n t i f y i ...

Page 222 - G e n e r a t i n g I n t e r r u p t s; . Bits 3 to 0 of the RMIR register control the interrupt; Figure 8-6 Pin Edge Detection; RMIN input; Edge detection output

I R R e m o t e S i g n a l R e c e i v e r I R R e m o t e S i g n a l R e c e i v e r O p e r a t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 221 Panasonic 8 . 3 . 5 G e n e r a t i n ...

Page 223 - C o n t r o l l i n g t h e S L OW Mo d e

I R R e m o t e S i g n a l R e c e i v e r I R R e m o t e S i g n a l R e c e i v e r O p e r a t i o n P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 222 Panasonic 8 . 3 . 6 C o n t r o l l i ...

Page 224 - I R R e m o t e S i g n a l R e c e i v e r C o n t r o l R e g i s t e r s; is f; divided by 2

I R R e m o t e S i g n a l R e c e i v e r I R R e m o t e S i g n a l R e c e i v e r C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 223 Panasonic 8 . 4 I R R e ...

Page 227 - SP and SPSLW: Switch clock frequencies; This 4-bit setting must be between 0 and 60 T; LONGDF: Long data format detection; Set to 1 when long data is detected.; SHORTDF: Short data format detection; Set to 1 when short data is detected.

I R R e m o t e S i g n a l R e c e i v e r I R R e m o t e S i g n a l R e c e i v e r C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 226 Panasonic RMLD: Remote S...

Page 228 - C l o s e d - C a p t i o n D e c o d e r; Table 9-1 Pins Used for CCD0 and CCD1

C l o s e d - C a p t i o n D e c o d e r D e s c r i p t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 227 Panasonic 9 C l o s e d - C a p t i o n D e c o d e r 9 . 1 D e s c r i p t i o ...

Page 229 - F u n c t i o n a l D e s c r i p t i o n; A n a l o g - t o - D i g i t a l C o nve r t e r; Figure 9-2 Recommended ADC Configuration; VREFHS

C l o s e d - C a p t i o n D e c o d e r F u n c t i o n a l D e s c r i p t i o n P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 228 Panasonic 9 . 3 F u n c t i o n a l D e s c r i p t i o n 9 ...

Page 230 - C l a m p i n g C i r c u i t

C l o s e d - C a p t i o n D e c o d e r F u n c t i o n a l D e s c r i p t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 229 Panasonic 9 . 3 . 2 C l a m p i n g C i r c u i t This block...

Page 231 - See the page number indicated for register and bit descriptions.; S y n c S e p a r a t o r C i r c u i t; Register for selecting the low-pass filter

C l o s e d - C a p t i o n D e c o d e r F u n c t i o n a l D e s c r i p t i o n P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 230 Panasonic Table 9-5 provides the registers used to control a...

Page 234 - D a t a S l i c e r; Figure 9-8 VSYNC Masking

C l o s e d - C a p t i o n D e c o d e r F u n c t i o n a l D e s c r i p t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 233 Panasonic 9 . 3 . 3 . 2 V S Y N C S e p a r a t o rThe VSYNC...

Page 235 - the page number indicated for register and bit descriptions.; C o n t r o l l e r a n d S a m p l i n g C i r c u i t; Registers for detecting CRI and generating sampling clock

C l o s e d - C a p t i o n D e c o d e r F u n c t i o n a l D e s c r i p t i o n P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 234 Panasonic Table 9-7 provides the registers used to control a...

Page 237 - C l o s e d - C a p t i o n D e c o d e r R e g i s t e r s

C l o s e d - C a p t i o n D e c o d e r C l o s e d - C a p t i o n D e c o d e r R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 236 Panasonic 9 . 4 C l o s e d - C a p t i o ...

Page 238 - FCCNT: VBI Decoding Format Select Register; FCPSEL: Hard/soft sampling start position select; When this field is unused, tie it to b’00’.; SLPULSEL: Polarity select for the CRI cycle transition detection; : CRI capture interval only; NCRIGSEL: Sampling pulse generation interval

C l o s e d - C a p t i o n D e c o d e r C l o s e d - C a p t i o n D e c o d e r R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 237 Panasonic For designs using the closed-cap...

Page 240 - SBFLAG: Start bit detection flag; ACQ1: ACQ Capture Timing Control Register 1

C l o s e d - C a p t i o n D e c o d e r C l o s e d - C a p t i o n D e c o d e r R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 239 Panasonic HNUM: HSYNC Count Register x’007...

Page 243 - MING: Output select for noise filter detecting minimum sync tip

C l o s e d - C a p t i o n D e c o d e r C l o s e d - C a p t i o n D e c o d e r R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 242 Panasonic DATAE: Data Capture Stop Timing ...

Page 246 - SAFE: Clamping current source select; Figure 9-15 BSP and PSP Multiplexing

C l o s e d - C a p t i o n D e c o d e r C l o s e d - C a p t i o n D e c o d e r R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 245 Panasonic BSP[5:0]: Sync separator level f...

Page 247 - ODDEVEN: Field detection signal; HLOCKLV: Sync Separator Detection Control Register 1

C l o s e d - C a p t i o n D e c o d e r C l o s e d - C a p t i o n D e c o d e r R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 246 Panasonic HSEP1: HSYNC Separator Control R...

Page 250 - P u l s e W i d t h M o d u l a t o r; 0 P u l s e W i d t h M o d u l a t o r; 0 . 1 D e s c r i p t i o n; with a minimum pulse width of 16/f; Output Wave

P u l s e W i d t h M o d u l a t o r D e s c r i p t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 249 Panasonic 1 0 P u l s e W i d t h M o d u l a t o r 1 0 . 1 D e s c r i p t i o n Fo...

Page 251 - 0 . 2 B l o ck D i a g r a m; , and they set to 1 when PWM output is high.; Output pulse cycle = 2; Figure 10-2 PWM Block Diagram

P u l s e W i d t h M o d u l a t o r B l o c k D i a g r a m P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 250 Panasonic Not using internal pullup func-tion,Figuer10-2 connect the external pull...

Page 252 - 1 . 1 D e s c r i p t i o n

I / O P o r t s D e s c r i p t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 251 Panasonic 1 1 I / O Po r t s 1 1 . 1 D e s c r i p t i o n The MN102H75K/85K contains 50 pins that form ge...

Page 253 - 1 . 2 I / O Po r t C i r c u i t D i a g r a m s

I / O P o r t s I / O P o r t C i r c u i t D i a g r a m s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 252 Panasonic 1 1 . 2 I / O Po r t C i r c u i t D i a g r a m s Figure 11-1 P00/RMIN/IR...

Page 259 - To use as SBT1,set P2MD8 and P2MD9 to 0.

I / O P o r t s I / O P o r t C i r c u i t D i a g r a m s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 258 Panasonic Figure 11-7 P24/TM4IC/SBT1 (Port 2) P2PUP4 0: Pullup off1: Pullup on 00: P...

Page 278 - 1 . 3 I / O Po r t C o n t ro l R e g i s t e r s; : Pullup resistor off

I / O P o r t s I / O P o r t C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 277 Panasonic 1 1 . 3 I / O Po r t C o n t ro l R e g i s t e r s Do not activate the ...

Page 279 - P0IN – P5IN: Ports 0–5 Input Registers; P0DIR – P5DIR: Ports 0–5 I/O Control Registers

I / O P o r t s I / O P o r t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 278 Panasonic P0IN – P5IN: Ports 0–5 Input Registers x’00FFD0’ – x’00FFD5’ P7IN – P8IN...

Page 281 - P1MD: Port 1 Output Mode Register

I / O P o r t s I / O P o r t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 280 Panasonic P1MD: Port 1 Output Mode Register x’00FFF2’ P1MD is a 16-bit access regi...

Page 283 - P3MD: Port 3 Output Mode Register; This bit exists, but contains no function.

I / O P o r t s I / O P o r t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 282 Panasonic P3MD: Port 3 Output Mode Register x’00FFF6’ P3MD is an 8-bit access regi...

Page 285 - P5MD: Port 5 Output Mode Register

I / O P o r t s I / O P o r t C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 284 Panasonic P5MD: Port 5 Output Mode Register x’00FFFA’ P5MD is an 8-bit access regi...

Page 286 - ODASCI1: Serial port 1 output switch

I / O P o r t s I / O P o r t C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 285 Panasonic PCNT0: Por t Control Register 0 x’00FF90’ PCNT0 is a 16-bit access regis...

Page 288 - P7P8CNT: Por ts 7 and 8 forced pullup; Ports 7 and 8 are only available in the quad flat package.; C function enable; ply to the associated block, which reduces power dissipation.

I / O P o r t s I / O P o r t C o n t r o l R e g i s t e r s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 287 Panasonic PCNT2: Por t Control Register 2 x’00FF92’ Always set bits 7 to 3 of PCNT...

Page 289 - R O M C o r r e c t i o n; 2 RO M C o r r e c t i o n; 2 . 1 D e s c r i p t i o n; designated addresses.; CPU; Start

R O M C o r r e c t i o n D e s c r i p t i o n P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 288 Panasonic 1 2 RO M C o r r e c t i o n 1 2 . 1 D e s c r i p t i o n The ROM correction function...

Page 290 - 2 . 2 B l o ck D i a g r a m; Figure 12-3 ROM Correction Block Diagram

R O M C o r r e c t i o n B l o c k D i a g r a m M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 289 Panasonic 1 2 . 2 B l o ck D i a g r a m Figure 12-3 is a block diagram of the ROM correction ...

Page 291 - R O M C o r r e c t i o n C o n t r o l R e g i s t e r s; 2 . 4 R O M C o r r e c t i o n C o n t r o l R e g i s t e r s; ROMCEN15: Address 15 ROM correction enable

R O M C o r r e c t i o n R O M C o r r e c t i o n C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 290 Panasonic 1 2 . 4 R O M C o r r e c t i o n C o n t r o l R ...

Page 294 - C B u s C o n t r o l l e r; 3 . 1 D e s c r i p t i o n; C bus controller, fully compliant with the

I 2 C B u s C o n t r o l l e r D e s c r i p t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 293 Panasonic 1 3 I 2 C B u s C o n t r o l l e r 1 3 . 1 D e s c r i p t i o n The MN102H75K/...

Page 295 - Figure 13-2 shows an example of an I

I 2 C B u s C o n t r o l l e r D e s c r i p t i o n P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 294 Panasonic Figure 13-2 shows an example of an I 2 C bus configuration using two microcon- t...

Page 296 - A. Master Transmitter; C Bus Interface Operation

I 2 C B u s C o n t r o l l e r D e s c r i p t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 295 Panasonic Figure 13-3 shows the MN102H75K/85K operation sequence in each of these modes. I...

Page 297 - 3 . 2 B l o ck D i a g r a m; The I; C sequence controller

I 2 C B u s C o n t r o l l e r B l o c k D i a g r a m P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 296 Panasonic 1 3 . 2 B l o ck D i a g r a m 1 3 . 3 F u n c t i o n a l D e s c r i p t i o...

Page 299 - S e t t i n g U p t h e I; 3 . 4 S e t t i n g U p t h e I; Circuit

I 2 C B u s C o n t r o l l e r S e t t i n g U p t h e I 2 C B u s C o n n e c t i o n P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 298 Panasonic 1 3 . 4 S e t t i n g U p t h e I 2 C B u s C ...

Page 300 - S D A a n d S C L W a v e f o r m C h a r a c t e r i s t i c s; 3 . 5 S DA a n d S C L Wav e f o r m C h a r a c t e r i s t i c s

I 2 C B u s C o n t r o l l e r S D A a n d S C L W a v e f o r m C h a r a c t e r i s t i c s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 299 Panasonic 1 3 . 5 S DA a n d S C L Wav e f o r m...

Page 301 - C I n t e r f a c e S e t u p E x a m p l e s; 3 . 6 . 1 S e t t i n g U p a Tr a n s i t i o n f r o m M a s t e r Tr a n s m i t t e r t o M a s -; To enable I

I 2 C B u s C o n t r o l l e r I 2 C I n t e r f a c e S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 300 Panasonic 1 3 . 6 I 2 C I n t e r f a c e S e t u p E x a m p ...

Page 302 - The circled areas are signals output from the MN102H75K/85K.

I 2 C B u s C o n t r o l l e r I 2 C I n t e r f a c e S e t u p E x a m p l e s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 301 Panasonic 1 3 . 6 . 1 . 3 S e t t i n g U p t h e S e c o n d ...

Page 303 - 3 . 6 . 2 S e t t i n g U p a Tr a n s i t i o n f r o m S l a ve R e c e i ve r t o S l a ve

I 2 C B u s C o n t r o l l e r I 2 C I n t e r f a c e S e t u p E x a m p l e s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 302 Panasonic 1 3 . 6 . 2 S e t t i n g U p a Tr a n s i t i o n f...

Page 305 - C B u s I n t e r f a c e R e g i s t e r s; All registers in I; C Transmission Data Register; ferent start and stop conditions.; ACK: Acknowledge signal output control; C bus. It is shifted out MSB first to the interface.

I 2 C B u s C o n t r o l l e r I 2 C B u s I n t e r f a c e R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 304 Panasonic 1 3 . 7 I 2 C B u s I n t e r f a c e R e g i s t e r ...

Page 307 - C Clock Control Register; In this case, the following settings apply:; C Bus Reset Register; C bus. This function works in all I; C Bus Status Register; SCLS: SCL clock line status; This bit monitors the state of the I

I 2 C B u s C o n t r o l l e r I 2 C B u s I n t e r f a c e R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 306 Panasonic I2CCLK: I 2 C Clock Control Register x’007E46’ To conf...

Page 308 - H C o u n t e r; 4 H C o u n t e r; 4 . 1 D e s c r i p t i o n; Figure 14-1 H Counter Block Diagram; In this example, HI0 is active high and VSYNC is active low.; Figure 14-2 H Counter Operation Example

H C o u n t e r D e s c r i p t i o n M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 307 Panasonic 1 4 H C o u n t e r 1 4 . 1 D e s c r i p t i o n The MN102H75K/85K contains two H counter circu...

Page 309 - H C o u n t e r O p e r a t i o n; input a count source signal in less than 245 ns (t

H C o u n t e r H C o u n t e r O p e r a t i o n P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 308 Panasonic Figure 14-3 shows the input timing for the count source and reset signals. Never inp...

Page 311 - H C o u n t e r C o n t r o l R e g i s t e r s; 4 . 4 H C o u n t e r C o n t r o l R e g i s t e r s; HCCNT0: H Counter Control Register 0; SEDG0: Polarity select for reset signal; SEDG1: Polarity select for reset signal; All other settings default to 1024 μs.

H C o u n t e r H C o u n t e r C o n t r o l R e g i s t e r s P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 310 Panasonic 1 4 . 4 H C o u n t e r C o n t r o l R e g i s t e r s All registers ...

Page 313 - R e g i s t e r M a p; A p p e n d i x A R e g i s t e r M a p; MSBs

R e g i s t e r M a p P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 312 Panasonic A p p e n d i x A R e g i s t e r M a p Table A-1 Register Map: x’007E00’ to x’007FFF’ (Registers in this area c...

Page 317 - M N 1 0 2 H F 7 5 K F l a s h E E P R O M V e r s i o n; A p p e n d i x B M N 1 0 2 H F 7 5 K F l a s h E E P RO M Ve r s i o n; is overwritten in PROM writer mode.; Figure B-1 Memory Map for Onboard Serial Programming Mode

M N 1 0 2 H F 7 5 K F l a s h E E P R O M V e r s i o n D e s c r i p t i o n P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 316 Panasonic A p p e n d i x B M N 1 0 2 H F 7 5 K F l a s h E E P RO...

Page 318 - B e n e f i t s; to the microcontroller pin states.

M N 1 0 2 H F 7 5 K F l a s h E E P R O M V e r s i o n B e n e f i t s M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 317 Panasonic B . 2 B e n e f i t s Because you can maintain and upgrade the...

Page 319 - U s i n g t h e P R O M W r i t e r M o d e

M N 1 0 2 H F 7 5 K F l a s h E E P R O M V e r s i o n U s i n g t h e P R O M W r i t e r M o d e P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 318 Panasonic Check the following web page of ou...

Page 320 - U s i n g t h e O n b o a r d S e r i a l P r o g r a m m i n g M o d e; Onboard serial writer; Television set

M N 1 0 2 H F 7 5 K F l a s h E E P R O M V e r s i o n U s i n g t h e O n b o a r d S e r i a l P r o g r a m m i n g M o d e M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 319 Panasonic B . 4 ...

Page 321 - C on figu rin g th e S ys tem for O nb oa rd Se ria l P ro gra m m ing; source to the target board. The serial writer supplies; Model: AF200 flash microcontroller programmer; Target board

M N 1 0 2 H F 7 5 K F l a s h E E P R O M V e r s i o n U s i n g t h e O n b o a r d S e r i a l P r o g r a m m i n g M o d e P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 320 Panasonic B .4 ....

Page 322 - C i r c u i t R e q u i r e m e n t s fo r t h e Ta r g e t B o a r d; Install a switch on the target board to toggle between V; supplied by the; for normal operation.; Figure B-6 Target Board – Serial Writer Connection; During normal microcontroller operation, V; should always be equal to; supply only when programming

M N 1 0 2 H F 7 5 K F l a s h E E P R O M V e r s i o n U s i n g t h e O n b o a r d S e r i a l P r o g r a m m i n g M o d e M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 321 Panasonic B . 4 ...

Page 324 - Do not write to this area.

M N 1 0 2 H F 7 5 K F l a s h E E P R O M V e r s i o n U s i n g t h e O n b o a r d S e r i a l P r o g r a m m i n g M o d e M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 323 Panasonic B . 4 ...

Page 325 - interrupt service routine.; M i c r o c o n t r o l l e r C l o c k o n t h e Ta r g e t B o a r d

M N 1 0 2 H F 7 5 K F l a s h E E P R O M V e r s i o n U s i n g t h e O n b o a r d S e r i a l P r o g r a m m i n g M o d e P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 324 Panasonic ■ Bran...

Page 326 - S e t t i n g U p t h e O n b o a r d S e r i a l P r o g r a m m i n g M o d e; To set up the serial writer interface:; SBT goes high on microcontroller power-up, for t

M N 1 0 2 H F 7 5 K F l a s h E E P R O M V e r s i o n U s i n g t h e O n b o a r d S e r i a l P r o g r a m m i n g M o d e M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 325 Panasonic B . 4 ...

Page 327 - Reset start

M N 1 0 2 H F 7 5 K F l a s h E E P R O M V e r s i o n U s i n g t h e O n b o a r d S e r i a l P r o g r a m m i n g M o d e P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 326 Panasonic ■ Star...

Page 328 - B r a n ch i n g t o t h e U s e r P r o g r a m; B . 4 . 7 . 1 B r a n c h i n g t o t h e R e s e t S t a r t R o u t i n e

M N 1 0 2 H F 7 5 K F l a s h E E P R O M V e r s i o n U s i n g t h e O n b o a r d S e r i a l P r o g r a m m i n g M o d e M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y 327 Panasonic B . 4 ...

Page 329 - R e p r o g r a m m i n g F l o w; R e p ro g r a m m i n g F l o w; Times indicated are minimum time requirements.

M N 1 0 2 H F 7 5 K F l a s h E E P R O M V e r s i o n R e p r o g r a m m i n g F l o w P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 328 Panasonic B . 5 R e p ro g r a m m i n g F l o w Figur...

Page 332 - Pin Descriptions

P a n a s o n i c S e m i c o n d u c t o r D e v e l o p m e n t C o m p a n y M N 1 0 2 H 7 5 K / F 7 5 K / 8 5 K / F 8 5 K L S I U s e r M a n u a l 2 Panasonic P30 1.6 Pin Descriptions 1 .6 . 1 MN 1 0 2 H 8 5 K Pi n D e s cr i p t i o n Notes: 1. Pins marked with an asterisk (*) are N-channel, o...

Page 337 - LSI User’s Manual

Issued by Matsushita Electric Industrial Co., Ltd.  Matsushita Electric Industrial Co., Ltd. MN102H75K/F75K/85K/F85K LSI User’s Manual October,2001 1st Edition 1st Printing

Page 338 - SALES OFFICES; NORTH AMERICA

Semiconductor Company, Matsushita Electric Industrial Co., Ltd. Nagaokakyo, Kyoto, 617-8520 Japan Tel: (075) 951-8151 http://www.panasonic.co.jp/semicon/ SALES OFFICES ■ NORTH AMERICA ● U.S.A. Sales Office: Panasonic Industrial Company [PIC] • New Jersey Office: Two Panasonic Way Secaucus, New Jerse...