AMD CS5536 - Manuals

2 AMD Geode™ LX Processor DDR2 BIOS Porting Guide 46959A - March 2009 Application Note 3.0 Solution The method for initializing DDR2 memory on the processoris to insert a CPLD and quick switches in the address andBA signals. Figure 3-1 shows a block diagram of thisdesign. During initialization, the ...

AMD Geode™ LX Processor DDR2 BIOS Porting Guide 3 46959A - March 2009 Application Note 3.2 CPLD Registers The CPLD contains two registers that indicate how itshould assert the BA[1:0], A[12:0] signals and switchenable signals. • If accessing the registers via I2C, the register addresses are 80h and ...

4 AMD Geode™ LX Processor DDR2 BIOS Porting Guide 46959A - March 2009 Application Note 3.3 Initialization Steps Some of the following steps may be optional, depending onthe specific implementation. The reader is encouraged tohave a copy of the JEDEC standard for DDR2 SDRAM,including the SPD byte def...